UefiCpuPkg MtrrLib: For MtrrSetAllMtrrs(), do not set FE/E bits in IA32_MTRR_DEF_TYPE...

Signed-off-by: Sun Rui <rui.sun@intel.com>
Reviewed-by: Fan Jeff <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13182 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
index bcf5e20459c3369e638a11513a5f9ab339abe9ec..b598d51b4b86c4c62724c50027ab1dc24fa9af02 100644 (file)
--- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
+++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   MTRR setting library\r
 \r
-  Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -203,26 +203,20 @@ PreMtrrChange (
   return Value;\r
 }\r
 \r
-\r
 /**\r
   Cleaning up after programming MTRRs.\r
 \r
   This function will do some clean up after programming MTRRs:\r
-  enable MTRR caching functionality, and enable cache\r
+  Flush all TLBs,  re-enable caching, restore CR4.\r
 \r
   @param  Cr4  CR4 value to restore\r
 \r
 **/\r
 VOID\r
-PostMtrrChange (\r
-  UINTN Cr4\r
+PostMtrrChangeEnableCache (\r
+  IN UINTN  Cr4\r
   )\r
 {\r
-  //\r
-  // Enable Cache MTRR\r
-  //\r
-  AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 3);\r
-\r
   //\r
   // Flush all TLBs \r
   //\r
@@ -239,6 +233,28 @@ PostMtrrChange (
   AsmWriteCr4 (Cr4);\r
 }\r
 \r
+/**\r
+  Cleaning up after programming MTRRs.\r
+\r
+  This function will do some clean up after programming MTRRs:\r
+  enable MTRR caching functionality, and enable cache\r
+\r
+  @param  Cr4  CR4 value to restore\r
+\r
+**/\r
+VOID\r
+PostMtrrChange (\r
+  IN UINTN  Cr4\r
+  )\r
+{\r
+  //\r
+  // Enable Cache MTRR\r
+  //\r
+  AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 3);\r
+\r
+  PostMtrrChangeEnableCache (Cr4);\r
+}\r
+\r
 \r
 /**\r
   Programs fixed MTRRs registers.\r
@@ -1502,7 +1518,7 @@ MtrrSetAllMtrrs (
   //\r
   AsmWriteMsr64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, MtrrSetting->MtrrDefType);\r
 \r
-  PostMtrrChange (Cr4);\r
+  PostMtrrChangeEnableCache (Cr4);\r
 \r
   return MtrrSetting;\r
 }\r