/** @file\r
PCI emumeration support functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
}\r
}\r
\r
+ PciIoDevice->ResizableBarOffset = 0;\r
+ if (PcdGetBool (PcdPcieResizableBarSupport)) {\r
+ Status = LocatePciExpressCapabilityRegBlock (\r
+ PciIoDevice,\r
+ PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID,\r
+ &PciIoDevice->ResizableBarOffset,\r
+ NULL\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;\r
+ UINT32 Offset;\r
+ Offset = PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)\r
+ + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY),\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ Offset,\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL),\r
+ &ResizableBarControl\r
+ );\r
+ PciIoDevice->ResizableBarNumber = ResizableBarControl.Bits.ResizableBarNumber;\r
+ PciProgramResizableBar (PciIoDevice, PciResizableBarMax);\r
+ }\r
+ }\r
+\r
//\r
// Initialize the reserved resource list\r
//\r
/** @file\r
Internal library implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
}\r
}\r
\r
+/**\r
+ Adjust the Devices' BAR size to minimum value if it support Resizeable BAR capability.\r
+\r
+ @param RootBridgeDev Pointer to instance of PCI_IO_DEVICE..\r
+\r
+ @return TRUE if BAR size is adjusted.\r
+\r
+**/\r
+BOOLEAN\r
+AdjustPciDeviceBarSize (\r
+ IN PCI_IO_DEVICE *RootBridgeDev\r
+ )\r
+{\r
+ PCI_IO_DEVICE *PciIoDevice;\r
+ LIST_ENTRY *CurrentLink;\r
+ BOOLEAN Adjusted;\r
+ UINTN Offset;\r
+ UINTN BarIndex;\r
+\r
+ Adjusted = FALSE;\r
+ CurrentLink = RootBridgeDev->ChildList.ForwardLink;\r
+\r
+ while (CurrentLink != NULL && CurrentLink != &RootBridgeDev->ChildList) {\r
+ PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
+\r
+ if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {\r
+ if (AdjustPciDeviceBarSize (PciIoDevice)) {\r
+ Adjusted = TRUE;\r
+ }\r
+ } else {\r
+ if (PciIoDevice->ResizableBarOffset != 0) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "PciBus: [%02x|%02x|%02x] Adjust Pci Device Bar Size\n",\r
+ PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber\r
+ ));\r
+ PciProgramResizableBar (PciIoDevice, PciResizableBarMin);\r
+ //\r
+ // Start to parse the bars\r
+ //\r
+ for (Offset = 0x10, BarIndex = 0; Offset <= 0x24 && BarIndex < PCI_MAX_BAR; BarIndex++) {\r
+ Offset = PciParseBar (PciIoDevice, Offset, BarIndex);\r
+ }\r
+ Adjusted = TRUE;\r
+ DEBUG_CODE (DumpPciBars (PciIoDevice););\r
+ }\r
+ }\r
+\r
+ CurrentLink = CurrentLink->ForwardLink;\r
+ }\r
+\r
+ return Adjusted;\r
+}\r
+\r
/**\r
Submits the I/O and memory resource requirements for the specified PCI Host Bridge.\r
\r
PCI_RESOURCE_NODE PMem64Pool;\r
EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;\r
EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
+ BOOLEAN ResizableBarNeedAdjust;\r
+ BOOLEAN ResizableBarAdjusted;\r
+\r
+ ResizableBarNeedAdjust = PcdGetBool (PcdPcieResizableBarSupport);\r
\r
//\r
// It may try several times if the resource allocation fails\r
sizeof (AllocFailExtendedData)\r
);\r
\r
- Status = PciHostBridgeAdjustAllocation (\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool,\r
- IoResStatus,\r
- Mem32ResStatus,\r
- PMem32ResStatus,\r
- Mem64ResStatus,\r
- PMem64ResStatus\r
- );\r
-\r
+ //\r
+ // When resource conflict happens, adjust the BAR size first.\r
+ // Only when adjusting BAR size doesn't help or BAR size cannot be adjusted,\r
+ // reject the device who requests largest resource that causes conflict.\r
+ //\r
+ ResizableBarAdjusted = FALSE;\r
+ if (ResizableBarNeedAdjust) {\r
+ ResizableBarAdjusted = AdjustPciDeviceBarSize (RootBridgeDev);\r
+ ResizableBarNeedAdjust = FALSE;\r
+ }\r
+ if (!ResizableBarAdjusted) {\r
+ Status = PciHostBridgeAdjustAllocation (\r
+ &IoPool,\r
+ &Mem32Pool,\r
+ &PMem32Pool,\r
+ &Mem64Pool,\r
+ &PMem64Pool,\r
+ IoResStatus,\r
+ Mem32ResStatus,\r
+ PMem32ResStatus,\r
+ Mem64ResStatus,\r
+ PMem64ResStatus\r
+ );\r
+ }\r
//\r
// Destroy all the resource tree\r
//\r
\r
return EFI_SUCCESS;\r
}\r
+\r
+/**\r
+ This function is used to program the Resizable BAR Register.\r
+\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r
+ @param ResizableBarOp PciResizableBarMax: Set BAR to max size\r
+ PciResizableBarMin: set BAR to min size.\r
+\r
+ @retval EFI_SUCCESS Successfully enumerated the host bridge.\r
+ @retval other Some error occurred when enumerating the host bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+PciProgramResizableBar (\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp\r
+ )\r
+{\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINT64 Capabilities;\r
+ UINT32 Index;\r
+ UINT32 Offset;\r
+ INTN Bit;\r
+ UINTN ResizableBarNumber;\r
+ EFI_STATUS Status;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Entries[PCI_MAX_BAR];\r
+\r
+ ASSERT (PciIoDevice->ResizableBarOffset != 0);\r
+\r
+ DEBUG ((DEBUG_INFO, " Programs Resizable BAR register, offset: 0x%08x, number: %d\n",\r
+ PciIoDevice->ResizableBarOffset, PciIoDevice->ResizableBarNumber));\r
+\r
+ ResizableBarNumber = MIN (PciIoDevice->ResizableBarNumber, PCI_MAX_BAR);\r
+ PciIo = &PciIoDevice->PciIo;\r
+ Status = PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) * ResizableBarNumber,\r
+ (VOID *)(&Entries)\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ for (Index = 0; Index < ResizableBarNumber; Index++) {\r
+\r
+ //\r
+ // When the bit of Capabilities Set, indicates that the Function supports\r
+ // operating with the BAR sized to (2^Bit) MB.\r
+ // Example:\r
+ // Bit 0 is set: supports operating with the BAR sized to 1 MB\r
+ // Bit 1 is set: supports operating with the BAR sized to 2 MB\r
+ // Bit n is set: supports operating with the BAR sized to (2^n) MB\r
+ //\r
+ Capabilities = LShiftU64(Entries[Index].ResizableBarControl.Bits.BarSizeCapability, 28)\r
+ | Entries[Index].ResizableBarCapability.Bits.BarSizeCapability;\r
+\r
+ if (ResizableBarOp == PciResizableBarMax) {\r
+ Bit = HighBitSet64(Capabilities);\r
+ } else if (ResizableBarOp == PciResizableBarMin) {\r
+ Bit = LowBitSet64(Capabilities);\r
+ } else {\r
+ ASSERT ((ResizableBarOp == PciResizableBarMax) || (ResizableBarOp == PciResizableBarMin));\r
+ }\r
+\r
+ ASSERT (Bit >= 0);\r
+\r
+ Offset = PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)\r
+ + Index * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY)\r
+ + OFFSET_OF (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY, ResizableBarControl);\r
+\r
+ Entries[Index].ResizableBarControl.Bits.BarSize = (UINT32) Bit;\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ " Resizable Bar: Offset = 0x%x, Bar Size Capability = 0x%016lx, New Bar Size = 0x%lx\n",\r
+ OFFSET_OF (PCI_TYPE00, Device.Bar[Entries[Index].ResizableBarControl.Bits.BarIndex]),\r
+ Capabilities, LShiftU64 (SIZE_1MB, Bit)\r
+ ));\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Offset,\r
+ 1,\r
+ &Entries[Index].ResizableBarControl.Uint32\r
+ );\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
/** @file\r
Internal library declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
UINT8 *AllocRes;\r
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;\r
\r
+typedef enum {\r
+ PciResizableBarMin = 0x00,\r
+ PciResizableBarMax = 0xFF\r
+} PCI_RESIZABLE_BAR_OPERATION;\r
\r
/**\r
Retrieve the PCI Card device BAR information via PciIo interface.\r
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
);\r
\r
+/**\r
+ This function is used to program the Resizable BAR Register.\r
+\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r
+ @param ResizableBarOp PciResizableBarMax: Set BAR to max size\r
+ PciResizableBarMin: set BAR to min size.\r
+\r
+ @retval EFI_SUCCESS Successfully enumerated the host bridge.\r
+ @retval other Some error occurred when enumerating the host bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+PciProgramResizableBar (\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp\r
+ );\r
#endif\r
# and libraries instances, which are used for those modules.\r
#\r
# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.\r
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>\r
# (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development LP<BR>\r
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
# @Prompt Enable StatusCode via memory.\r
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE|BOOLEAN|0x00010023\r
\r
+ ## Indicates if the PCIe Resizable BAR Capability Supported.<BR><BR>\r
+ # TRUE - PCIe Resizable BAR Capability is supported.<BR>\r
+ # FALSE - PCIe Resizable BAR Capability is not supported.<BR>\r
+ # @Prompt Enable PCIe Resizable BAR Capability support.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|TRUE|BOOLEAN|0x10000024\r
+\r
[PcdsPatchableInModule]\r
## Specify memory size with page number for PEI code when\r
# Loading Module at Fixed Address feature is enabled.\r
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