On MpCore system, the primary core can now be any core of the system.
To identify the primary core, you can use 'gArmTokenSpaceGuid.PcdArmPrimaryCoreMask'
and 'gArmTokenSpaceGuid.PcdArmPrimaryCore'.
These PCDs by default use the ClusterId and CoreId to identify the core. And the
primary core is defined as the ClusetrId=0 and CoreId=0.
The helper macros are: IS_PRIMARY_CORE(MpId), GET_CORE_ID(MpId), GET_CLUSTER_ID(MpId),
GET_CORE_POS(MpId), PRIMARY_CORE_ID.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12412
6f19259b-4bc3-4df7-8a09-
765794883524
24 files changed:
gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r
gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r
\r
gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r
gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r
\r
+ # Use ClusterId + CoreId to identify the PrimaryCore\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
+ # The Primary Core is ClusterId[0] & CoreId[0] \r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
+\r
#\r
# ARM MPCore MailBox PCDs\r
#\r
#\r
# ARM MPCore MailBox PCDs\r
#\r
ARM_PROCESSOR_MODE_MASK = 0x1F
} ARM_PROCESSOR_MODE;
ARM_PROCESSOR_MODE_MASK = 0x1F
} ARM_PROCESSOR_MODE;
+#define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
+#define GET_CORE_ID(MpId) ((MpId) & 0x3)
+#define GET_CLUSTER_ID(MpId) (((MpId) >> 6) & 0x3C)
+// Get the position of the core for the Stack Offset (4 Core per Cluster)
+// Position = (ClusterId * 4) + CoreId
+#define GET_CORE_POS(MpId) ((((MpId) >> 6) & 0x3C) + ((MpId) & 0x3))
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & 0x3)
+
ARM_CACHE_TYPE
EFIAPI
ArmCacheType (
ARM_CACHE_TYPE
EFIAPI
ArmCacheType (
**/
VOID
ArmPlatformSecExtraAction (
**/
VOID
ArmPlatformSecExtraAction (
OUT UINTN* JumpAddress
)
{
OUT UINTN* JumpAddress
)
{
**/
VOID
ArmPlatformSecExtraAction (
**/
VOID
ArmPlatformSecExtraAction (
OUT UINTN* JumpAddress
);
OUT UINTN* JumpAddress
);
\r
#include <PiPei.h>\r
\r
\r
#include <PiPei.h>\r
\r
+#include <Library/ArmLib.h>\r
#include <Library/ArmGicLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PrintLib.h>\r
#include <Library/SerialPortLib.h>\r
#include <Library/ArmGicLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PrintLib.h>\r
#include <Library/SerialPortLib.h>\r
-#include <Chipset/ArmV7.h>
-#define ARM_PRIMARY_CORE 0\r
+#include <Chipset/ArmV7.h>
\r
// When the firmware is built as not Standalone, the secondary cores need to wait the firmware\r
// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.\r
\r
// When the firmware is built as not Standalone, the secondary cores need to wait the firmware\r
// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.\r
ArmCallWFI();\r
\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
ArmCallWFI();\r
\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);\r
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
\r
// Jump to secondary core entry point.\r
secondary_start ();\r
\r
// Jump to secondary core entry point.\r
secondary_start ();\r
**/\r
VOID\r
ArmPlatformSecExtraAction (\r
**/\r
VOID\r
ArmPlatformSecExtraAction (\r
OUT UINTN* JumpAddress\r
)\r
{\r
OUT UINTN* JumpAddress\r
)\r
{\r
UINTN CharCount;\r
\r
if (FeaturePcdGet (PcdStandalone) == FALSE) {\r
UINTN CharCount;\r
\r
if (FeaturePcdGet (PcdStandalone) == FALSE) {\r
- if (CoreId == ARM_PRIMARY_CORE) {\r
+ if (IS_PRIMARY_CORE(MpId)) {\r
UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);\r
\r
// Patch the DRAM to make an infinite loop at the start address\r
UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);\r
\r
// Patch the DRAM to make an infinite loop at the start address\r
*JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
}\r
} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {\r
*JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
}\r
} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {\r
- if (CoreId == ARM_PRIMARY_CORE) {\r
+ if (IS_PRIMARY_CORE(MpId)) {\r
// Signal the secondary cores they can jump to PEI phase\r
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
\r
// Signal the secondary cores they can jump to PEI phase\r
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
\r
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
VOID\r
EFIAPI\r
SecondaryMain (\r
VOID\r
EFIAPI\r
SecondaryMain (\r
)\r
{\r
// Function pointer to Secondary Core entry point\r
)\r
{\r
// Function pointer to Secondary Core entry point\r
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
ArmCallWFI();\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
ArmCallWFI();\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
}\r
\r
secondary_start = (VOID (*)())secondary_entry_addr;\r
}\r
\r
secondary_start = (VOID (*)())secondary_entry_addr;\r
VOID\r
EFIAPI\r
SecondaryMain (\r
VOID\r
EFIAPI\r
SecondaryMain (\r
\r
VOID\r
CEntryPoint (\r
\r
VOID\r
CEntryPoint (\r
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
\r
//If not primary Jump to Secondary Main\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
\r
//If not primary Jump to Secondary Main\r
+ if (IS_PRIMARY_CORE(MpId)) {\r
// Initialize the Debug Agent for Source Level Debugging\r
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
SaveAndSetDebugTimerInterrupt (TRUE);\r
// Initialize the Debug Agent for Source Level Debugging\r
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
SaveAndSetDebugTimerInterrupt (TRUE);\r
// Goto primary Main.\r
PrimaryMain (PeiCoreEntryPoint);\r
} else {\r
// Goto primary Main.\r
PrimaryMain (PeiCoreEntryPoint);\r
} else {\r
- SecondaryMain (CoreId);\r
+ SecondaryMain (MpId);\r
}\r
\r
// PEI Core should always load and never return\r
}\r
\r
// PEI Core should always load and never return\r
VOID\r
EFIAPI\r
SecondaryMain (\r
VOID\r
EFIAPI\r
SecondaryMain (\r
-#global symbols referenced by this module\r
GCC_ASM_IMPORT(CEntryPoint)\r
GCC_ASM_IMPORT(CEntryPoint)\r
-\r
-StartupAddr: .word CEntryPoint\r
-\r
-#make _ModuleEntryPoint as global\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
+StartupAddr: .word CEntryPoint\r
\r
ASM_PFX(_ModuleEntryPoint):\r
# Identify CPU ID\r
\r
ASM_PFX(_ModuleEntryPoint):\r
# Identify CPU ID\r
- mrc p15, 0, r0, c0, c0, 5\r
- and r0, #0xf\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r0, r0, r1\r
\r
_SetupStack:\r
# Setup Stack for the 4 CPU cores\r
\r
_SetupStack:\r
# Setup Stack for the 4 CPU cores\r
INCLUDE AsmMacroIoLib.inc\r
\r
IMPORT CEntryPoint\r
INCLUDE AsmMacroIoLib.inc\r
\r
IMPORT CEntryPoint\r
EXPORT _ModuleEntryPoint\r
\r
PRESERVE8\r
EXPORT _ModuleEntryPoint\r
\r
PRESERVE8\r
\r
_ModuleEntryPoint\r
// Identify CPU ID\r
\r
_ModuleEntryPoint\r
// Identify CPU ID\r
- mrc p15, 0, r0, c0, c0, 5\r
- and r0, #0xf\r
+ bl ArmReadMpidr\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r0, r0, r1\r
\r
_SetupStack\r
// Setup Stack for the 4 CPU cores\r
\r
_SetupStack\r
// Setup Stack for the 4 CPU cores\r
ldr r2, StartupAddr\r
\r
// jump to PrePeiCore C code\r
ldr r2, StartupAddr\r
\r
// jump to PrePeiCore C code\r
// r1 = pei_core_address\r
blx r2\r
\r
// r1 = pei_core_address\r
blx r2\r
\r
gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
gArmTokenSpaceGuid.PcdNormalFvSize\r
\r
gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
gArmTokenSpaceGuid.PcdNormalFvSize\r
\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
+\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize\r
\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize\r
\r
\r
VOID\r
SecondaryMain (\r
\r
VOID\r
SecondaryMain (\r
)\r
{\r
// Function pointer to Secondary Core entry point\r
)\r
{\r
// Function pointer to Secondary Core entry point\r
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
ArmCallWFI();\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
ArmCallWFI();\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
}\r
\r
secondary_start = (VOID (*)())secondary_entry_addr;\r
}\r
\r
secondary_start = (VOID (*)())secondary_entry_addr;\r
\r
VOID\r
SecondaryMain (\r
\r
VOID\r
SecondaryMain (\r
)\r
{\r
// We must never get into this function on UniCore system\r
)\r
{\r
// We must never get into this function on UniCore system\r
\r
# Global symbols referenced by this module\r
GCC_ASM_IMPORT(CEntryPoint)\r
\r
# Global symbols referenced by this module\r
GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
StartupAddr: .word CEntryPoint\r
\r
\r
ASM_PFX(_ModuleEntryPoint):\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
StartupAddr: .word CEntryPoint\r
\r
\r
ASM_PFX(_ModuleEntryPoint):\r
- // Identify CPU ID\r
- mrc p15, 0, r0, c0, c0, 5\r
- and r0, #0xf\r
+ // Get ID of this CPU in Multicore system\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r0, r0, r1\r
\r
_SetSVCMode:\r
// Enter SVC mode\r
\r
_SetSVCMode:\r
// Enter SVC mode\r
ldr r2, StartupAddr\r
\r
// Jump to PrePiCore C code\r
ldr r2, StartupAddr\r
\r
// Jump to PrePiCore C code\r
// r1 = UefiMemoryBase\r
blx r2\r
\r
// r1 = UefiMemoryBase\r
blx r2\r
\r
INCLUDE AsmMacroIoLib.inc\r
\r
IMPORT CEntryPoint\r
INCLUDE AsmMacroIoLib.inc\r
\r
IMPORT CEntryPoint\r
EXPORT _ModuleEntryPoint\r
\r
PRESERVE8\r
EXPORT _ModuleEntryPoint\r
\r
PRESERVE8\r
StartupAddr DCD CEntryPoint\r
\r
_ModuleEntryPoint\r
StartupAddr DCD CEntryPoint\r
\r
_ModuleEntryPoint\r
- // Identify CPU ID\r
- mrc p15, 0, r0, c0, c0, 5\r
- and r0, #0xf\r
+ // Get ID of this CPU in Multicore system\r
+ bl ArmReadMpidr\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
\r
_SetSVCMode\r
// Enter SVC mode\r
\r
_SetSVCMode\r
// Enter SVC mode\r
ldr r2, StartupAddr\r
\r
// Jump to PrePiCore C code\r
ldr r2, StartupAddr\r
\r
// Jump to PrePiCore C code\r
// r1 = UefiMemoryBase\r
blx r2\r
\r
// r1 = UefiMemoryBase\r
blx r2\r
\r
gArmTokenSpaceGuid.PcdSystemMemorySize\r
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\r
\r
gArmTokenSpaceGuid.PcdSystemMemorySize\r
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\r
\r
- gArmPlatformTokenSpaceGuid.PcdMPCoreMaxCores\r
+ gArmPlatformTokenSpaceGuid.PcdClusterCount\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
+\r
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize\r
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize\r
\r
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize\r
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize\r
\r
\r
VOID\r
CEntryPoint (\r
\r
VOID\r
CEntryPoint (\r
IN UINTN UefiMemoryBase\r
)\r
{\r
UINT64 StartTimeStamp;\r
\r
IN UINTN UefiMemoryBase\r
)\r
{\r
UINT64 StartTimeStamp;\r
\r
- if ((CoreId == ARM_PRIMARY_CORE) && PerformanceMeasurementEnabled ()) {\r
+ if (IS_PRIMARY_CORE(MpId) && PerformanceMeasurementEnabled ()) {\r
// Initialize the Timer Library to setup the Timer HW controller\r
TimerConstructor ();\r
// We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
// Initialize the Timer Library to setup the Timer HW controller\r
TimerConstructor ();\r
// We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
ArmWriteVBar ((UINT32)PrePiVectorTable);\r
\r
// If not primary Jump to Secondary Main\r
ArmWriteVBar ((UINT32)PrePiVectorTable);\r
\r
// If not primary Jump to Secondary Main\r
- if (CoreId == ARM_PRIMARY_CORE) {\r
+ if (IS_PRIMARY_CORE(MpId)) {\r
// Goto primary Main.\r
PrimaryMain (UefiMemoryBase, StartTimeStamp);\r
} else {\r
// Goto primary Main.\r
PrimaryMain (UefiMemoryBase, StartTimeStamp);\r
} else {\r
- SecondaryMain (CoreId);\r
+ SecondaryMain (MpId);\r
}\r
\r
// DXE Core should always load and never return\r
}\r
\r
// DXE Core should always load and never return\r
\r
#include <Chipset/ArmV7.h>\r
\r
\r
#include <Chipset/ArmV7.h>\r
\r
-#define ARM_PRIMARY_CORE 0\r
#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);\r
\r
// Vector Table for PrePi Phase\r
#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);\r
\r
// Vector Table for PrePi Phase\r
\r
VOID\r
SecondaryMain (\r
\r
VOID\r
SecondaryMain (\r
);\r
\r
// Either implemented by PrePiLib or by MemoryInitPei\r
);\r
\r
// Either implemented by PrePiLib or by MemoryInitPei\r
#include <Chipset/ArmV7.h>
#include <Library/ArmGicLib.h>
#include <Chipset/ArmV7.h>
#include <Library/ArmGicLib.h>
-#define ARM_PRIMARY_CORE 0
-
#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
extern VOID *monitor_vector_table;
#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
extern VOID *monitor_vector_table;
UINTN JumpAddress;
// Primary CPU clears out the SCU tag RAMs, secondaries wait
UINTN JumpAddress;
// Primary CPU clears out the SCU tag RAMs, secondaries wait
- if (CoreId == ARM_PRIMARY_CORE) {
+ if (IS_PRIMARY_CORE(MpId)) {
if (FixedPcdGet32(PcdMPCoreSupport)) {
ArmInvalidScu();
}
if (FixedPcdGet32(PcdMPCoreSupport)) {
ArmInvalidScu();
}
- if (CoreId == ARM_PRIMARY_CORE) {
+ if (IS_PRIMARY_CORE(MpId)) {
// Initialize peripherals that must be done at the early stage
// Example: Some L2x0 controllers must be initialized in Secure World
ArmPlatformSecInitialize ();
// Initialize peripherals that must be done at the early stage
// Example: Some L2x0 controllers must be initialized in Secure World
ArmPlatformSecInitialize ();
if (ArmPlatformTrustzoneSupported()) {
if (FixedPcdGet32(PcdMPCoreSupport)) {
// Setup SMP in Non Secure world
if (ArmPlatformTrustzoneSupported()) {
if (FixedPcdGet32(PcdMPCoreSupport)) {
// Setup SMP in Non Secure world
- ArmSetupSmpNonSecure (CoreId);
+ ArmSetupSmpNonSecure (GET_CORE_ID(MpId));
- enter_monitor_mode((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * CoreId)));
+ enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * GET_CORE_POS(MpId))));
//Write the monitor mode vector table address
ArmWriteVMBar((UINT32) &monitor_vector_table);
//-------------------- Monitor Mode ---------------------
// Setup the Trustzone Chipsets
//Write the monitor mode vector table address
ArmWriteVMBar((UINT32) &monitor_vector_table);
//-------------------- Monitor Mode ---------------------
// Setup the Trustzone Chipsets
- if (CoreId == ARM_PRIMARY_CORE) {
+ if (IS_PRIMARY_CORE(MpId)) {
ArmPlatformTrustzoneInit();
// Wake up the secondary cores by sending a interrupt to everyone else
ArmPlatformTrustzoneInit();
// Wake up the secondary cores by sending a interrupt to everyone else
// security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
ArmWriteScr(SCR_NS | SCR_FW | SCR_AW);
} else {
// security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
ArmWriteScr(SCR_NS | SCR_FW | SCR_AW);
} else {
- if (CoreId == ARM_PRIMARY_CORE) {
+ if (IS_PRIMARY_CORE(MpId)) {
SerialPrint ("Trust Zone Configuration is disabled\n\r");
}
// Trustzone is not enabled, just enable the Distributor and CPU interface
SerialPrint ("Trust Zone Configuration is disabled\n\r");
}
// Trustzone is not enabled, just enable the Distributor and CPU interface
- if (CoreId == ARM_PRIMARY_CORE) {
+ if (IS_PRIMARY_CORE(MpId)) {
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
}
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
}
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
}
JumpAddress = PcdGet32 (PcdNormalFvBaseAddress);
}
JumpAddress = PcdGet32 (PcdNormalFvBaseAddress);
- ArmPlatformSecExtraAction (CoreId, &JumpAddress);
+ ArmPlatformSecExtraAction (MpId, &JumpAddress);
return_from_exception (JumpAddress);
//-------------------- Non Secure Mode ---------------------
return_from_exception (JumpAddress);
//-------------------- Non Secure Mode ---------------------
gArmTokenSpaceGuid.PcdVFPEnabled
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
gArmTokenSpaceGuid.PcdVFPEnabled
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
GCC_ASM_IMPORT(ArmDisableInterrupts)\r
GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
GCC_ASM_IMPORT(ArmWriteVBar)\r
GCC_ASM_IMPORT(ArmDisableInterrupts)\r
GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
GCC_ASM_IMPORT(ArmWriteVBar)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_IMPORT(SecVectorTable)\r
\r
#if (FixedPcdGet32(PcdMPCoreSupport))\r
GCC_ASM_IMPORT(SecVectorTable)\r
\r
#if (FixedPcdGet32(PcdMPCoreSupport))\r
_IdentifyCpu: \r
# Identify CPU ID\r
bl ASM_PFX(ArmReadMpidr)\r
_IdentifyCpu: \r
# Identify CPU ID\r
bl ASM_PFX(ArmReadMpidr)\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
\r
#get ID of this CPU in Multicore system\r
\r
#get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)\r
+ cmp r5, r1\r
# Only the primary core initialize the memory (SMC)\r
beq _InitMem\r
\r
# Only the primary core initialize the memory (SMC)\r
beq _InitMem\r
\r
_IdentifyCpu
// Identify CPU ID
bl ArmReadMpidr
_IdentifyCpu
// Identify CPU ID
bl ArmReadMpidr
+ // Get ID of this CPU in Multicore system
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
+ and r5, r0, r1
- //get ID of this CPU in Multicore system
- cmp r5, #0
+ // Is it the Primary Core ?
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
+ cmp r5, r1
// Only the primary core initialize the memory (SMC)
beq _InitMem
// Only the primary core initialize the memory (SMC)
beq _InitMem
ldr r3, StartupAddr
// Jump to SEC C code
ldr r3, StartupAddr
// Jump to SEC C code