## @file\r
# CPU Exception Handler library instance for DXE modules.\r
#\r
-# Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
MODULE_UNI_FILE = DxeCpuExceptionHandlerLib.uni\r
FILE_GUID = B6E9835A-EDCF-4748-98A8-27D3C722E02D\r
MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
+ VERSION_STRING = 1.1\r
LIBRARY_CLASS = CpuExceptionHandlerLib|DXE_CORE DXE_DRIVER UEFI_APPLICATION\r
\r
#\r
#------------------------------------------------------------------------------\r
#*\r
-#* Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>\r
+#* Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
#* This program and the accompanying materials\r
#* are licensed and made available under the terms and conditions of the BSD License\r
#* which accompanies this distribution. The full text of the license may be found at\r
pushl %eax\r
\r
#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
+## insure FXSAVE/FXRSTOR is enabled in CR4...\r
+## ... while we're at it, make sure DE is also enabled...\r
+ mov $1, %eax\r
+ pushl %ebx # temporarily save value of ebx on stack \r
+ cpuid # use CPUID to determine if FXSAVE/FXRESTOR\r
+ # and DE are supported\r
+ popl %ebx # retore value of ebx that was overwritten\r
+ # by CPUID \r
movl %cr4, %eax\r
- orl $0x208, %eax\r
+ pushl %eax # push cr4 firstly\r
+ testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support\r
+ jz L1\r
+ orl $BIT9, %eax # Set CR4.OSFXSR\r
+L1: \r
+ testl $BIT2, %edx # Test for Debugging Extensions support\r
+ jz L2\r
+ orl $BIT3, %eax # Set CR4.DE\r
+L2: \r
movl %eax, %cr4\r
- pushl %eax\r
movl %cr3, %eax\r
pushl %eax\r
movl %cr2, %eax\r
#; FX_SAVE_STATE_IA32 FxSaveState;\r
subl $512, %esp\r
movl %esp, %edi\r
+ testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support. \r
+ # edx still contains result from CPUID above\r
+ jz L3\r
.byte 0x0f, 0x0ae, 0x07 #fxsave [edi]\r
+L3: \r
\r
#; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
cld\r
\r
#; FX_SAVE_STATE_IA32 FxSaveState;\r
movl %esp, %esi\r
+ movl $1, %eax\r
+ cpuid # use CPUID to determine if FXSAVE/FXRESTOR \r
+ # are supported\r
+ testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support\r
+ jz L4\r
.byte 0x0f, 0x0ae, 0x0e # fxrstor [esi]\r
+L4: \r
addl $512, %esp\r
\r
#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
push eax\r
\r
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
+ mov eax, 1\r
+ push ebx ; temporarily save value of ebx on stack \r
+ cpuid ; use CPUID to determine if FXSAVE/FXRESTOR and DE \r
+ ; are supported\r
+ pop ebx ; retore value of ebx that was overwritten by CPUID \r
mov eax, cr4\r
- or eax, 208h\r
+ push eax ; push cr4 firstly\r
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support\r
+ jz @F\r
+ or eax, BIT9 ; Set CR4.OSFXSR\r
+@@: \r
+ test edx, BIT2 ; Test for Debugging Extensions support\r
+ jz @F\r
+ or eax, BIT3 ; Set CR4.DE\r
+@@: \r
mov cr4, eax\r
- push eax\r
mov eax, cr3\r
push eax\r
mov eax, cr2\r
;; FX_SAVE_STATE_IA32 FxSaveState;\r
sub esp, 512\r
mov edi, esp\r
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.\r
+ ; edx still contains result from CPUID above\r
+ jz @F\r
db 0fh, 0aeh, 07h ;fxsave [edi]\r
+@@: \r
\r
;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
cld\r
\r
;; FX_SAVE_STATE_IA32 FxSaveState;\r
mov esi, esp\r
+ mov eax, 1\r
+ cpuid ; use CPUID to determine if FXSAVE/FXRESTOR\r
+ ; are supported\r
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support\r
+ jz @F\r
db 0fh, 0aeh, 0eh ; fxrstor [esi]\r
+@@: \r
add esp, 512\r
\r
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
## @file\r
# CPU Exception Handler library instance for SEC/PEI modules.\r
#\r
-# Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
MODULE_UNI_FILE = SecPeiCpuExceptionHandlerLib.uni\r
FILE_GUID = CA4BBC99-DFC6-4234-B553-8B6586B7B113\r
MODULE_TYPE = PEIM\r
- VERSION_STRING = 1.0\r
+ VERSION_STRING = 1.1\r
LIBRARY_CLASS = CpuExceptionHandlerLib|SEC PEI_CORE PEIM\r
\r
#\r
## @file\r
# CPU Exception Handler library instance for SMM modules.\r
#\r
-# Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
MODULE_UNI_FILE = SmmCpuExceptionHandlerLib.uni\r
FILE_GUID = 8D2C439B-3981-42ff-9CE5-1B50ECA502D6\r
MODULE_TYPE = DXE_SMM_DRIVER\r
- VERSION_STRING = 1.0\r
+ VERSION_STRING = 1.1\r
LIBRARY_CLASS = CpuExceptionHandlerLib|DXE_SMM_DRIVER\r
\r
#\r