## The value should be a multiple of 4KB.\r
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x30000005\r
\r
- ## The PCD is used to specify memory size with page number for a pre-allocated ACPI NVS memory to be used\r
+ ## The PCD is used to specify memory size with page number for a pre-allocated reserved memory to be used\r
# by PEI in S3 phase. The default size 32K. When changing the value of this PCD, the platform\r
# developer should make sure the memory size is large enough to meet PEI requiremnt in S3 phase.\r
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|0x30000006\r
};\r
\r
/**\r
- Allocate EfiACPIMemoryNVS below 4G memory address.\r
+ Allocate memory below 4G memory address.\r
\r
- This function allocates EfiACPIMemoryNVS below 4G memory address.\r
+ This function allocates memory below 4G memory address.\r
\r
+ @param MemoryType Memory type of memory to allocate.\r
@param Size Size of memory to allocate.\r
\r
@return Allocated address for output.\r
\r
**/\r
VOID*\r
-AllocateAcpiNvsMemoryBelow4G (\r
- IN UINTN Size\r
+AllocateMemoryBelow4G (\r
+ IN UINTN MemoryType,\r
+ IN UINTN Size\r
)\r
{\r
UINTN Pages;\r
\r
Status = gBS->AllocatePages (\r
AllocateMaxAddress,\r
- EfiACPIMemoryNVS,\r
+ MemoryType,\r
Pages,\r
&Address\r
);\r
UINT32 RegEax;\r
UINT32 RegEdx;\r
UINT8 PhysicalAddressBits;\r
- EFI_PHYSICAL_ADDRESS PageAddress;\r
- UINTN IndexOfPml4Entries;\r
- UINTN IndexOfPdpEntries;\r
- UINTN IndexOfPageDirectoryEntries;\r
UINT32 NumberOfPml4EntriesNeeded;\r
UINT32 NumberOfPdpEntriesNeeded;\r
- PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;\r
- PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;\r
- PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;\r
- PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
EFI_PHYSICAL_ADDRESS S3NvsPageTableAddress;\r
UINTN TotalPageTableSize;\r
VOID *Hob;\r
BOOLEAN Page1GSupport;\r
- PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;\r
\r
Page1GSupport = FALSE;\r
if (PcdGetBool(PcdUse1GPageTable)) {\r
DEBUG ((EFI_D_ERROR, "TotalPageTableSize - %x pages\n", TotalPageTableSize));\r
\r
//\r
- // By architecture only one PageMapLevel4 exists - so lets allocate storgage for it.\r
+ // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
//\r
- S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateAcpiNvsMemoryBelow4G (EFI_PAGES_TO_SIZE(TotalPageTableSize));\r
+ S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, EFI_PAGES_TO_SIZE(TotalPageTableSize));\r
ASSERT (S3NvsPageTableAddress != 0);\r
- PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)(UINTN)S3NvsPageTableAddress;\r
- S3NvsPageTableAddress += SIZE_4KB;\r
-\r
- PageMapLevel4Entry = PageMap;\r
- PageAddress = 0;\r
- for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
- //\r
- // Each PML4 entry points to a page of Page Directory Pointer entires.\r
- // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
- //\r
- PageDirectoryPointerEntry = (PAGE_MAP_AND_DIRECTORY_POINTER *)(UINTN)S3NvsPageTableAddress;\r
- S3NvsPageTableAddress += SIZE_4KB;\r
- //\r
- // Make a PML4 Entry\r
- //\r
- PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
- PageMapLevel4Entry->Bits.ReadWrite = 1;\r
- PageMapLevel4Entry->Bits.Present = 1;\r
- \r
- if (Page1GSupport) {\r
- PageDirectory1GEntry = (PAGE_TABLE_1G_ENTRY *)(UINTN)PageDirectoryPointerEntry;\r
- \r
- for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {\r
- //\r
- // Fill in the Page Directory entries\r
- //\r
- PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;\r
- PageDirectory1GEntry->Bits.ReadWrite = 1;\r
- PageDirectory1GEntry->Bits.Present = 1;\r
- PageDirectory1GEntry->Bits.MustBe1 = 1;\r
- }\r
- } else {\r
- for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
- //\r
- // Each Directory Pointer entries points to a page of Page Directory entires.\r
- // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
- // \r
- PageDirectoryEntry = (PAGE_TABLE_ENTRY *)(UINTN)S3NvsPageTableAddress;\r
- S3NvsPageTableAddress += SIZE_4KB;\r
- \r
- //\r
- // Fill in a Page Directory Pointer Entries\r
- //\r
- PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
- PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
- PageDirectoryPointerEntry->Bits.Present = 1;\r
- \r
- for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {\r
- //\r
- // Fill in the Page Directory entries\r
- //\r
- PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
- PageDirectoryEntry->Bits.ReadWrite = 1;\r
- PageDirectoryEntry->Bits.Present = 1;\r
- PageDirectoryEntry->Bits.MustBe1 = 1;\r
- }\r
- }\r
- }\r
- }\r
- return (EFI_PHYSICAL_ADDRESS) (UINTN) PageMap;\r
+ return S3NvsPageTableAddress;\r
} else {\r
//\r
// If DXE is running 32-bit mode, no need to establish page table.\r
}\r
AlreadyEntered = TRUE;\r
\r
- AcpiS3Context = AllocateAcpiNvsMemoryBelow4G (sizeof(*AcpiS3Context));\r
+ AcpiS3Context = AllocateMemoryBelow4G (EfiReservedMemoryType, sizeof(*AcpiS3Context));\r
ASSERT (AcpiS3Context != NULL);\r
AcpiS3ContextBuffer = (EFI_PHYSICAL_ADDRESS)(UINTN)AcpiS3Context;\r
\r
AcpiS3Context->AcpiFacsTable = (EFI_PHYSICAL_ADDRESS)(UINTN)FindAcpiFacsTable ();\r
ASSERT (AcpiS3Context->AcpiFacsTable != 0);\r
\r
- IdtGate = AllocateAcpiNvsMemoryBelow4G (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 0x100 + sizeof(IA32_DESCRIPTOR));\r
+ IdtGate = AllocateMemoryBelow4G (EfiReservedMemoryType, sizeof(IA32_IDT_GATE_DESCRIPTOR) * 0x100 + sizeof(IA32_DESCRIPTOR));\r
Idtr = (IA32_DESCRIPTOR *)(IdtGate + 0x100);\r
Idtr->Base = (UINTN)IdtGate;\r
Idtr->Limit = (UINT16)(sizeof(IA32_IDT_GATE_DESCRIPTOR) * 0x100 - 1);\r
// Allocate stack\r
//\r
AcpiS3Context->BootScriptStackSize = PcdGet32 (PcdS3BootScriptStackSize);\r
- AcpiS3Context->BootScriptStackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateAcpiNvsMemoryBelow4G (PcdGet32 (PcdS3BootScriptStackSize));\r
+ AcpiS3Context->BootScriptStackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, PcdGet32 (PcdS3BootScriptStackSize));\r
ASSERT (AcpiS3Context->BootScriptStackBase != 0);\r
\r
//\r
// Allocate a code buffer < 4G for S3 debug to load external code, set invalid code instructions in it.\r
//\r
- AcpiS3Context->S3DebugBufferAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateAcpiNvsMemoryBelow4G (EFI_PAGE_SIZE);\r
+ AcpiS3Context->S3DebugBufferAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, EFI_PAGE_SIZE);\r
SetMem ((VOID *)(UINTN)AcpiS3Context->S3DebugBufferAddress, EFI_PAGE_SIZE, 0xff);\r
\r
DEBUG((EFI_D_INFO, "AcpiS3Context: AcpiFacsTable is 0x%8x\n", AcpiS3Context->AcpiFacsTable));\r
This is an implementation of the ACPI S3 Save protocol. This is defined in \r
S3 boot path specification 0.9.\r
\r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
#ifndef _ACPI_S3_SAVE_H_\r
#define _ACPI_S3_SAVE_H_\r
\r
-#pragma pack(1)\r
-\r
-typedef union {\r
- struct {\r
- UINT32 LimitLow : 16;\r
- UINT32 BaseLow : 16;\r
- UINT32 BaseMid : 8;\r
- UINT32 Type : 4;\r
- UINT32 System : 1;\r
- UINT32 Dpl : 2;\r
- UINT32 Present : 1;\r
- UINT32 LimitHigh : 4;\r
- UINT32 Software : 1;\r
- UINT32 Reserved : 1;\r
- UINT32 DefaultSize : 1;\r
- UINT32 Granularity : 1;\r
- UINT32 BaseHigh : 8;\r
- } Bits;\r
- UINT64 Uint64;\r
-} IA32_GDT;\r
-\r
-typedef struct {\r
- IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;\r
- UINT32 Offset32To63;\r
- UINT32 Reserved;\r
-} X64_IDT_GATE_DESCRIPTOR;\r
-\r
-//\r
-// Page-Map Level-4 Offset (PML4) and\r
-// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
-//\r
-\r
-typedef union {\r
- struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Reserved:1; // Reserved\r
- UINT64 MustBeZero:2; // Must Be Zero\r
- UINT64 Available:3; // Available for use by system software\r
- UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
- UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // No Execute bit\r
- } Bits;\r
- UINT64 Uint64;\r
-} PAGE_MAP_AND_DIRECTORY_POINTER;\r
-\r
-//\r
-// Page Table Entry 2MB\r
-//\r
-typedef union {\r
- struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
- UINT64 Available:3; // Available for use by system software\r
- UINT64 PAT:1; //\r
- UINT64 MustBeZero:8; // Must be zero;\r
- UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
- UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
- } Bits;\r
- UINT64 Uint64;\r
-} PAGE_TABLE_ENTRY;\r
-\r
-//\r
-// Page Table Entry 1GB\r
-//\r
-typedef union {\r
- struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
- UINT64 Available:3; // Available for use by system software\r
- UINT64 PAT:1; //\r
- UINT64 MustBeZero:17; // Must be zero;\r
- UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
- UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
- } Bits;\r
- UINT64 Uint64;\r
-} PAGE_TABLE_1G_ENTRY;\r
-\r
-#pragma pack()\r
-\r
/**\r
Gets the buffer of legacy memory below 1 MB \r
This function is to get the buffer in legacy memory below 1MB that is required during S3 resume.\r
/** @file\r
This is an implementation of the AcpiVariable platform field for ECP platform.\r
\r
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
ACPI_VARIABLE_SET_COMPATIBILITY *mAcpiVariableSetCompatibility = NULL;\r
\r
/**\r
- Allocate EfiACPIMemoryNVS below 4G memory address.\r
+ Allocate memory below 4G memory address.\r
\r
- This function allocates EfiACPIMemoryNVS below 4G memory address.\r
+ This function allocates memory below 4G memory address.\r
\r
+ @param MemoryType Memory type of memory to allocate.\r
@param Size Size of memory to allocate.\r
\r
@return Allocated address for output.\r
\r
**/\r
VOID*\r
-AllocateAcpiNvsMemoryBelow4G (\r
- IN UINTN Size\r
+AllocateMemoryBelow4G (\r
+ IN UINTN MemoryType,\r
+ IN UINTN Size\r
);\r
\r
/**\r
//\r
// Allocate ACPI reserved memory under 4G\r
//\r
- AcpiMemoryBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateAcpiNvsMemoryBelow4G (PcdGet32 (PcdS3AcpiReservedMemorySize));\r
+ AcpiMemoryBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, PcdGet32 (PcdS3AcpiReservedMemorySize));\r
ASSERT (AcpiMemoryBase != 0);\r
AcpiMemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);\r
\r
// Allocate/initialize the compatible version of Acpi Variable Set since Framework chipset/platform \r
// driver need this variable\r
//\r
- mAcpiVariableSetCompatibility = AllocateAcpiNvsMemoryBelow4G (sizeof(ACPI_VARIABLE_SET_COMPATIBILITY));\r
+ mAcpiVariableSetCompatibility = AllocateMemoryBelow4G (EfiACPIMemoryNVS, sizeof(ACPI_VARIABLE_SET_COMPATIBILITY));\r
Status = gRT->SetVariable (\r
ACPI_GLOBAL_VARIABLE,\r
&gEfiAcpiVariableCompatiblityGuid,\r
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