The register address of GICR_IPRIORITYR is in SGI_base frame. Add
IPRIORITY_ADDRESS macro for getting GICR_IPRIORITYR address. Otherwise
GIC RAS error(Uncorrected software error) may report in ArmGicDxe.
This resolves BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3236
Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Tested-by: Ard Biesheuvel <ardb@kernel.org> # QEMU/kvm guest on ThunderX2
Tested-by: Quan Nguyen <quan@os.amperecomputing.com>
#define ICENABLER_ADDRESS(base,offset) ((base) + \\r
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))\r
\r
+#define IPRIORITY_ADDRESS(base,offset) ((base) + \\r
+ ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))\r
+\r
/**\r
*\r
* Return whether the Source interrupt index refers to a shared interrupt (SPI)\r
}\r
\r
MmioAndThenOr32 (\r
- GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),\r
+ IPRIORITY_ADDRESS (GicCpuRedistributorBase, RegOffset),\r
~(0xff << RegShift),\r
Priority << RegShift\r
);\r