UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008

MpInitLib is the library that's responsible to wake up APs to provide
MP PPI and Protocol services.

The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57.
Without this change, AP may enter to GP fault when BSP's 5-level page
table is set to AP during AP wakes up.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index a1ad665564110cbeebb0d6570bdd4d2d2b926424..d6f84c6f45c02c551d63aa30822f4a34a4d45bf3 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -790,6 +790,7 @@ FillExchangeInfoData (
   volatile MP_CPU_EXCHANGE_INFO    *ExchangeInfo;\r
   UINTN                            Size;\r
   IA32_SEGMENT_DESCRIPTOR          *Selector;\r
+  IA32_CR4                         Cr4;\r
 \r
   ExchangeInfo                  = CpuMpData->MpCpuExchangeInfo;\r
   ExchangeInfo->Lock            = 0;\r
@@ -814,6 +815,18 @@ FillExchangeInfoData (
 \r
   ExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;\r
 \r
+  //\r
+  // We can check either CPUID(7).ECX[bit16] or check CR4.LA57[bit12]\r
+  //  to determin whether 5-Level Paging is enabled.\r
+  // CPUID(7).ECX[bit16] shows CPU's capability, CR4.LA57[bit12] shows\r
+  // current system setting.\r
+  // Using latter way is simpler because it also eliminates the needs to\r
+  //  check whether platform wants to enable it.\r
+  //\r
+  Cr4.UintN = AsmReadCr4 ();\r
+  ExchangeInfo->Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
+  DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging));\r
+\r
   //\r
   // Get the BSP's data of GDT and IDT\r
   //\r

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index effa235778d55583db5928894384c4a72195801c..4b12f91d47dc49e44dabe93aa90200bd981119f3 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -185,6 +185,10 @@ typedef struct {
   UINT16                ModeTransitionSegment;\r
   UINT32                ModeHighMemory;\r
   UINT16                ModeHighSegment;\r
+  //\r
+  // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.\r
+  //\r
+  BOOLEAN               Enable5LevelPaging;\r
 } MP_CPU_EXCHANGE_INFO;\r
 \r
 #pragma pack()\r

diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc
index 467f54a8602e3afcc4ddff52a6d0355b9ad5fc05..58ef369342a78b59e3538321012eb31ff7d4375f 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc
+++ b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -40,3 +40,4 @@ ModeTransitionMemoryLocation        equ  LockLocation + 94h
 ModeTransitionSegmentLocation       equ  LockLocation + 98h\r
 ModeHighMemoryLocation              equ  LockLocation + 9Ah\r
 ModeHighSegmentLocation             equ  LockLocation + 9Eh\r
+Enable5LevelPagingLocation          equ  LockLocation + 0A0h\r

diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
index cea90f3d4deb56dcc4e1318aa966d259efc585d2..87f2523e856faaeecd187058f5ac039665d86627 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -100,6 +100,18 @@ SkipEnableExecuteDisableBit:
     ;\r
     mov        eax, cr4\r
     bts        eax, 5\r
+\r
+    mov        esi, Enable5LevelPagingLocation\r
+    cmp        byte [ebx + esi], 0\r
+    jz         SkipEnable5LevelPaging\r
+\r
+    ;\r
+    ; Enable 5 Level Paging\r
+    ;\r
+    bts        eax, 12                     ; Set LA57=1.\r
+\r
+SkipEnable5LevelPaging:\r
+\r
     mov        cr4, eax\r
 \r
     ;\r