UefiCpuPkg/PiSmmCpu: Use new PCD PcdCpuSmmRestrictedMemoryAccess

The patch changes PiSmmCpu driver to consume PCD
PcdCpuSmmRestrictedMemoryAccess.
Because the behavior controlled by PcdCpuSmmStaticPageTable in
original code is not changed after switching to
PcdCpuSmmRestrictedMemoryAccess.

The functionality is not impacted by this patch.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
index da0308c47f2aeb5a5835ba04fba4b313fa263003..b12b2691f8c17f68cb2eb0b989e91625a13c40f5 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
@@ -133,7 +133,6 @@
   gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress               ## SOMETIMES_PRODUCES\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable         ## CONSUMES\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode                      ## CONSUMES\r
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable               ## CONSUMES\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize               ## SOMETIMES_CONSUMES\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable                   ## CONSUMES\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask    ## CONSUMES\r
@@ -141,6 +140,9 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask               ## CONSUMES\r
   gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask        ## CONSUMES\r
 \r
+[Pcd.X64]\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess        ## CONSUMES\r
+\r
 [Depex]\r
   gEfiMpServiceProtocolGuid\r
 \r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index d60c404a3df5e120e46ce066b442638a4ed222ed..7516f3505540ee09a8d909b5f85ee712bab27332 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -15,7 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 LIST_ENTRY                          mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);\r
 BOOLEAN                             m1GPageTableSupport = FALSE;\r
-BOOLEAN                             mCpuSmmStaticPageTable;\r
+BOOLEAN                             mCpuSmmRestrictedMemoryAccess;\r
 BOOLEAN                             m5LevelPagingSupport;\r
 X86_ASSEMBLY_PATCH_LABEL            gPatch5LevelPagingSupport;\r
 \r
@@ -334,15 +334,15 @@ SmmInitPageTable (
   //\r
   InitializeSpinLock (mPFLock);\r
 \r
-  mCpuSmmStaticPageTable = PcdGetBool (PcdCpuSmmStaticPageTable);\r
-  m1GPageTableSupport    = Is1GPageSupport ();\r
-  m5LevelPagingSupport   = Is5LevelPagingSupport ();\r
-  mPhysicalAddressBits   = CalculateMaximumSupportAddress ();\r
+  mCpuSmmRestrictedMemoryAccess = PcdGetBool (PcdCpuSmmRestrictedMemoryAccess);\r
+  m1GPageTableSupport           = Is1GPageSupport ();\r
+  m5LevelPagingSupport          = Is5LevelPagingSupport ();\r
+  mPhysicalAddressBits          = CalculateMaximumSupportAddress ();\r
   PatchInstructionX86 (gPatch5LevelPagingSupport, m5LevelPagingSupport, 1);\r
-  DEBUG ((DEBUG_INFO, "5LevelPaging Support     - %d\n", m5LevelPagingSupport));\r
-  DEBUG ((DEBUG_INFO, "1GPageTable Support      - %d\n", m1GPageTableSupport));\r
-  DEBUG ((DEBUG_INFO, "PcdCpuSmmStaticPageTable - %d\n", mCpuSmmStaticPageTable));\r
-  DEBUG ((DEBUG_INFO, "PhysicalAddressBits      - %d\n", mPhysicalAddressBits));\r
+  DEBUG ((DEBUG_INFO, "5LevelPaging Support            - %d\n", m5LevelPagingSupport));\r
+  DEBUG ((DEBUG_INFO, "1GPageTable Support             - %d\n", m1GPageTableSupport));\r
+  DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n", mCpuSmmRestrictedMemoryAccess));\r
+  DEBUG ((DEBUG_INFO, "PhysicalAddressBits             - %d\n", mPhysicalAddressBits));\r
   //\r
   // Generate PAE page table for the first 4GB memory space\r
   //\r
@@ -385,7 +385,11 @@ SmmInitPageTable (
     PTEntry = Pml5Entry;\r
   }\r
 \r
-  if (mCpuSmmStaticPageTable) {\r
+  if (mCpuSmmRestrictedMemoryAccess) {\r
+    //\r
+    // When access to non-SMRAM memory is restricted, create page table\r
+    // that covers all memory space.\r
+    //\r
     SetStaticPageTable ((UINTN)PTEntry);\r
   } else {\r
     //\r
@@ -972,7 +976,7 @@ SmiPFHandler (
 \r
   PFAddress = AsmReadCr2 ();\r
 \r
-  if (mCpuSmmStaticPageTable && (PFAddress >= LShiftU64 (1, (mPhysicalAddressBits - 1)))) {\r
+  if (mCpuSmmRestrictedMemoryAccess && (PFAddress >= LShiftU64 (1, (mPhysicalAddressBits - 1)))) {\r
     DumpCpuContext (InterruptType, SystemContext);\r
     DEBUG ((DEBUG_ERROR, "Do not support address 0x%lx by processor!\n", PFAddress));\r
     CpuDeadLoop ();\r
@@ -1049,7 +1053,7 @@ SmiPFHandler (
       goto Exit;\r
     }\r
 \r
-    if (mCpuSmmStaticPageTable && IsSmmCommBufferForbiddenAddress (PFAddress)) {\r
+    if (mCpuSmmRestrictedMemoryAccess && IsSmmCommBufferForbiddenAddress (PFAddress)) {\r
       DumpCpuContext (InterruptType, SystemContext);\r
       DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%lx)!\n", PFAddress));\r
       DEBUG_CODE (\r
@@ -1100,26 +1104,26 @@ SetPageTableAttributes (
   Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
 \r
   //\r
-  // Don't do this if\r
-  //  - no static page table; or\r
+  // Don't mark page table memory as read-only if\r
+  //  - no restriction on access to non-SMRAM memory; or\r
   //  - SMM heap guard feature enabled; or\r
   //      BIT2: SMM page guard enabled\r
   //      BIT3: SMM pool guard enabled\r
   //  - SMM profile feature enabled\r
   //\r
-  if (!mCpuSmmStaticPageTable ||\r
+  if (!mCpuSmmRestrictedMemoryAccess ||\r
       ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) ||\r
       FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
     //\r
-    // Static paging and heap guard could not be enabled at the same time.\r
+    // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.\r
     //\r
-    ASSERT (!(mCpuSmmStaticPageTable &&\r
+    ASSERT (!(mCpuSmmRestrictedMemoryAccess &&\r
               (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0));\r
 \r
     //\r
-    // Static paging and SMM profile could not be enabled at the same time.\r
+    // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.\r
     //\r
-    ASSERT (!(mCpuSmmStaticPageTable && FeaturePcdGet (PcdCpuSmmProfileEnable)));\r
+    ASSERT (!(mCpuSmmRestrictedMemoryAccess && FeaturePcdGet (PcdCpuSmmProfileEnable)));\r
     return ;\r
   }\r
 \r
@@ -1223,7 +1227,10 @@ SaveCr2 (
   OUT UINTN  *Cr2\r
   )\r
 {\r
-  if (!mCpuSmmStaticPageTable) {\r
+  if (!mCpuSmmRestrictedMemoryAccess) {\r
+    //\r
+    // On-demand paging is enabled when access to non-SMRAM is not restricted.\r
+    //\r
     *Cr2 = AsmReadCr2 ();\r
   }\r
 }\r
@@ -1238,7 +1245,10 @@ RestoreCr2 (
   IN UINTN  Cr2\r
   )\r
 {\r
-  if (!mCpuSmmStaticPageTable) {\r
+  if (!mCpuSmmRestrictedMemoryAccess) {\r
+    //\r
+    // On-demand paging is enabled when access to non-SMRAM is not restricted.\r
+    //\r
     AsmWriteCr2 (Cr2);\r
   }\r
 }\r