\r
//\r
// Attempt to reset SMRAM cacheability to UC\r
+ // Assume CPU AP is available at this time\r
//\r
Status = gDS->SetMemorySpaceAttributes(\r
mSmramCacheBase, \r
// Note that it is expected that cacheability of SMRAM has been set to WB if CPU AP\r
// is not available here.\r
//\r
+ CpuArch = NULL;\r
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&CpuArch);\r
if (!EFI_ERROR (Status)) {\r
Status = gDS->SetMemorySpaceAttributes(\r
//\r
// Attempt to reset SMRAM cacheability to UC\r
//\r
- Status = gDS->SetMemorySpaceAttributes(\r
- mSmramCacheBase, \r
- mSmramCacheSize,\r
- EFI_MEMORY_UC\r
- );\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window to EFI_MEMORY_UC\n"));\r
- } \r
+ if (CpuArch != NULL) {\r
+ Status = gDS->SetMemorySpaceAttributes(\r
+ mSmramCacheBase, \r
+ mSmramCacheSize,\r
+ EFI_MEMORY_UC\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window to EFI_MEMORY_UC\n"));\r
+ } \r
+ }\r
}\r
} else {\r
//\r