The RVCT compiler may emit calls to the various __aeabi_c?cmp??
functions, which return their results via the CPU condition flags
C and Z. According to ARM doc IHI 0043D 'Run-time ABI for the ARM
architecture':
The 3-way comparison functions c*cmple, c*cmpeq and c*rcmple return
their results in the CPSR Z and C flags. C is clear only if the operands
are ordered and the first operand is less than the second. Z is set only
when the operands are ordered and equal.
Add implementations for the double and float variants of the above.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19327
6f19259b-4bc3-4df7-8a09-
765794883524
--- /dev/null
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2015, Linaro Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+ EXPORT __aeabi_cdrcmple\r
+ EXPORT __aeabi_cdcmpeq\r
+ EXPORT __aeabi_cdcmple\r
+ IMPORT _softfloat_float64_eq\r
+ IMPORT _softfloat_float64_lt\r
+\r
+ AREA __aeabi_cdcmp, CODE, READONLY\r
+ PRESERVE8\r
+\r
+__aeabi_cdrcmple\r
+ MOV IP, R0\r
+ MOV R0, R2\r
+ MOV R2, IP\r
+\r
+ MOV IP, R1\r
+ MOV R1, R3\r
+ MOV R3, IP\r
+\r
+__aeabi_cdcmpeq\r
+__aeabi_cdcmple\r
+ PUSH {R0 - R3, IP, LR}\r
+ BL _softfloat_float64_eq\r
+ SUB IP, R0, #1\r
+ CMP IP, #0 // sets C and Z if R0 == 1\r
+ POPEQ {R0 - R3, IP, PC}\r
+\r
+ LDM SP, {R0 - R3}\r
+ BL _softfloat_float64_lt\r
+ SUB IP, R0, #1\r
+ CMP IP, #1 // sets C if R0 == 0\r
+ POP {R0 - R3, IP, PC}\r
+\r
+ END\r
--- /dev/null
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2015, Linaro Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+ EXPORT __aeabi_cfrcmple\r
+ EXPORT __aeabi_cfcmpeq\r
+ EXPORT __aeabi_cfcmple\r
+ IMPORT _softfloat_float32_eq\r
+ IMPORT _softfloat_float32_lt\r
+\r
+ AREA __aeabi_cfcmp, CODE, READONLY\r
+ PRESERVE8\r
+\r
+__aeabi_cfrcmple\r
+ MOV IP, R0\r
+ MOV R0, R1\r
+ MOV R1, IP\r
+\r
+__aeabi_cfcmpeq\r
+__aeabi_cfcmple\r
+ PUSH {R0 - R3, IP, LR}\r
+ BL _softfloat_float32_eq\r
+ SUB IP, R0, #1\r
+ CMP IP, #0 // sets C and Z if R0 == 1\r
+ POPEQ {R0 - R3, IP, PC}\r
+\r
+ LDM SP, {R0 - R1}\r
+ BL _softfloat_float32_lt\r
+ SUB IP, R0, #1\r
+ CMP IP, #1 // sets C if R0 == 0\r
+ POP {R0 - R3, IP, PC}\r
+\r
+ END\r
Arm/__aeabi_dcmpun.c\r
Arm/__aeabi_fcmpun.c\r
\r
+ Arm/__aeabi_cdcmp.asm | RVCT\r
+ Arm/__aeabi_cfcmp.asm | RVCT\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
#define float128_gt __gttf2\r
#endif\r
\r
-#ifdef __ARM_EABI__\r
+#if defined (__ARM_EABI__) || defined (__CC_ARM)\r
#ifdef __ARM_PCS_VFP\r
#include <arm/aeabi.h>\r
#endif\r