BaseTools/GenFw: disable RVCT linker size optimization

Disable the RVCT size optimization that may put sections at an offset
that is not aligned to their own alignment, by adding the --no_legacyalign
switch to the RVCT linker command line. This is necessary since such sections
cannot be correctly converted into PE/COFF sections without padding them at
the front, which defeats the purpose of the optimization anyway.

With the optimization gone, we can also remove the special case for ARM in
GenFw that could result in corrupt PE/COFF images to be emitted. Instead,
sections whose base address is not aligned correctly are outright rejected.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18540 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index aa2b6b1488c4c9e3e2380e792f07a5331e7b6f24..cf4914415e5fce29bdf5f4bc67460cdebfad459f 100644 (file)
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -6609,7 +6609,7 @@ RELEASE_XCODE5_X64_CC_FLAGS   = -target x86_64-pc-win32-macho -c    -Os       -W
 \r
 DEFINE RVCT_ALL_ASM_FLAGS   = --diag_suppress=1786 --diag_error=warning --apcs /interwork\r
 DEFINE RVCT_ALL_CC_FLAGS    = --c90 -c --no_autoinline --asm --gnu --apcs /interwork --signed_chars --no_unaligned_access --split_sections --enum_is_int --preinclude AutoGen.h --diag_suppress=186 --diag_warning 167 --diag_error=warning --diag_style=ide --protect_stack\r
-DEFINE RVCT_ALL_DLINK_FLAGS = --ro-base 0 --no_scanlib --reloc --no_exceptions --datacompressor off --strict --symbols --diag_style=ide\r
+DEFINE RVCT_ALL_DLINK_FLAGS = --ro-base 0 --no_scanlib --reloc --no_exceptions --datacompressor off --strict --symbols --diag_style=ide --no_legacyalign\r
 \r
 ####################################################################################\r
 #\r

diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/GenFw/Elf32Convert.c
index 4b330a61669fb55c0dfa06bcc5d61d8debbd96e6..a7b077873b4058ac2c4e3c2cce70da7e3dcf6ca3 100644 (file)
--- a/BaseTools/Source/C/GenFw/Elf32Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
@@ -340,12 +340,8 @@ ScanSections32 (
         if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {\r
           // if the section address is aligned we must align PE/COFF\r
           mCoffOffset = (mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1);\r
-        } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {\r
-          // ARM RVCT tools have behavior outside of the ELF specification to try\r
-          // and make images smaller.  If sh_addr is not aligned to sh_addralign\r
-          // then the section needs to preserve sh_addr MOD sh_addralign.\r
-          // Normally doing nothing here works great.\r
-          Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");\r
+        } else {\r
+          Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");\r
         }\r
       }\r
 \r
@@ -375,10 +371,7 @@ ScanSections32 (
   }\r
 \r
   mDebugOffset = DebugRvaAlign(mCoffOffset);\r
-\r
-  if (mEhdr->e_machine != EM_ARM) {\r
-    mCoffOffset = CoffAlign(mCoffOffset);\r
-  }\r
+  mCoffOffset = CoffAlign(mCoffOffset);\r
 \r
   if (SectionCount > 1 && mOutImageType == FW_EFI_IMAGE) {\r
     Warning (NULL, 0, 0, NULL, "Mulitple sections in %s are merged into 1 text section. Source level debug might not work correctly.", mInImageName);\r
@@ -398,12 +391,8 @@ ScanSections32 (
         if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {\r
           // if the section address is aligned we must align PE/COFF\r
           mCoffOffset = (mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1);\r
-        } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {\r
-          // ARM RVCT tools have behavior outside of the ELF specification to try\r
-          // and make images smaller.  If sh_addr is not aligned to sh_addralign\r
-          // then the section needs to preserve sh_addr MOD sh_addralign.\r
-          // Normally doing nothing here works great.\r
-          Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");\r
+        } else {\r
+          Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");\r
         }\r
       }\r
 \r
@@ -455,12 +444,8 @@ ScanSections32 (
         if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {\r
           // if the section address is aligned we must align PE/COFF\r
           mCoffOffset = (mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1);\r
-        } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {\r
-          // ARM RVCT tools have behavior outside of the ELF specification to try\r
-          // and make images smaller.  If sh_addr is not aligned to sh_addralign\r
-          // then the section needs to preserve sh_addr MOD sh_addralign.\r
-          // Normally doing nothing here works great.\r
-          Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");\r
+        } else {\r
+          Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");\r
         }\r
       }\r
       if (shdr->sh_size != 0) {\r