UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttling

Today's implementation only assumes SandyBridge CPU supports
Extended On-Demand Clock Modulation Duty Cycle.
Actually it is supported when CPUID.06h.EAX[5] == 1.

When platform requests 50% throttling, it causes value 1000b
set to the low-4 bits of IA32_CLOCK_MODULATION.
But the wrong code sets 1000b to bits[1-3] which causes assertion.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <vanjeff_919@hotmail.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
index 56e53561e9de0f9fab0a51698f4016d983cac6d8..84d59de78f9775816a924e676f5289a1e7d806e9 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
@@ -1,7 +1,7 @@
 /** @file\r
   Clock Modulation feature.\r
 \r
-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -67,40 +67,34 @@ ClockModulationInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
-  if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
-    CPU_REGISTER_TABLE_WRITE_FIELD (\r
-      ProcessorNumber,\r
-      Msr,\r
-      MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION,\r
-      MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER,\r
-      Bits.OnDemandClockModulationDutyCycle,\r
-      PcdGet8 (PcdCpuClockModulationDutyCycle)\r
-      );\r
-    CPU_REGISTER_TABLE_WRITE_FIELD (\r
-      ProcessorNumber,\r
-      Msr,\r
-      MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION,\r
-      MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER,\r
-      Bits.OnDemandClockModulationEnable,\r
-      (State) ? 1 : 0\r
-      );\r
-  } else {\r
-    CPU_REGISTER_TABLE_WRITE_FIELD (\r
-      ProcessorNumber,\r
-      Msr,\r
-      MSR_IA32_CLOCK_MODULATION,\r
-      MSR_IA32_CLOCK_MODULATION_REGISTER,\r
-      Bits.OnDemandClockModulationDutyCycle,\r
-      PcdGet8 (PcdCpuClockModulationDutyCycle)\r
-      );\r
+  CPUID_THERMAL_POWER_MANAGEMENT_EAX   ThermalPowerManagementEax;\r
+  AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &ThermalPowerManagementEax.Uint32, NULL, NULL, NULL);\r
+\r
+  CPU_REGISTER_TABLE_WRITE_FIELD (\r
+    ProcessorNumber,\r
+    Msr,\r
+    MSR_IA32_CLOCK_MODULATION,\r
+    MSR_IA32_CLOCK_MODULATION_REGISTER,\r
+    Bits.OnDemandClockModulationDutyCycle,\r
+    PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1\r
+    );\r
+  if (ThermalPowerManagementEax.Bits.ECMD == 1) {\r
     CPU_REGISTER_TABLE_WRITE_FIELD (\r
       ProcessorNumber,\r
       Msr,\r
       MSR_IA32_CLOCK_MODULATION,\r
       MSR_IA32_CLOCK_MODULATION_REGISTER,\r
-      Bits.OnDemandClockModulationEnable,\r
-      (State) ? 1 : 0\r
+      Bits.ExtendedOnDemandClockModulationDutyCycle,\r
+      PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0\r
       );\r
   }\r
+  CPU_REGISTER_TABLE_WRITE_FIELD (\r
+    ProcessorNumber,\r
+    Msr,\r
+    MSR_IA32_CLOCK_MODULATION,\r
+    MSR_IA32_CLOCK_MODULATION_REGISTER,\r
+    Bits.OnDemandClockModulationEnable,\r
+    (State) ? 1 : 0\r
+    );\r
   return RETURN_SUCCESS;\r
 }\r