MdePkg: Add P2P Bridge Secondary Latency Timer register definition

Add P2P Bridge Secondary Latency Timer register definition to Pci22.h

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@hp.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17793 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 4a191403e3bff14ec08069fc4024e5ec9e398eeb..78ec6b316629fc9d876413924011da7dd6c44d50 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -9,7 +9,7 @@
   \r
 \r
   Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
-  Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>\r
+  Copyright (c) 2014 - 2105, Hewlett-Packard Development Company, L.P.<BR>\r
   This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
@@ -552,6 +552,7 @@ typedef struct {
 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18   \r
 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19   \r
 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a   \r
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET   0x1b\r
 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E   \r
 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E   \r
 \r