Renamed remotely

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6029 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/X86Cache.c b/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/X86Cache.c
new file mode 100644 (file)
index 0000000..2e2cb76
--- /dev/null
+++ b/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/X86Cache.c
@@ -0,0 +1,262 @@
+/*++\r
+\r
+Copyright (c) 2004 - 2006, Intel Corporation                                                         \r
+All rights reserved. This program and the accompanying materials                          \r
+are licensed and made available under the terms and conditions of the BSD License         \r
+which accompanies this distribution.  The full text of the license may be found at        \r
+http://opensource.org/licenses/bsd-license.php                                            \r
+                                                                                          \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.  \r
+\r
+\r
+Module Name:\r
+\r
+  x86Cache.c\r
+  \r
+Abstract: \r
+\r
+  Cache Maintenance Functions.\r
+\r
+--*/\r
+\r
+#include "EdkIIGlueBase.h"\r
+\r
+//\r
+// This size must be at or below the smallest cache size possible among all\r
+// supported processors\r
+//\r
+#define CACHE_LINE_SIZE             0x20\r
+\r
+/**\r
+  Invalidates the entire instruction cache in cache coherency domain of the\r
+  calling CPU.\r
+\r
+  Invalidates the entire instruction cache in cache coherency domain of the\r
+  calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+GlueInvalidateInstructionCache (\r
+  VOID\r
+  )\r
+{\r
+}\r
+\r
+/**\r
+  Invalidates a range of instruction cache lines in the cache coherency domain\r
+  of the calling CPU.\r
+\r
+  Invalidates the instruction cache lines specified by Address and Length. If\r
+  Address is not aligned on a cache line boundary, then entire instruction\r
+  cache line containing Address is invalidated. If Address + Length is not\r
+  aligned on a cache line boundary, then the entire instruction cache line\r
+  containing Address + Length -1 is invalidated. This function may choose to\r
+  invalidate the entire instruction cache if that is more efficient than\r
+  invalidating the specified range. If Length is 0, the no instruction cache\r
+  lines are invalidated. Address is returned.\r
+\r
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+  @param  Address The base address of the instruction cache lines to\r
+                  invalidate. If the CPU is in a physical addressing mode, then\r
+                  Address is a physical address. If the CPU is in a virtual\r
+                  addressing mode, then Address is a virtual address.\r
+\r
+  @param  Length  The number of bytes to invalidate from the instruction cache.\r
+\r
+  @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateInstructionCacheRange (\r
+  IN      VOID                      *Address,\r
+  IN      UINTN                     Length\r
+  )\r
+{\r
+  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+  return Address;\r
+}\r
+\r
+/**\r
+  Writes Back and Invalidates the entire data cache in cache coherency domain\r
+  of the calling CPU.\r
+\r
+  Writes Back and Invalidates the entire data cache in cache coherency domain\r
+  of the calling CPU. This function guarantees that all dirty cache lines are\r
+  written back to system memory, and also invalidates all the data cache lines\r
+  in the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackInvalidateDataCache (\r
+  VOID\r
+  )\r
+{\r
+  AsmWbinvd ();\r
+}\r
+\r
+/**\r
+  Writes Back and Invalidates a range of data cache lines in the cache\r
+  coherency domain of the calling CPU.\r
+\r
+  Writes Back and Invalidate the data cache lines specified by Address and\r
+  Length. If Address is not aligned on a cache line boundary, then entire data\r
+  cache line containing Address is written back and invalidated. If Address +\r
+  Length is not aligned on a cache line boundary, then the entire data cache\r
+  line containing Address + Length -1 is written back and invalidated. This\r
+  function may choose to write back and invalidate the entire data cache if\r
+  that is more efficient than writing back and invalidating the specified\r
+  range. If Length is 0, the no data cache lines are written back and\r
+  invalidated. Address is returned.\r
+\r
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+  @param  Address The base address of the data cache lines to write back and\r
+                  invalidate. If the CPU is in a physical addressing mode, then\r
+                  Address is a physical address. If the CPU is in a virtual\r
+                  addressing mode, then Address is a virtual address.\r
+  @param  Length  The number of bytes to write back and invalidate from the\r
+                  data cache.\r
+\r
+  @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackInvalidateDataCacheRange (\r
+  IN      VOID                      *Address,\r
+  IN      UINTN                     Length\r
+  )\r
+{\r
+  UINTN                             Start, End;\r
+\r
+  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+\r
+  if (Length == 0) {\r
+    return Address;\r
+  }\r
+\r
+  Start = (UINTN)Address;\r
+  End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);\r
+  Start &= ~(CACHE_LINE_SIZE - 1);\r
+\r
+  do {\r
+    Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;\r
+  } while (Start != End);\r
+  return Address;\r
+}\r
+\r
+/**\r
+  Writes Back the entire data cache in cache coherency domain of the calling\r
+  CPU.\r
+\r
+  Writes Back the entire data cache in cache coherency domain of the calling\r
+  CPU. This function guarantees that all dirty cache lines are written back to\r
+  system memory. This function may also invalidate all the data cache lines in\r
+  the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackDataCache (\r
+  VOID\r
+  )\r
+{\r
+  WriteBackInvalidateDataCache ();\r
+}\r
+\r
+/**\r
+  Writes Back a range of data cache lines in the cache coherency domain of the\r
+  calling CPU.\r
+\r
+  Writes Back the data cache lines specified by Address and Length. If Address\r
+  is not aligned on a cache line boundary, then entire data cache line\r
+  containing Address is written back. If Address + Length is not aligned on a\r
+  cache line boundary, then the entire data cache line containing Address +\r
+  Length -1 is written back. This function may choose to write back the entire\r
+  data cache if that is more efficient than writing back the specified range.\r
+  If Length is 0, the no data cache lines are written back. This function may\r
+  also invalidate all the data cache lines in the specified range of the cache\r
+  coherency domain of the calling CPU. Address is returned.\r
+\r
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+  @param  Address The base address of the data cache lines to write back. If\r
+                  the CPU is in a physical addressing mode, then Address is a\r
+                  physical address. If the CPU is in a virtual addressing\r
+                  mode, then Address is a virtual address.\r
+  @param  Length  The number of bytes to write back from the data cache.\r
+\r
+  @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackDataCacheRange (\r
+  IN      VOID                      *Address,\r
+  IN      UINTN                     Length\r
+  )\r
+{\r
+  return WriteBackInvalidateDataCacheRange (Address, Length);\r
+}\r
+\r
+/**\r
+  Invalidates the entire data cache in cache coherency domain of the calling\r
+  CPU.\r
+\r
+  Invalidates the entire data cache in cache coherency domain of the calling\r
+  CPU. This function must be used with care because dirty cache lines are not\r
+  written back to system memory. It is typically used for cache diagnostics. If\r
+  the CPU does not support invalidation of the entire data cache, then a write\r
+  back and invalidate operation should be performed on the entire data cache.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InvalidateDataCache (\r
+  VOID\r
+  )\r
+{\r
+  AsmInvd ();\r
+}\r
+\r
+/**\r
+  Invalidates a range of data cache lines in the cache coherency domain of the\r
+  calling CPU.\r
+\r
+  Invalidates the data cache lines specified by Address and Length. If Address\r
+  is not aligned on a cache line boundary, then entire data cache line\r
+  containing Address is invalidated. If Address + Length is not aligned on a\r
+  cache line boundary, then the entire data cache line containing Address +\r
+  Length -1 is invalidated. This function must never invalidate any cache lines\r
+  outside the specified range. If Length is 0, the no data cache lines are\r
+  invalidated. Address is returned. This function must be used with care\r
+  because dirty cache lines are not written back to system memory. It is\r
+  typically used for cache diagnostics. If the CPU does not support\r
+  invalidation of a data cache range, then a write back and invalidate\r
+  operation should be performed on the data cache range.\r
+\r
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+  @param  Address The base address of the data cache lines to invalidate. If\r
+                  the CPU is in a physical addressing mode, then Address is a\r
+                  physical address. If the CPU is in a virtual addressing mode,\r
+                  then Address is a virtual address.\r
+  @param  Length  The number of bytes to invalidate from the data cache.\r
+\r
+  @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateDataCacheRange (\r
+  IN      VOID                      *Address,\r
+  IN      UINTN                     Length\r
+  )\r
+{\r
+  return WriteBackInvalidateDataCacheRange (Address, Length);\r
+}\r

diff --git a/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/x86Cache.c b/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/x86Cache.c
deleted file mode 100644 (file)
index 2e2cb76..0000000
--- a/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/x86Cache.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/*++\r
-\r
-Copyright (c) 2004 - 2006, Intel Corporation                                                         \r
-All rights reserved. This program and the accompanying materials                          \r
-are licensed and made available under the terms and conditions of the BSD License         \r
-which accompanies this distribution.  The full text of the license may be found at        \r
-http://opensource.org/licenses/bsd-license.php                                            \r
-                                                                                          \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.  \r
-\r
-\r
-Module Name:\r
-\r
-  x86Cache.c\r
-  \r
-Abstract: \r
-\r
-  Cache Maintenance Functions.\r
-\r
---*/\r
-\r
-#include "EdkIIGlueBase.h"\r
-\r
-//\r
-// This size must be at or below the smallest cache size possible among all\r
-// supported processors\r
-//\r
-#define CACHE_LINE_SIZE             0x20\r
-\r
-/**\r
-  Invalidates the entire instruction cache in cache coherency domain of the\r
-  calling CPU.\r
-\r
-  Invalidates the entire instruction cache in cache coherency domain of the\r
-  calling CPU.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-GlueInvalidateInstructionCache (\r
-  VOID\r
-  )\r
-{\r
-}\r
-\r
-/**\r
-  Invalidates a range of instruction cache lines in the cache coherency domain\r
-  of the calling CPU.\r
-\r
-  Invalidates the instruction cache lines specified by Address and Length. If\r
-  Address is not aligned on a cache line boundary, then entire instruction\r
-  cache line containing Address is invalidated. If Address + Length is not\r
-  aligned on a cache line boundary, then the entire instruction cache line\r
-  containing Address + Length -1 is invalidated. This function may choose to\r
-  invalidate the entire instruction cache if that is more efficient than\r
-  invalidating the specified range. If Length is 0, the no instruction cache\r
-  lines are invalidated. Address is returned.\r
-\r
-  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
-  @param  Address The base address of the instruction cache lines to\r
-                  invalidate. If the CPU is in a physical addressing mode, then\r
-                  Address is a physical address. If the CPU is in a virtual\r
-                  addressing mode, then Address is a virtual address.\r
-\r
-  @param  Length  The number of bytes to invalidate from the instruction cache.\r
-\r
-  @return Address\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-InvalidateInstructionCacheRange (\r
-  IN      VOID                      *Address,\r
-  IN      UINTN                     Length\r
-  )\r
-{\r
-  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
-  return Address;\r
-}\r
-\r
-/**\r
-  Writes Back and Invalidates the entire data cache in cache coherency domain\r
-  of the calling CPU.\r
-\r
-  Writes Back and Invalidates the entire data cache in cache coherency domain\r
-  of the calling CPU. This function guarantees that all dirty cache lines are\r
-  written back to system memory, and also invalidates all the data cache lines\r
-  in the cache coherency domain of the calling CPU.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-WriteBackInvalidateDataCache (\r
-  VOID\r
-  )\r
-{\r
-  AsmWbinvd ();\r
-}\r
-\r
-/**\r
-  Writes Back and Invalidates a range of data cache lines in the cache\r
-  coherency domain of the calling CPU.\r
-\r
-  Writes Back and Invalidate the data cache lines specified by Address and\r
-  Length. If Address is not aligned on a cache line boundary, then entire data\r
-  cache line containing Address is written back and invalidated. If Address +\r
-  Length is not aligned on a cache line boundary, then the entire data cache\r
-  line containing Address + Length -1 is written back and invalidated. This\r
-  function may choose to write back and invalidate the entire data cache if\r
-  that is more efficient than writing back and invalidating the specified\r
-  range. If Length is 0, the no data cache lines are written back and\r
-  invalidated. Address is returned.\r
-\r
-  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
-  @param  Address The base address of the data cache lines to write back and\r
-                  invalidate. If the CPU is in a physical addressing mode, then\r
-                  Address is a physical address. If the CPU is in a virtual\r
-                  addressing mode, then Address is a virtual address.\r
-  @param  Length  The number of bytes to write back and invalidate from the\r
-                  data cache.\r
-\r
-  @return Address\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-WriteBackInvalidateDataCacheRange (\r
-  IN      VOID                      *Address,\r
-  IN      UINTN                     Length\r
-  )\r
-{\r
-  UINTN                             Start, End;\r
-\r
-  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
-\r
-  if (Length == 0) {\r
-    return Address;\r
-  }\r
-\r
-  Start = (UINTN)Address;\r
-  End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);\r
-  Start &= ~(CACHE_LINE_SIZE - 1);\r
-\r
-  do {\r
-    Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;\r
-  } while (Start != End);\r
-  return Address;\r
-}\r
-\r
-/**\r
-  Writes Back the entire data cache in cache coherency domain of the calling\r
-  CPU.\r
-\r
-  Writes Back the entire data cache in cache coherency domain of the calling\r
-  CPU. This function guarantees that all dirty cache lines are written back to\r
-  system memory. This function may also invalidate all the data cache lines in\r
-  the cache coherency domain of the calling CPU.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-WriteBackDataCache (\r
-  VOID\r
-  )\r
-{\r
-  WriteBackInvalidateDataCache ();\r
-}\r
-\r
-/**\r
-  Writes Back a range of data cache lines in the cache coherency domain of the\r
-  calling CPU.\r
-\r
-  Writes Back the data cache lines specified by Address and Length. If Address\r
-  is not aligned on a cache line boundary, then entire data cache line\r
-  containing Address is written back. If Address + Length is not aligned on a\r
-  cache line boundary, then the entire data cache line containing Address +\r
-  Length -1 is written back. This function may choose to write back the entire\r
-  data cache if that is more efficient than writing back the specified range.\r
-  If Length is 0, the no data cache lines are written back. This function may\r
-  also invalidate all the data cache lines in the specified range of the cache\r
-  coherency domain of the calling CPU. Address is returned.\r
-\r
-  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
-  @param  Address The base address of the data cache lines to write back. If\r
-                  the CPU is in a physical addressing mode, then Address is a\r
-                  physical address. If the CPU is in a virtual addressing\r
-                  mode, then Address is a virtual address.\r
-  @param  Length  The number of bytes to write back from the data cache.\r
-\r
-  @return Address\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-WriteBackDataCacheRange (\r
-  IN      VOID                      *Address,\r
-  IN      UINTN                     Length\r
-  )\r
-{\r
-  return WriteBackInvalidateDataCacheRange (Address, Length);\r
-}\r
-\r
-/**\r
-  Invalidates the entire data cache in cache coherency domain of the calling\r
-  CPU.\r
-\r
-  Invalidates the entire data cache in cache coherency domain of the calling\r
-  CPU. This function must be used with care because dirty cache lines are not\r
-  written back to system memory. It is typically used for cache diagnostics. If\r
-  the CPU does not support invalidation of the entire data cache, then a write\r
-  back and invalidate operation should be performed on the entire data cache.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-InvalidateDataCache (\r
-  VOID\r
-  )\r
-{\r
-  AsmInvd ();\r
-}\r
-\r
-/**\r
-  Invalidates a range of data cache lines in the cache coherency domain of the\r
-  calling CPU.\r
-\r
-  Invalidates the data cache lines specified by Address and Length. If Address\r
-  is not aligned on a cache line boundary, then entire data cache line\r
-  containing Address is invalidated. If Address + Length is not aligned on a\r
-  cache line boundary, then the entire data cache line containing Address +\r
-  Length -1 is invalidated. This function must never invalidate any cache lines\r
-  outside the specified range. If Length is 0, the no data cache lines are\r
-  invalidated. Address is returned. This function must be used with care\r
-  because dirty cache lines are not written back to system memory. It is\r
-  typically used for cache diagnostics. If the CPU does not support\r
-  invalidation of a data cache range, then a write back and invalidate\r
-  operation should be performed on the data cache range.\r
-\r
-  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
-  @param  Address The base address of the data cache lines to invalidate. If\r
-                  the CPU is in a physical addressing mode, then Address is a\r
-                  physical address. If the CPU is in a virtual addressing mode,\r
-                  then Address is a virtual address.\r
-  @param  Length  The number of bytes to invalidate from the data cache.\r
-\r
-  @return Address\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-InvalidateDataCacheRange (\r
-  IN      VOID                      *Address,\r
-  IN      UINTN                     Length\r
-  )\r
-{\r
-  return WriteBackInvalidateDataCacheRange (Address, Length);\r
-}\r