0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c, 0x83 } \\r
}\r
\r
+#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \\r
+ FixedPcdGetSize (PcdCpuStackSwitchExceptionList)\r
+\r
+#define CPU_STACK_SWITCH_EXCEPTION_LIST \\r
+ FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)\r
+\r
+#define CPU_KNOWN_GOOD_STACK_SIZE \\r
+ FixedPcdGet32 (PcdCpuKnownGoodStackSize)\r
+\r
+#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)\r
+\r
//\r
// Record exception handler information\r
//\r
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData\r
);\r
\r
+/**\r
+ Setup separate stack for specific exceptions.\r
+\r
+ @param[in] StackSwitchData Pointer to data required for setuping up\r
+ stack switch.\r
+\r
+ @retval EFI_SUCCESS The exceptions have been successfully\r
+ initialized with new stack.\r
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.\r
+**/\r
+EFI_STATUS\r
+ArchSetupExcpetionStack (\r
+ IN CPU_EXCEPTION_INIT_DATA *StackSwitchData\r
+ );\r
+\r
+/**\r
+ Return address map of exception handler template so that C code can generate\r
+ exception tables. The template is only for exceptions using task gate instead\r
+ of interrupt gate.\r
+\r
+ @param AddressMap Pointer to a buffer where the address map is returned.\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmGetTssTemplateMap (\r
+ OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap\r
+ );\r
+\r
#endif\r
\r
[Sources.Ia32]\r
Ia32/ExceptionHandlerAsm.asm\r
Ia32/ExceptionHandlerAsm.nasm\r
+ Ia32/ExceptionTssEntryAsm.nasm\r
Ia32/ExceptionHandlerAsm.S\r
Ia32/ArchExceptionHandler.c\r
Ia32/ArchInterruptDefs.h\r
PeiDxeSmmCpuException.c\r
DxeException.c\r
\r
+[Pcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
\r
EXCEPTION_HANDLER_DATA mExceptionHandlerData;\r
\r
+UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *\r
+ CPU_KNOWN_GOOD_STACK_SIZE];\r
+UINT8 mNewGdt[CPU_TSS_GDT_SIZE];\r
+\r
/**\r
Common exception handler.\r
\r
{\r
return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);\r
}\r
+\r
+/**\r
+ Initializes CPU exceptions entries and setup stack switch for given exceptions.\r
+\r
+ This method will call InitializeCpuExceptionHandlers() to setup default\r
+ exception handlers unless indicated not to do it explicitly.\r
+\r
+ If InitData is passed with NULL, this method will use the resource reserved\r
+ by global variables to initialize it; Otherwise it will use data in InitData\r
+ to setup stack switch. This is for the different use cases in DxeCore and\r
+ Cpu MP exception initialization.\r
+\r
+ @param[in] VectorInfo Pointer to reserved vector list.\r
+ @param[in] InitData Pointer to data required to setup stack switch for\r
+ given exceptions.\r
+\r
+ @retval EFI_SUCCESS The exceptions have been successfully\r
+ initialized.\r
+ @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid\r
+ content.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeCpuExceptionHandlersEx (\r
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,\r
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ CPU_EXCEPTION_INIT_DATA EssData;\r
+ IA32_DESCRIPTOR Idtr;\r
+ IA32_DESCRIPTOR Gdtr;\r
+\r
+ //\r
+ // To avoid repeat initialization of default handlers, the caller should pass\r
+ // an extended init data with InitDefaultHandlers set to FALSE. There's no\r
+ // need to call this method to just initialize default handlers. Call non-ex\r
+ // version instead; or this method must be implemented as a simple wrapper of\r
+ // non-ex version of it, if this version has to be called.\r
+ //\r
+ if (InitData == NULL || InitData->X64.InitDefaultHandlers) {\r
+ Status = InitializeCpuExceptionHandlers (VectorInfo);\r
+ } else {\r
+ Status = EFI_SUCCESS;\r
+ }\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // Initializing stack switch is only necessary for Stack Guard functionality.\r
+ //\r
+ if (PcdGetBool (PcdCpuStackGuard)) {\r
+ if (InitData == NULL) {\r
+ SetMem (mNewGdt, sizeof (mNewGdt), 0);\r
+\r
+ AsmReadIdtr (&Idtr);\r
+ AsmReadGdtr (&Gdtr);\r
+\r
+ EssData.X64.Revision = CPU_EXCEPTION_INIT_DATA_REV;\r
+ EssData.X64.KnownGoodStackTop = (UINTN)mNewStack;\r
+ EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE;\r
+ EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;\r
+ EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;\r
+ EssData.X64.IdtTable = (VOID *)Idtr.Base;\r
+ EssData.X64.IdtTableSize = Idtr.Limit + 1;\r
+ EssData.X64.GdtTable = mNewGdt;\r
+ EssData.X64.GdtTableSize = sizeof (mNewGdt);\r
+ EssData.X64.ExceptionTssDesc = mNewGdt + Gdtr.Limit + 1;\r
+ EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE;\r
+ EssData.X64.ExceptionTss = mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;\r
+ EssData.X64.ExceptionTssSize = CPU_TSS_SIZE;\r
+\r
+ InitData = &EssData;\r
+ }\r
+ Status = ArchSetupExcpetionStack (InitData);\r
+ }\r
+ }\r
+\r
+ return Status;\r
+}\r
SystemContext.SystemContextIa32->ExceptionData = ReservedVectors[ExceptionType].ExceptionData;\r
}\r
\r
+/**\r
+ Setup separate stack for given exceptions.\r
+\r
+ @param[in] StackSwitchData Pointer to data required for setuping up\r
+ stack switch.\r
+\r
+ @retval EFI_SUCCESS The exceptions have been successfully\r
+ initialized with new stack.\r
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.\r
+\r
+**/\r
+EFI_STATUS\r
+ArchSetupExcpetionStack (\r
+ IN CPU_EXCEPTION_INIT_DATA *StackSwitchData\r
+ )\r
+{\r
+ IA32_DESCRIPTOR Gdtr;\r
+ IA32_DESCRIPTOR Idtr;\r
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;\r
+ IA32_TSS_DESCRIPTOR *TssDesc;\r
+ IA32_TASK_STATE_SEGMENT *Tss;\r
+ UINTN StackTop;\r
+ UINTN Index;\r
+ UINTN Vector;\r
+ UINTN TssBase;\r
+ UINTN GdtSize;\r
+ EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;\r
+\r
+ if (StackSwitchData == NULL ||\r
+ StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV ||\r
+ StackSwitchData->Ia32.KnownGoodStackTop == 0 ||\r
+ StackSwitchData->Ia32.KnownGoodStackSize == 0 ||\r
+ StackSwitchData->Ia32.StackSwitchExceptions == NULL ||\r
+ StackSwitchData->Ia32.StackSwitchExceptionNumber == 0 ||\r
+ StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM ||\r
+ StackSwitchData->Ia32.GdtTable == NULL ||\r
+ StackSwitchData->Ia32.IdtTable == NULL ||\r
+ StackSwitchData->Ia32.ExceptionTssDesc == NULL ||\r
+ StackSwitchData->Ia32.ExceptionTss == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // The caller is responsible for that the GDT table, no matter the existing\r
+ // one or newly allocated, has enough space to hold descriptors for exception\r
+ // task-state segments.\r
+ //\r
+ if (((UINTN)StackSwitchData->Ia32.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc < (UINTN)(StackSwitchData->Ia32.GdtTable)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize >\r
+ ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // We need one descriptor and one TSS for current task and every exception\r
+ // specified.\r
+ //\r
+ if (StackSwitchData->Ia32.ExceptionTssDescSize <\r
+ sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ if (StackSwitchData->Ia32.ExceptionTssSize <\r
+ sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ TssDesc = StackSwitchData->Ia32.ExceptionTssDesc;\r
+ Tss = StackSwitchData->Ia32.ExceptionTss;\r
+\r
+ //\r
+ // Initialize new GDT table and/or IDT table, if any\r
+ //\r
+ AsmReadIdtr (&Idtr);\r
+ AsmReadGdtr (&Gdtr);\r
+\r
+ GdtSize = (UINTN)TssDesc +\r
+ sizeof (IA32_TSS_DESCRIPTOR) *\r
+ (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1) -\r
+ (UINTN)(StackSwitchData->Ia32.GdtTable);\r
+ if ((UINTN)StackSwitchData->Ia32.GdtTable != Gdtr.Base) {\r
+ CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
+ Gdtr.Base = (UINTN)StackSwitchData->Ia32.GdtTable;\r
+ Gdtr.Limit = (UINT16)GdtSize - 1;\r
+ }\r
+\r
+ if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) {\r
+ Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable;\r
+ }\r
+ if (StackSwitchData->Ia32.IdtTableSize > 0) {\r
+ Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1);\r
+ }\r
+\r
+ //\r
+ // Fixup current task descriptor. Task-state segment for current task will\r
+ // be filled by processor during task switching.\r
+ //\r
+ TssBase = (UINTN)Tss;\r
+\r
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;\r
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;\r
+ TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);\r
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;\r
+ TssDesc->Bits.P = 1;\r
+ TssDesc->Bits.LimitHigh = 0;\r
+ TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);\r
+\r
+ //\r
+ // Fixup exception task descriptor and task-state segment\r
+ //\r
+ AsmGetTssTemplateMap (&TemplateMap);\r
+ StackTop = StackSwitchData->Ia32.KnownGoodStackTop - CPU_STACK_ALIGNMENT;\r
+ StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);\r
+ IdtTable = StackSwitchData->Ia32.IdtTable;\r
+ for (Index = 0; Index < StackSwitchData->Ia32.StackSwitchExceptionNumber; ++Index) {\r
+ TssDesc += 1;\r
+ Tss += 1;\r
+\r
+ //\r
+ // Fixup TSS descriptor\r
+ //\r
+ TssBase = (UINTN)Tss;\r
+\r
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;\r
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;\r
+ TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);\r
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;\r
+ TssDesc->Bits.P = 1;\r
+ TssDesc->Bits.LimitHigh = 0;\r
+ TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);\r
+\r
+ //\r
+ // Fixup TSS\r
+ //\r
+ Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index];\r
+ if (Vector >= CPU_EXCEPTION_NUM ||\r
+ Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) {\r
+ continue;\r
+ }\r
+\r
+ Tss->EIP = (UINT32)(TemplateMap.ExceptionStart\r
+ + Vector * TemplateMap.ExceptionStubHeaderSize);\r
+ Tss->EFLAGS = 0x2;\r
+ Tss->ESP = StackTop;\r
+ Tss->CR3 = AsmReadCr3 ();\r
+ Tss->ES = AsmReadEs ();\r
+ Tss->CS = AsmReadCs ();\r
+ Tss->SS = AsmReadSs ();\r
+ Tss->DS = AsmReadDs ();\r
+ Tss->FS = AsmReadFs ();\r
+ Tss->GS = AsmReadGs ();\r
+\r
+ StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;\r
+\r
+ //\r
+ // Update IDT to use Task Gate for given exception\r
+ //\r
+ IdtTable[Vector].Bits.OffsetLow = 0;\r
+ IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc - Gdtr.Base);\r
+ IdtTable[Vector].Bits.Reserved_0 = 0;\r
+ IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;\r
+ IdtTable[Vector].Bits.OffsetHigh = 0;\r
+ }\r
+\r
+ //\r
+ // Publish GDT\r
+ //\r
+ AsmWriteGdtr (&Gdtr);\r
+\r
+ //\r
+ // Load current task\r
+ //\r
+ AsmWriteTr ((UINT16)((UINTN)StackSwitchData->Ia32.ExceptionTssDesc - Gdtr.Base));\r
+\r
+ //\r
+ // Publish IDT\r
+ //\r
+ AsmWriteIdtr (&Idtr);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
/**\r
Display processor context.\r
\r
UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];\r
} RESERVED_VECTORS_DATA;\r
\r
+#define CPU_TSS_DESC_SIZE \\r
+ (sizeof (IA32_TSS_DESCRIPTOR) * \\r
+ (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))\r
+\r
+#define CPU_TSS_SIZE \\r
+ (sizeof (IA32_TASK_STATE_SEGMENT) * \\r
+ (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))\r
+\r
#endif\r
--- /dev/null
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ExceptionTssEntryAsm.Asm\r
+;\r
+; Abstract:\r
+;\r
+; IA32 CPU Exception Handler with Separate Stack\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+;\r
+; IA32 TSS Memory Layout Description\r
+;\r
+struc IA32_TSS\r
+ resw 1\r
+ resw 1\r
+ .ESP0: resd 1\r
+ .SS0: resw 1\r
+ resw 1\r
+ .ESP1: resd 1\r
+ .SS1: resw 1\r
+ resw 1\r
+ .ESP2: resd 1\r
+ .SS2: resw 1\r
+ resw 1\r
+ ._CR3: resd 1\r
+ .EIP: resd 1\r
+ .EFLAGS: resd 1\r
+ ._EAX: resd 1\r
+ ._ECX: resd 1\r
+ ._EDX: resd 1\r
+ ._EBX: resd 1\r
+ ._ESP: resd 1\r
+ ._EBP: resd 1\r
+ ._ESI: resd 1\r
+ ._EDI: resd 1\r
+ ._ES: resw 1\r
+ resw 1\r
+ ._CS: resw 1\r
+ resw 1\r
+ ._SS: resw 1\r
+ resw 1\r
+ ._DS: resw 1\r
+ resw 1\r
+ ._FS: resw 1\r
+ resw 1\r
+ ._GS: resw 1\r
+ resw 1\r
+ .LDT: resw 1\r
+ resw 1\r
+ resw 1\r
+ resw 1\r
+endstruc\r
+\r
+;\r
+; CommonExceptionHandler()\r
+;\r
+extern ASM_PFX(CommonExceptionHandler)\r
+\r
+SECTION .data\r
+\r
+SECTION .text\r
+\r
+ALIGN 8\r
+\r
+;\r
+; Exception handler stub table\r
+;\r
+AsmExceptionEntryBegin:\r
+%assign Vector 0\r
+%rep 32\r
+\r
+DoIret%[Vector]:\r
+ iretd\r
+ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):\r
+ db 0x6a ; push #VectorNum\r
+ db %[Vector]\r
+ mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)\r
+ call eax\r
+ mov esp, eax ; Restore stack top\r
+ jmp DoIret%[Vector]\r
+\r
+%assign Vector Vector+1\r
+%endrep\r
+AsmExceptionEntryEnd:\r
+\r
+;\r
+; Common part of exception handler\r
+;\r
+global ASM_PFX(CommonTaskSwtichEntryPoint)\r
+ASM_PFX(CommonTaskSwtichEntryPoint):\r
+ ;\r
+ ; Stack:\r
+ ; +---------------------+ <-- EBP - 8\r
+ ; + TSS Base +\r
+ ; +---------------------+ <-- EBP - 4\r
+ ; + CPUID.EDX +\r
+ ; +---------------------+ <-- EBP\r
+ ; + EIP +\r
+ ; +---------------------+ <-- EBP + 4\r
+ ; + Vector Number +\r
+ ; +---------------------+ <-- EBP + 8\r
+ ; + Error Code +\r
+ ; +---------------------+\r
+ ;\r
+\r
+ mov ebp, esp ; Stack frame\r
+\r
+; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported\r
+ mov eax, 1\r
+ cpuid\r
+ push edx\r
+\r
+; Get TSS base of interrupted task through PreviousTaskLink field in\r
+; current TSS base\r
+ sub esp, 8\r
+ sgdt [esp + 2]\r
+ mov eax, [esp + 4] ; GDT base\r
+ add esp, 8\r
+\r
+ xor ebx, ebx\r
+ str bx ; Current TR\r
+\r
+ mov ecx, [eax + ebx + 2]\r
+ shl ecx, 8\r
+ mov cl, [eax + ebx + 7]\r
+ ror ecx, 8 ; ecx = Current TSS base\r
+ push ecx ; keep it in stack for later use\r
+\r
+ movzx ebx, word [ecx] ; Previous Task Link\r
+ mov ecx, [eax + ebx + 2]\r
+ shl ecx, 8\r
+ mov cl, [eax + ebx + 7]\r
+ ror ecx, 8 ; ecx = Previous TSS base\r
+\r
+;\r
+; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32\r
+; is 16-byte aligned\r
+;\r
+ and esp, 0xfffffff0\r
+ sub esp, 12\r
+\r
+;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
+ push dword [ecx + IA32_TSS._EAX]\r
+ push dword [ecx + IA32_TSS._ECX]\r
+ push dword [ecx + IA32_TSS._EDX]\r
+ push dword [ecx + IA32_TSS._EBX]\r
+ push dword [ecx + IA32_TSS._ESP]\r
+ push dword [ecx + IA32_TSS._EBP]\r
+ push dword [ecx + IA32_TSS._ESI]\r
+ push dword [ecx + IA32_TSS._EDI]\r
+\r
+;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
+ movzx eax, word [ecx + IA32_TSS._SS]\r
+ push eax\r
+ movzx eax, word [ecx + IA32_TSS._CS]\r
+ push eax\r
+ movzx eax, word [ecx + IA32_TSS._DS]\r
+ push eax\r
+ movzx eax, word [ecx + IA32_TSS._ES]\r
+ push eax\r
+ movzx eax, word [ecx + IA32_TSS._FS]\r
+ push eax\r
+ movzx eax, word [ecx + IA32_TSS._GS]\r
+ push eax\r
+\r
+;; UINT32 Eip;\r
+ push dword [ecx + IA32_TSS.EIP]\r
+\r
+;; UINT32 Gdtr[2], Idtr[2];\r
+ sub esp, 8\r
+ sidt [esp]\r
+ mov eax, [esp + 2]\r
+ xchg eax, [esp]\r
+ and eax, 0xFFFF\r
+ mov [esp+4], eax\r
+\r
+ sub esp, 8\r
+ sgdt [esp]\r
+ mov eax, [esp + 2]\r
+ xchg eax, [esp]\r
+ and eax, 0xFFFF\r
+ mov [esp+4], eax\r
+\r
+;; UINT32 Ldtr, Tr;\r
+ mov eax, ebx ; ebx still keeps selector of interrupted task\r
+ push eax\r
+ movzx eax, word [ecx + IA32_TSS.LDT]\r
+ push eax\r
+\r
+;; UINT32 EFlags;\r
+ push dword [ecx + IA32_TSS.EFLAGS]\r
+\r
+;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
+ mov eax, cr4\r
+ push eax ; push cr4 firstly\r
+\r
+ mov edx, [ebp - 4] ; cpuid.edx\r
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support\r
+ jz .1\r
+ or eax, BIT9 ; Set CR4.OSFXSR\r
+.1:\r
+ test edx, BIT2 ; Test for Debugging Extensions support\r
+ jz .2\r
+ or eax, BIT3 ; Set CR4.DE\r
+.2:\r
+ mov cr4, eax\r
+\r
+ mov eax, cr3\r
+ push eax\r
+ mov eax, cr2\r
+ push eax\r
+ xor eax, eax\r
+ push eax\r
+ mov eax, cr0\r
+ push eax\r
+\r
+;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
+ mov eax, dr7\r
+ push eax\r
+ mov eax, dr6\r
+ push eax\r
+ mov eax, dr3\r
+ push eax\r
+ mov eax, dr2\r
+ push eax\r
+ mov eax, dr1\r
+ push eax\r
+ mov eax, dr0\r
+ push eax\r
+\r
+;; FX_SAVE_STATE_IA32 FxSaveState;\r
+;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)\r
+;; when executing fxsave/fxrstor instruction\r
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.\r
+ ; edx still contains result from CPUID above\r
+ jz .3\r
+ clts\r
+ sub esp, 512\r
+ mov edi, esp\r
+ db 0xf, 0xae, 0x7 ;fxsave [edi]\r
+.3:\r
+\r
+;; UINT32 ExceptionData;\r
+ push dword [ebp + 8]\r
+\r
+;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
+ cld\r
+\r
+;; call into exception handler\r
+ mov esi, ecx ; Keep TSS base to avoid overwrite\r
+ mov eax, ASM_PFX(CommonExceptionHandler)\r
+\r
+;; Prepare parameter and call\r
+ mov edx, esp\r
+ push edx ; EFI_SYSTEM_CONTEXT\r
+ push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)\r
+\r
+ ;\r
+ ; Call External Exception Handler\r
+ ;\r
+ call eax\r
+ add esp, 8 ; Restore stack before calling\r
+ mov ecx, esi ; Restore TSS base\r
+\r
+;; UINT32 ExceptionData;\r
+ add esp, 4\r
+\r
+;; FX_SAVE_STATE_IA32 FxSaveState;\r
+ mov edx, [ebp - 4] ; cpuid.edx\r
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support\r
+ jz .4\r
+ mov esi, esp\r
+ db 0xf, 0xae, 0xe ; fxrstor [esi]\r
+.4:\r
+ add esp, 512\r
+\r
+;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
+;; Skip restoration of DRx registers to support debuggers\r
+;; that set breakpoints in interrupt/exception context\r
+ add esp, 4 * 6\r
+\r
+;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
+ pop eax\r
+ mov cr0, eax\r
+ add esp, 4 ; not for Cr1\r
+ pop eax\r
+ mov cr2, eax\r
+ pop eax\r
+ mov dword [ecx + IA32_TSS._CR3], eax\r
+ pop eax\r
+ mov cr4, eax\r
+\r
+;; UINT32 EFlags;\r
+ pop dword [ecx + IA32_TSS.EFLAGS]\r
+ mov ebx, dword [ecx + IA32_TSS.EFLAGS]\r
+ btr ebx, 9 ; Do 'cli'\r
+ mov dword [ecx + IA32_TSS.EFLAGS], ebx\r
+\r
+;; UINT32 Ldtr, Tr;\r
+;; UINT32 Gdtr[2], Idtr[2];\r
+;; Best not let anyone mess with these particular registers...\r
+ add esp, 24\r
+\r
+;; UINT32 Eip;\r
+ pop dword [ecx + IA32_TSS.EIP]\r
+\r
+;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
+;; NOTE - modified segment registers could hang the debugger... We\r
+;; could attempt to insulate ourselves against this possibility,\r
+;; but that poses risks as well.\r
+;;\r
+ pop eax\r
+o16 mov [ecx + IA32_TSS._GS], ax\r
+ pop eax\r
+o16 mov [ecx + IA32_TSS._FS], ax\r
+ pop eax\r
+o16 mov [ecx + IA32_TSS._ES], ax\r
+ pop eax\r
+o16 mov [ecx + IA32_TSS._DS], ax\r
+ pop eax\r
+o16 mov [ecx + IA32_TSS._CS], ax\r
+ pop eax\r
+o16 mov [ecx + IA32_TSS._SS], ax\r
+\r
+;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
+ pop dword [ecx + IA32_TSS._EDI]\r
+ pop dword [ecx + IA32_TSS._ESI]\r
+ add esp, 4 ; not for ebp\r
+ add esp, 4 ; not for esp\r
+ pop dword [ecx + IA32_TSS._EBX]\r
+ pop dword [ecx + IA32_TSS._EDX]\r
+ pop dword [ecx + IA32_TSS._ECX]\r
+ pop dword [ecx + IA32_TSS._EAX]\r
+\r
+; Set single step DB# to allow debugger to able to go back to the EIP\r
+; where the exception is triggered.\r
+\r
+;; Create return context for iretd in stub function\r
+ mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer\r
+ mov ebx, dword [ecx + IA32_TSS.EIP]\r
+ mov [eax - 0xc], ebx ; create EIP in old stack\r
+ movzx ebx, word [ecx + IA32_TSS._CS]\r
+ mov [eax - 0x8], ebx ; create CS in old stack\r
+ mov ebx, dword [ecx + IA32_TSS.EFLAGS]\r
+ bts ebx, 8\r
+ mov [eax - 0x4], ebx ; create eflags in old stack\r
+ mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS\r
+ mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer\r
+ sub eax, 0xc ; minus 12 byte\r
+ mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer\r
+\r
+;; Replace the EIP of interrupted task with stub function\r
+ mov eax, ASM_PFX(SingleStepStubFunction)\r
+ mov dword [ecx + IA32_TSS.EIP], eax\r
+\r
+ mov ecx, [ebp - 8] ; Get current TSS base\r
+ mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack top\r
+ mov esp, ebp\r
+\r
+ ret\r
+\r
+global ASM_PFX(SingleStepStubFunction)\r
+ASM_PFX(SingleStepStubFunction):\r
+;\r
+; we need clean TS bit in CR0 to execute\r
+; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.\r
+;\r
+ clts\r
+ iretd\r
+\r
+global ASM_PFX(AsmGetTssTemplateMap)\r
+ASM_PFX(AsmGetTssTemplateMap):\r
+ push ebp ; C prolog\r
+ mov ebp, esp\r
+ pushad\r
+\r
+ mov ebx, dword [ebp + 0x8]\r
+ mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)\r
+ mov dword [ebx + 0x4], (AsmExceptionEntryEnd - AsmExceptionEntryBegin) / 32\r
+ mov dword [ebx + 0x8], 0\r
+\r
+ popad\r
+ pop ebp\r
+ ret\r
+\r
)\r
{\r
return EFI_UNSUPPORTED;\r
-}
\ No newline at end of file
+}\r
+\r
+/**\r
+ Initializes all CPU exceptions entries with optional extra initializations.\r
+\r
+ By default, this method should include all functionalities implemented by\r
+ InitializeCpuExceptionHandlers(), plus extra initialization works, if any.\r
+ This could be done by calling InitializeCpuExceptionHandlers() directly\r
+ in this method besides the extra works.\r
+\r
+ InitData is optional and its use and content are processor arch dependent.\r
+ The typical usage of it is to convey resources which have to be reserved\r
+ elsewhere and are necessary for the extra initializations of exception.\r
+\r
+ @param[in] VectorInfo Pointer to reserved vector list.\r
+ @param[in] InitData Pointer to data optional for extra initializations\r
+ of exception.\r
+\r
+ @retval EFI_SUCCESS The exceptions have been successfully\r
+ initialized.\r
+ @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid\r
+ content.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeCpuExceptionHandlersEx (\r
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,\r
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL\r
+ )\r
+{\r
+ return InitializeCpuExceptionHandlers (VectorInfo);\r
+}\r
[Sources.Ia32]\r
Ia32/ExceptionHandlerAsm.asm\r
Ia32/ExceptionHandlerAsm.nasm\r
+ Ia32/ExceptionTssEntryAsm.nasm\r
Ia32/ExceptionHandlerAsm.S\r
Ia32/ArchExceptionHandler.c\r
Ia32/ArchInterruptDefs.h\r
)\r
{\r
return EFI_UNSUPPORTED;\r
-}
\ No newline at end of file
+}\r
+\r
+/**\r
+ Initializes all CPU exceptions entries with optional extra initializations.\r
+\r
+ By default, this method should include all functionalities implemented by\r
+ InitializeCpuExceptionHandlers(), plus extra initialization works, if any.\r
+ This could be done by calling InitializeCpuExceptionHandlers() directly\r
+ in this method besides the extra works.\r
+\r
+ InitData is optional and its use and content are processor arch dependent.\r
+ The typical usage of it is to convey resources which have to be reserved\r
+ elsewhere and are necessary for the extra initializations of exception.\r
+\r
+ @param[in] VectorInfo Pointer to reserved vector list.\r
+ @param[in] InitData Pointer to data optional for extra initializations\r
+ of exception.\r
+\r
+ @retval EFI_SUCCESS The exceptions have been successfully\r
+ initialized.\r
+ @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid\r
+ content.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeCpuExceptionHandlersEx (\r
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,\r
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL\r
+ )\r
+{\r
+ return InitializeCpuExceptionHandlers (VectorInfo);\r
+}\r
[Sources.Ia32]\r
Ia32/ExceptionHandlerAsm.asm\r
Ia32/ExceptionHandlerAsm.nasm\r
+ Ia32/ExceptionTssEntryAsm.nasm\r
Ia32/ExceptionHandlerAsm.S\r
Ia32/ArchExceptionHandler.c\r
Ia32/ArchInterruptDefs.h\r
[Sources.Ia32]\r
Ia32/ExceptionHandlerAsm.asm\r
Ia32/ExceptionHandlerAsm.nasm\r
+ Ia32/ExceptionTssEntryAsm.nasm\r
Ia32/ExceptionHandlerAsm.S\r
Ia32/ArchExceptionHandler.c\r
Ia32/ArchInterruptDefs.h\r
)\r
{\r
return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);\r
-}
\ No newline at end of file
+}\r
+\r
+/**\r
+ Initializes all CPU exceptions entries with optional extra initializations.\r
+\r
+ By default, this method should include all functionalities implemented by\r
+ InitializeCpuExceptionHandlers(), plus extra initialization works, if any.\r
+ This could be done by calling InitializeCpuExceptionHandlers() directly\r
+ in this method besides the extra works.\r
+\r
+ InitData is optional and its use and content are processor arch dependent.\r
+ The typical usage of it is to convey resources which have to be reserved\r
+ elsewhere and are necessary for the extra initializations of exception.\r
+\r
+ @param[in] VectorInfo Pointer to reserved vector list.\r
+ @param[in] InitData Pointer to data optional for extra initializations\r
+ of exception.\r
+\r
+ @retval EFI_SUCCESS The exceptions have been successfully\r
+ initialized.\r
+ @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid\r
+ content.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeCpuExceptionHandlersEx (\r
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,\r
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL\r
+ )\r
+{\r
+ return InitializeCpuExceptionHandlers (VectorInfo);\r
+}\r
SystemContext.SystemContextX64->ExceptionData = ReservedVectors[ExceptionType].ExceptionData;\r
}\r
\r
+/**\r
+ Setup separate stack for given exceptions.\r
+\r
+ @param[in] StackSwitchData Pointer to data required for setuping up\r
+ stack switch.\r
+\r
+ @retval EFI_SUCCESS The exceptions have been successfully\r
+ initialized with new stack.\r
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.\r
+\r
+**/\r
+EFI_STATUS\r
+ArchSetupExcpetionStack (\r
+ IN CPU_EXCEPTION_INIT_DATA *StackSwitchData\r
+ )\r
+{\r
+ IA32_DESCRIPTOR Gdtr;\r
+ IA32_DESCRIPTOR Idtr;\r
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;\r
+ IA32_TSS_DESCRIPTOR *TssDesc;\r
+ IA32_TASK_STATE_SEGMENT *Tss;\r
+ UINTN StackTop;\r
+ UINTN Index;\r
+ UINTN Vector;\r
+ UINTN TssBase;\r
+ UINTN GdtSize;\r
+\r
+ if (StackSwitchData == NULL ||\r
+ StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV ||\r
+ StackSwitchData->X64.KnownGoodStackTop == 0 ||\r
+ StackSwitchData->X64.KnownGoodStackSize == 0 ||\r
+ StackSwitchData->X64.StackSwitchExceptions == NULL ||\r
+ StackSwitchData->X64.StackSwitchExceptionNumber == 0 ||\r
+ StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM ||\r
+ StackSwitchData->X64.GdtTable == NULL ||\r
+ StackSwitchData->X64.IdtTable == NULL ||\r
+ StackSwitchData->X64.ExceptionTssDesc == NULL ||\r
+ StackSwitchData->X64.ExceptionTss == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // The caller is responsible for that the GDT table, no matter the existing\r
+ // one or newly allocated, has enough space to hold descriptors for exception\r
+ // task-state segments.\r
+ //\r
+ if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchData->X64.GdtTable)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >\r
+ ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // One task gate descriptor and one task-state segment are needed.\r
+ //\r
+ if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Interrupt stack table supports only 7 vectors.\r
+ //\r
+ TssDesc = StackSwitchData->X64.ExceptionTssDesc;\r
+ Tss = StackSwitchData->X64.ExceptionTss;\r
+ if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Initialize new GDT table and/or IDT table, if any\r
+ //\r
+ AsmReadIdtr (&Idtr);\r
+ AsmReadGdtr (&Gdtr);\r
+\r
+ GdtSize = (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) -\r
+ (UINTN)(StackSwitchData->X64.GdtTable);\r
+ if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) {\r
+ CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
+ Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable;\r
+ Gdtr.Limit = (UINT16)GdtSize - 1;\r
+ }\r
+\r
+ if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {\r
+ Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;\r
+ }\r
+ if (StackSwitchData->X64.IdtTableSize > 0) {\r
+ Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);\r
+ }\r
+\r
+ //\r
+ // Fixup current task descriptor. Task-state segment for current task will\r
+ // be filled by processor during task switching.\r
+ //\r
+ TssBase = (UINTN)Tss;\r
+\r
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;\r
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;\r
+ TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);\r
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;\r
+ TssDesc->Bits.P = 1;\r
+ TssDesc->Bits.LimitHigh = 0;\r
+ TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);\r
+ TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);\r
+\r
+ //\r
+ // Fixup exception task descriptor and task-state segment\r
+ //\r
+ StackTop = StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMENT;\r
+ StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);\r
+ IdtTable = StackSwitchData->X64.IdtTable;\r
+ for (Index = 0; Index < StackSwitchData->X64.StackSwitchExceptionNumber; ++Index) {\r
+ //\r
+ // Fixup IST\r
+ //\r
+ Tss->IST[Index] = StackTop;\r
+ StackTop -= StackSwitchData->X64.KnownGoodStackSize;\r
+\r
+ //\r
+ // Set the IST field to enable corresponding IST\r
+ //\r
+ Vector = StackSwitchData->X64.StackSwitchExceptions[Index];\r
+ if (Vector >= CPU_EXCEPTION_NUM ||\r
+ Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) {\r
+ continue;\r
+ }\r
+ IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1);\r
+ }\r
+\r
+ //\r
+ // Publish GDT\r
+ //\r
+ AsmWriteGdtr (&Gdtr);\r
+\r
+ //\r
+ // Load current task\r
+ //\r
+ AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr.Base));\r
+\r
+ //\r
+ // Publish IDT\r
+ //\r
+ AsmWriteIdtr (&Idtr);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
/**\r
Display CPU information.\r
\r
UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];\r
} RESERVED_VECTORS_DATA;\r
\r
+#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)\r
+#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)\r
+\r
#endif\r
projects / mirror_edk2.git / commitdiff