+/** @file\r
+ Serial I/O Port library functions with no library constructor/destructor\r
+\r
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Protocol/SerialIo.h>\r
+\r
+#include "PL011Uart.h"\r
+\r
+#define FRACTION_PART_SIZE_IN_BITS 6\r
+#define FRACTION_PART_MASK ((1 << FRACTION_PART_SIZE_IN_BITS) - 1)\r
+\r
+//\r
+// EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only\r
+// control bit that is not supported.\r
+//\r
+STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;\r
+\r
+/**\r
+\r
+ Initialise the serial port to the specified settings.\r
+ The serial port is re-configured only if the specified settings\r
+ are different from the current settings.\r
+ All unspecified settings will be set to the default values.\r
+\r
+ @param UartBase The base address of the serial device.\r
+ @param UartClkInHz The clock in Hz for the serial device.\r
+ Ignored if the PCD PL011UartInteger is not 0\r
+ @param BaudRate The baud rate of the serial device. If the\r
+ baud rate is not supported, the speed will be\r
+ reduced to the nearest supported one and the\r
+ variable's value will be updated accordingly.\r
+ @param ReceiveFifoDepth The number of characters the device will\r
+ buffer on input. Value of 0 will use the\r
+ device's default FIFO depth.\r
+ @param Parity If applicable, this is the EFI_PARITY_TYPE\r
+ that is computed or checked as each character\r
+ is transmitted or received. If the device\r
+ does not support parity, the value is the\r
+ default parity value.\r
+ @param DataBits The number of data bits in each character.\r
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number\r
+ of stop bits per character.\r
+ If the device does not support stop bits, the\r
+ value is the default stop bit value.\r
+\r
+ @retval RETURN_SUCCESS All attributes were set correctly on the\r
+ serial device.\r
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an\r
+ unsupported value.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PL011UartInitializePort (\r
+ IN UINTN UartBase,\r
+ IN UINT32 UartClkInHz,\r
+ IN OUT UINT64 *BaudRate,\r
+ IN OUT UINT32 *ReceiveFifoDepth,\r
+ IN OUT EFI_PARITY_TYPE *Parity,\r
+ IN OUT UINT8 *DataBits,\r
+ IN OUT EFI_STOP_BITS_TYPE *StopBits\r
+ )\r
+{\r
+ UINT32 LineControl;\r
+ UINT32 Divisor;\r
+ UINT32 Integer;\r
+ UINT32 Fractional;\r
+ UINT32 HardwareFifoDepth;\r
+\r
+ HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \\r
+ > PL011_VER_R1P4) \\r
+ ? 32 : 16 ;\r
+ // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept\r
+ // 1 char buffer as the minimum FIFO size. Because everything can be rounded\r
+ // down, there is no maximum FIFO size.\r
+ if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {\r
+ // Enable FIFO\r
+ LineControl = PL011_UARTLCR_H_FEN;\r
+ *ReceiveFifoDepth = HardwareFifoDepth;\r
+ } else {\r
+ // Disable FIFO\r
+ LineControl = 0;\r
+ // Nothing else to do. 1 byte FIFO is default.\r
+ *ReceiveFifoDepth = 1;\r
+ }\r
+\r
+ //\r
+ // Parity\r
+ //\r
+ switch (*Parity) {\r
+ case DefaultParity:\r
+ *Parity = NoParity;\r
+ case NoParity:\r
+ // Nothing to do. Parity is disabled by default.\r
+ break;\r
+ case EvenParity:\r
+ LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);\r
+ break;\r
+ case OddParity:\r
+ LineControl |= PL011_UARTLCR_H_PEN;\r
+ break;\r
+ case MarkParity:\r
+ LineControl |= ( PL011_UARTLCR_H_PEN \\r
+ | PL011_UARTLCR_H_SPS \\r
+ | PL011_UARTLCR_H_EPS);\r
+ break;\r
+ case SpaceParity:\r
+ LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);\r
+ break;\r
+ default:\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Data Bits\r
+ //\r
+ switch (*DataBits) {\r
+ case 0:\r
+ *DataBits = 8;\r
+ case 8:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_8;\r
+ break;\r
+ case 7:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_7;\r
+ break;\r
+ case 6:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_6;\r
+ break;\r
+ case 5:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_5;\r
+ break;\r
+ default:\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Stop Bits\r
+ //\r
+ switch (*StopBits) {\r
+ case DefaultStopBits:\r
+ *StopBits = OneStopBit;\r
+ case OneStopBit:\r
+ // Nothing to do. One stop bit is enabled by default.\r
+ break;\r
+ case TwoStopBits:\r
+ LineControl |= PL011_UARTLCR_H_STP2;\r
+ break;\r
+ case OneFiveStopBits:\r
+ // Only 1 or 2 stop bits are supported\r
+ default:\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+\r
+ // Don't send the LineControl value to the PL011 yet,\r
+ // wait until after the Baud Rate setting.\r
+ // This ensures we do not mess up the UART settings halfway through\r
+ // in the rare case when there is an error with the Baud Rate.\r
+\r
+ //\r
+ // Baud Rate\r
+ //\r
+\r
+ // If PL011 Integer value has been defined then always ignore the BAUD rate\r
+ if (FixedPcdGet32 (PL011UartInteger) != 0) {\r
+ Integer = FixedPcdGet32 (PL011UartInteger);\r
+ Fractional = FixedPcdGet32 (PL011UartFractional);\r
+ } else {\r
+ // If BAUD rate is zero then replace it with the system default value\r
+ if (*BaudRate == 0) {\r
+ *BaudRate = FixedPcdGet32 (PcdSerialBaudRate);\r
+ if (*BaudRate == 0) {\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+ }\r
+ if (0 == UartClkInHz) {\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+\r
+ Divisor = (UartClkInHz * 4) / *BaudRate;\r
+ Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;\r
+ Fractional = Divisor & FRACTION_PART_MASK;\r
+ }\r
+\r
+ //\r
+ // If PL011 is already initialized, check the current settings\r
+ // and re-initialize only if the settings are different.\r
+ //\r
+ if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&\r
+ (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&\r
+ (MmioRead32 (UartBase + UARTIBRD) == Integer) &&\r
+ (MmioRead32 (UartBase + UARTFBRD) == Fractional)) {\r
+ // Nothing to do - already initialized with correct attributes\r
+ return RETURN_SUCCESS;\r
+ }\r
+\r
+ // Wait for the end of transmission\r
+ while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);\r
+\r
+ // Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed\r
+ // when the UART is enabled"\r
+ MmioWrite32 (UartBase + UARTCR, 0);\r
+\r
+ // Set Baud Rate Registers\r
+ MmioWrite32 (UartBase + UARTIBRD, Integer);\r
+ MmioWrite32 (UartBase + UARTFBRD, Fractional);\r
+\r
+ // No parity, 1 stop, no fifo, 8 data bits\r
+ MmioWrite32 (UartBase + UARTLCR_H, LineControl);\r
+\r
+ // Clear any pending errors\r
+ MmioWrite32 (UartBase + UARTECR, 0);\r
+\r
+ // Enable Tx, Rx, and UART overall\r
+ MmioWrite32 (UartBase + UARTCR,\r
+ PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ Assert or deassert the control signals on a serial port.\r
+ The following control signals are set according their bit settings :\r
+ . Request to Send\r
+ . Data Terminal Ready\r
+\r
+ @param[in] UartBase UART registers base address\r
+ @param[in] Control The following bits are taken into account :\r
+ . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
+ "Request To Send" control signal if this bit is\r
+ equal to one/zero.\r
+ . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
+ the "Data Terminal Ready" control signal if this\r
+ bit is equal to one/zero.\r
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
+ the hardware loopback if this bit is equal to\r
+ one/zero.\r
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
+ disable the hardware flow control based on CTS (Clear\r
+ To Send) and RTS (Ready To Send) control signals.\r
+\r
+ @retval RETURN_SUCCESS The new control bits were set on the device.\r
+ @retval RETURN_UNSUPPORTED The device does not support this operation.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PL011UartSetControl (\r
+ IN UINTN UartBase,\r
+ IN UINT32 Control\r
+ )\r
+{\r
+ UINT32 Bits;\r
+\r
+ if (Control & (mInvalidControlBits)) {\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
+\r
+ Bits = MmioRead32 (UartBase + UARTCR);\r
+\r
+ if (Control & EFI_SERIAL_REQUEST_TO_SEND) {\r
+ Bits |= PL011_UARTCR_RTS;\r
+ } else {\r
+ Bits &= ~PL011_UARTCR_RTS;\r
+ }\r
+\r
+ if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {\r
+ Bits |= PL011_UARTCR_DTR;\r
+ } else {\r
+ Bits &= ~PL011_UARTCR_DTR;\r
+ }\r
+\r
+ if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {\r
+ Bits |= PL011_UARTCR_LBE;\r
+ } else {\r
+ Bits &= ~PL011_UARTCR_LBE;\r
+ }\r
+\r
+ if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {\r
+ Bits |= (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);\r
+ } else {\r
+ Bits &= ~(PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);\r
+ }\r
+\r
+ MmioWrite32 (UartBase + UARTCR, Bits);\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ Retrieve the status of the control bits on a serial device.\r
+\r
+ @param[in] UartBase UART registers base address\r
+ @param[out] Control Status of the control bits on a serial device :\r
+\r
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND,\r
+ EFI_SERIAL_DATA_SET_READY,\r
+ EFI_SERIAL_RING_INDICATE,\r
+ EFI_SERIAL_CARRIER_DETECT,\r
+ EFI_SERIAL_REQUEST_TO_SEND,\r
+ EFI_SERIAL_DATA_TERMINAL_READY\r
+ are all related to the DTE (Data Terminal Equipment)\r
+ and DCE (Data Communication Equipment) modes of\r
+ operation of the serial device.\r
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r
+ receive buffer is empty, 0 otherwise.\r
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r
+ transmit buffer is empty, 0 otherwise.\r
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r
+ the hardware loopback is enabled (the ouput feeds the\r
+ receive buffer), 0 otherwise.\r
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if\r
+ a loopback is accomplished by software, 0 otherwise.\r
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r
+ one if the hardware flow control based on CTS (Clear\r
+ To Send) and RTS (Ready To Send) control signals is\r
+ enabled, 0 otherwise.\r
+\r
+ @retval RETURN_SUCCESS The control bits were read from the serial device.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PL011UartGetControl (\r
+ IN UINTN UartBase,\r
+ OUT UINT32 *Control\r
+ )\r
+{\r
+ UINT32 FlagRegister;\r
+ UINT32 ControlRegister;\r
+\r
+\r
+ FlagRegister = MmioRead32 (UartBase + UARTFR);\r
+ ControlRegister = MmioRead32 (UartBase + UARTCR);\r
+\r
+ *Control = 0;\r
+\r
+ if ((FlagRegister & PL011_UARTFR_CTS) == PL011_UARTFR_CTS) {\r
+ *Control |= EFI_SERIAL_CLEAR_TO_SEND;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_DSR) == PL011_UARTFR_DSR) {\r
+ *Control |= EFI_SERIAL_DATA_SET_READY;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_RI) == PL011_UARTFR_RI) {\r
+ *Control |= EFI_SERIAL_RING_INDICATE;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_DCD) == PL011_UARTFR_DCD) {\r
+ *Control |= EFI_SERIAL_CARRIER_DETECT;\r
+ }\r
+\r
+ if ((ControlRegister & PL011_UARTCR_RTS) == PL011_UARTCR_RTS) {\r
+ *Control |= EFI_SERIAL_REQUEST_TO_SEND;\r
+ }\r
+\r
+ if ((ControlRegister & PL011_UARTCR_DTR) == PL011_UARTCR_DTR) {\r
+ *Control |= EFI_SERIAL_DATA_TERMINAL_READY;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_RXFE) == PL011_UARTFR_RXFE) {\r
+ *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_TXFE) == PL011_UARTFR_TXFE) {\r
+ *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;\r
+ }\r
+\r
+ if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))\r
+ == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {\r
+ *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;\r
+ }\r
+\r
+ if ((ControlRegister & PL011_UARTCR_LBE) == PL011_UARTCR_LBE) {\r
+ *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;\r
+ }\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Write data to serial device.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
+\r
+ @retval 0 Write data failed.\r
+ @retval !0 Actual number of bytes written to serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PL011UartWrite (\r
+ IN UINTN UartBase,\r
+ IN UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
+{\r
+ UINT8* CONST Final = &Buffer[NumberOfBytes];\r
+\r
+ while (Buffer < Final) {\r
+ // Wait until UART able to accept another char\r
+ while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));\r
+\r
+ MmioWrite8 (UartBase + UARTDR, *Buffer++);\r
+ }\r
+\r
+ return NumberOfBytes;\r
+}\r
+\r
+/**\r
+ Read data from serial device and save the data in buffer.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
+\r
+ @retval 0 Read data failed.\r
+ @retval !0 Actual number of bytes read from serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PL011UartRead (\r
+ IN UINTN UartBase,\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
+{\r
+ UINTN Count;\r
+\r
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {\r
+ while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);\r
+ *Buffer = MmioRead8 (UartBase + UARTDR);\r
+ }\r
+\r
+ return NumberOfBytes;\r
+}\r
+\r
+/**\r
+ Check to see if any data is available to be read from the debug device.\r
+\r
+ @retval TRUE At least one byte of data is available to be read\r
+ @retval FALSE No data is available to be read\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PL011UartPoll (\r
+ IN UINTN UartBase\r
+ )\r
+{\r
+ return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);\r
+}\r
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