PcdIsaBusSupportDma|0x00010040|gEfiIntelFrameworkModulePkgTokenSpaceGuid|BOOLEAN|TRUE\r
PcdIsaBusOnlySupportSlaveDma|0x00010041|gEfiIntelFrameworkModulePkgTokenSpaceGuid|BOOLEAN|FALSE\r
PcdIsaBusSupportIsaMemory|0x00010042|gEfiIntelFrameworkModulePkgTokenSpaceGuid|BOOLEAN|TRUE\r
+ PcdPciCfgDisable|0x00010043|gEfiIntelFrameworkModulePkgTokenSpaceGuid|BOOLEAN|FALSE\r
+ PcdPciCfg2Disable|0x00010044|gEfiIntelFrameworkModulePkgTokenSpaceGuid|BOOLEAN|FALSE\r
\r
[PcdsFixedAtBuild.common]\r
PcdStatusCodeMemorySize|0x00010025|gEfiIntelFrameworkModulePkgTokenSpaceGuid|UINT16|1\r
PcdIsaBusSupportDma|gEfiIntelFrameworkModulePkgTokenSpaceGuid|TRUE\r
PcdIsaBusOnlySupportSlaveDma|gEfiIntelFrameworkModulePkgTokenSpaceGuid|FALSE\r
PcdIsaBusSupportIsaMemory|gEfiIntelFrameworkModulePkgTokenSpaceGuid|TRUE\r
+ PcdPciCfgDisable|gEfiIntelFrameworkModulePkgTokenSpaceGuid|TRUE\r
+ PcdPciCfg2Disable|gEfiIntelFrameworkModulePkgTokenSpaceGuid|TRUE\r
PcdNtEmulatorEnable|gEfiMdeModulePkgTokenSpaceGuid|FALSE\r
\r
[PcdsFixedAtBuild.common]\r
$(WORKSPACE)/IntelFrameworkModulePkg/Universal/SetupBrowserDxe/SetupBrowser.inf\r
$(WORKSPACE)/IntelFrameworkModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf\r
$(WORKSPACE)/IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf\r
+ $(WORKSPACE)/IntelFrameworkModulePkg/Universal/PcatSingleSegmentPciCfgPei/PcatSingleSegmentPciCfgPei.inf\r
$(WORKSPACE)/IntelFrameworkModulePkg/Bus/Pci/VgaMiniPortDxe/VgaMiniPortDxe.inf\r
\r
[Components.IA32]\r
--- /dev/null
+#/** @file\r
+# Single Segment Pci Configuration PPI\r
+#\r
+# This file declares PciCfg PPI used to access PCI configuration space in PEI\r
+# Copyright (c) 2006 - 2007, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PcatSingleSegmentPciCfgPei\r
+ FILE_GUID = 27A5159D-5E61-4809-919A-422E887101EF\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+ ENTRY_POINT = PeimInitializePciCfg\r
+\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+ PciCfg.c\r
+ PciCfg2.c\r
+ PciCfgInternal.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+\r
+\r
+[LibraryClasses]\r
+ PeimEntryPoint\r
+ PciLib\r
+ BaseLib\r
+ DebugLib\r
+\r
+\r
+[Ppis]\r
+ gEfiPciCfg2PpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiPciCfgPpiInServiceTableGuid # PPI ALWAYS_PRODUCED\r
+\r
+[PcdsFeatureFlag.common]\r
+ PcdPciCfgDisable|gEfiIntelFrameworkModulePkgTokenSpaceGuid\r
+ PcdPciCfg2Disable|gEfiIntelFrameworkModulePkgTokenSpaceGuid\r
+\r
+[Depex]\r
+ TRUE\r
+\r
--- /dev/null
+/*++\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ PciCfg.c\r
+\r
+Abstract:\r
+\r
+ Single Segment Pci Configuration PPI\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#include "PciCfgInternal.h"\r
+\r
+\r
+/**\r
+ PCI read operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param This Pointer to local data for the interface.\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ @param Address The physical address of the access.\r
+ @param Buffer A pointer to the buffer of data.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Unsupported width\r
+ enumeration.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciCfgRead (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_PCI_CFG_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ UINTN PciLibAddress;\r
+\r
+ PciLibAddress = COMMON_TO_PCILIB_ADDRESS (Address);\r
+ switch (Width) {\r
+ case EfiPeiPciCfgWidthUint8:\r
+ * (UINT8 *) Buffer = PciRead8 (PciLibAddress);\r
+ break;\r
+\r
+ case EfiPeiPciCfgWidthUint16:\r
+ * (UINT16 *) Buffer = PciRead16 (PciLibAddress);\r
+ break;\r
+\r
+ case EfiPeiPciCfgWidthUint32:\r
+ * (UINT32 *) Buffer = PciRead32 (PciLibAddress);\r
+ break;\r
+\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ PCI write operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param This Pointer to local data for the interface.\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ @param Address The physical address of the access.\r
+ @param Buffer A pointer to the buffer of data.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ \r
+ \r
+ @retval EFI_INVALID_PARAMETER Unsupported width\r
+ enumeration.\r
+ \r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciCfgWrite (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_PCI_CFG_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ UINTN PciLibAddress;\r
+\r
+ PciLibAddress = COMMON_TO_PCILIB_ADDRESS (Address);\r
+ switch (Width) {\r
+ case EfiPeiPciCfgWidthUint8:\r
+ PciWrite8 (PciLibAddress, *(UINT8 *) Buffer);\r
+ break;\r
+\r
+ case EfiPeiPciCfgWidthUint16:\r
+ PciWrite16 (PciLibAddress, *(UINT16 *) Buffer);\r
+ break;\r
+\r
+ case EfiPeiPciCfgWidthUint32:\r
+ PciWrite32 (PciLibAddress, *(UINT32 *) Buffer);\r
+ break;\r
+\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ PCI read-modify-write operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param This Pointer to local data for the interface.\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ @param Address The physical address of the access.\r
+ @param SetBits Value of the bits to set.\r
+ @param ClearBits Value of the bits to clear.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Unsupported width\r
+ enumeration.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciCfgModify (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_PCI_CFG_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN SetBits,\r
+ IN UINTN ClearBits\r
+ )\r
+{\r
+ UINTN PciLibAddress;\r
+\r
+ PciLibAddress = COMMON_TO_PCILIB_ADDRESS (Address);\r
+ switch (Width) {\r
+ case EfiPeiPciCfgWidthUint8:\r
+ PciAndThenOr8 (PciLibAddress, (UINT8)~ClearBits, (UINT8)SetBits);\r
+ break;\r
+\r
+ case EfiPeiPciCfgWidthUint16:\r
+ PciAndThenOr16 (PciLibAddress, (UINT16)~ClearBits, (UINT16)SetBits);\r
+ break;\r
+\r
+ case EfiPeiPciCfgWidthUint32:\r
+ PciAndThenOr32 (PciLibAddress, (UINT32)~ClearBits, (UINT32)SetBits);\r
+ break;\r
+\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/**\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PciCfgInternal.h"\r
+\r
+/**\r
+ @par Ppi Description:\r
+ The EFI_PEI_PCI_CFG2_PPI interfaces are used to abstract\r
+ accesses to PCI controllers behind a PCI root bridge\r
+ controller.\r
+\r
+ @param Read PCI read services. See the Read() function description.\r
+\r
+ @param Write PCI write services. See the Write() function description.\r
+\r
+ @param Modify PCI read-modify-write services. See the Modify() function description.\r
+\r
+ @param Segment The PCI bus segment which the specified functions will access.\r
+\r
+**/\r
+GLOBAL_REMOVE_IF_UNREFERENCED\r
+EFI_PEI_PCI_CFG2_PPI gPciCfg2Ppi = {\r
+ PciCfg2Read,\r
+ PciCfg2Write,\r
+ PciCfg2Modify\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED\r
+EFI_PEI_PPI_DESCRIPTOR gPciCfg2PpiList = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPciCfg2PpiGuid,\r
+ &gPciCfg2Ppi\r
+};\r
+\r
+\r
+/**\r
+ @par Ppi Description:\r
+ The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI\r
+ controllers behind a PCI root bridge controller.\r
+\r
+ @param Read PCI read services. See the Read() function description.\r
+\r
+ @param Write PCI write services. See the Write() function description.\r
+\r
+ @param Modify PCI read-modify-write services. See the Modify() function description.\r
+\r
+ @param Segment The PCI bus segment which the specified functions will access.\r
+\r
+**/\r
+GLOBAL_REMOVE_IF_UNREFERENCED\r
+EFI_PEI_PCI_CFG_PPI gPciCfgPpi = {\r
+ PciCfgRead,\r
+ PciCfgWrite,\r
+ PciCfgModify\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED\r
+EFI_PEI_PPI_DESCRIPTOR gPciCfgPpiList = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPciCfgPpiInServiceTableGuid,\r
+ &gPciCfgPpi\r
+};\r
+\r
+/**\r
+ Reads from a given location in the PCI configuration space.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+ @param Address The physical address of the access. The format of\r
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+ @param Buffer A pointer to the buffer of data..\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
+ time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Read (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+)\r
+{\r
+ UINTN PciLibAddress;\r
+\r
+ PciLibAddress = COMMON_TO_PCILIB_ADDRESS (Address);\r
+\r
+ if (Width == EfiPeiPciCfgWidthUint8) {\r
+ *((UINT8 *) Buffer) = PciRead8 (PciLibAddress);\r
+ } else if (Width == EfiPeiPciCfgWidthUint16) {\r
+ *((UINT16 *) Buffer) = PciRead16 (PciLibAddress);\r
+ } else if (Width == EfiPeiPciCfgWidthUint32) {\r
+ *((UINT32 *) Buffer) = PciRead32 (PciLibAddress);\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Write to a given location in the PCI configuration space.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+ @param Address The physical address of the access. The format of\r
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+ @param Buffer A pointer to the buffer of data..\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
+ time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Write (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+)\r
+{\r
+ UINTN PciLibAddress;\r
+\r
+ PciLibAddress = COMMON_TO_PCILIB_ADDRESS (Address);\r
+\r
+ if (Width == EfiPeiPciCfgWidthUint8) {\r
+ PciWrite8 (PciLibAddress, *((UINT8 *) Buffer));\r
+ } else if (Width == EfiPeiPciCfgWidthUint16) {\r
+ PciWrite16 (PciLibAddress, *((UINT16 *) Buffer));\r
+ } else if (Width == EfiPeiPciCfgWidthUint32) {\r
+ PciWrite32 (PciLibAddress, *((UINT32 *) Buffer));\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ PCI read-modify-write operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes. Type\r
+ EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r
+\r
+ @param Address The physical address of the access.\r
+\r
+ @param SetBits Points to value to bitwise-OR with the read configuration value.\r
+\r
+ The size of the value is determined by Width.\r
+\r
+ @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.\r
+ The size of the value is determined by Width.\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting\r
+ the operation at this time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Modify (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN CONST VOID *SetBits,\r
+ IN CONST VOID *ClearBits\r
+)\r
+{\r
+ UINTN PciLibAddress;\r
+\r
+ PciLibAddress = COMMON_TO_PCILIB_ADDRESS (Address);\r
+\r
+ if (Width == EfiPeiPciCfgWidthUint8) {\r
+ PciAndThenOr8 (PciLibAddress, ~(*(UINT8 *)ClearBits), *((UINT8 *) SetBits));\r
+ } else if (Width == EfiPeiPciCfgWidthUint16) {\r
+ PciAndThenOr16 (PciLibAddress, ~ReadUnaligned16 ((UINT16 *) ClearBits), ReadUnaligned16 ((UINT16 *) SetBits));\r
+ } else if (Width == EfiPeiPciCfgWidthUint32) {\r
+ PciAndThenOr32 (PciLibAddress, ~ReadUnaligned32 ((UINT32 *) ClearBits), ReadUnaligned32 ((UINT32 *) SetBits));\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializePciCfg (\r
+ IN EFI_FFS_FILE_HEADER *FfsHeader,\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = EFI_SUCCESS;\r
+\r
+ if ((**PeiServices).Hdr.Revision < PEI_SERVICES_REVISION) {\r
+ //\r
+ // BugBug: Curently, the FrameworkPkg does not define\r
+ // FRAMEWORK_PEI_SERVICES. So, In order to install \r
+ // the PeiServices.PciCfg(), we casttype \r
+ // EFI_PEI_PCI_CFG_PPI to EFI_PEI_PCI_CFG2_PPI.\r
+ // After defining the FRAMEWORK_PEI_SERVICES. this should\r
+ // be updated as:\r
+ // \r
+ // FrameworkPeiServices = (FRAMEWORK_PEI_SERVICES **) PeiServices;\r
+ // (**FrameworkPeiServices).PciCfg = &mPciCfgPpi;\r
+ // \r
+ (**PeiServices).PciCfg = (EFI_PEI_PCI_CFG2_PPI *) &gPciCfgPpi;\r
+ } else {\r
+ (**PeiServices).PciCfg = &gPciCfg2Ppi;\r
+ }\r
+ \r
+ if (!FeaturePcdGet (PcdPciCfgDisable)) {\r
+ Status = (**PeiServices).InstallPpi (PeiServices, &gPciCfgPpiList);\r
+ } \r
+ if (!FeaturePcdGet (PcdPciCfg2Disable)) {\r
+ Status = (**PeiServices).InstallPpi (PeiServices, &gPciCfg2PpiList);\r
+ }\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/**\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __PCICFGPPI_INTERLNAL_H_\r
+#define __PCICFGPPI_INTERLNAL_H_\r
+\r
+#include <PiPei.h>\r
+#include <FrameworkPei.h>\r
+\r
+#include <Ppi/PciCfg2.h>\r
+#include <Ppi/PciCfg.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/PeimEntryPoint.h>\r
+\r
+#include <IndustryStandard\Pci.h>\r
+\r
+#define COMMON_TO_PCILIB_ADDRESS(A) (UINTN)PCI_LIB_ADDRESS( \\r
+ ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &A)->Bus, \\r
+ ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &A)->Device, \\r
+ ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &A)->Function, \\r
+ ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &A)->Register \\r
+ )\r
+\r
+\r
+/**\r
+ Reads from a given location in the PCI configuration space.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+ @param Address The physical address of the access. The format of\r
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+ @param Buffer A pointer to the buffer of data..\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
+ time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Read (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+);\r
+\r
+/**\r
+ Write to a given location in the PCI configuration space.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+ @param Address The physical address of the access. The format of\r
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+ @param Buffer A pointer to the buffer of data..\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
+ time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Write (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+);\r
+\r
+\r
+/**\r
+ PCI read-modify-write operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes. Type\r
+ EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r
+\r
+ @param Address The physical address of the access.\r
+\r
+ @param SetBits Points to value to bitwise-OR with the read configuration value.\r
+\r
+ The size of the value is determined by Width.\r
+\r
+ @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.\r
+ The size of the value is determined by Width.\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting\r
+ the operation at this time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Modify (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN CONST VOID *SetBits,\r
+ IN CONST VOID *ClearBits\r
+);\r
+\r
+\r
+\r
+/**\r
+ PCI read operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param This Pointer to local data for the interface.\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ @param Address The physical address of the access.\r
+ @param Buffer A pointer to the buffer of data.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ @retval EFI_NOT_YET_AVAILABLE The service has not been installed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfgRead (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_PCI_CFG_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ PCI write operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param This Pointer to local data for the interface.\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ @param Address The physical address of the access.\r
+ @param Buffer A pointer to the buffer of data.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ @retval EFI_NOT_YET_AVAILABLE The service has not been installed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfgWrite (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_PCI_CFG_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ PCI read-modify-write operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+ @param This Pointer to local data for the interface.\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ @param Address The physical address of the access.\r
+ @param SetBits Value of the bits to set.\r
+ @param ClearBits Value of the bits to clear.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfgModify (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_PCI_CFG_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN SetBits,\r
+ IN UINTN ClearBits\r
+ );\r
+\r
+//\r
+// Global Variables\r
+//\r
+extern EFI_PEI_PCI_CFG_PPI gPciCfgPpi;\r
+extern EFI_PEI_PPI_DESCRIPTOR gPciCfgPpiList;\r
+\r
+\r
+#endif\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<ModuleSurfaceArea xsi:schemaLocation="http://www.TianoCore.org/2006/Edk2.0 http://www.TianoCore.org/2006/Edk2.0/SurfaceArea.xsd" xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">\r
+ <MsaHeader>\r
+ <ModuleName>PciCfg</ModuleName>\r
+ <ModuleType>PEIM</ModuleType>\r
+ <GuidValue>27A5159D-5E61-4809-919A-422E887101EF</GuidValue>\r
+ <Version>1.0</Version>\r
+ <Abstract>Single Segment Pci Configuration PPI</Abstract>\r
+ <Description>This file declares PciCfg PPI used to access PCI configuration space in PEI</Description>\r
+ <Copyright>Copyright (c) 2006 - 2007, Intel Corporation.</Copyright>\r
+ <License>
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ </License>\r
+ <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>\r
+ </MsaHeader>\r
+ <ModuleDefinitions>\r
+ <SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>\r
+ <BinaryModule>false</BinaryModule>\r
+ <OutputFileBasename>PciCfg</OutputFileBasename>\r
+ </ModuleDefinitions>\r
+ <LibraryClassDefinitions>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>DebugLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>PciLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>PeimEntryPoint</Keyword>\r
+ </LibraryClass>\r
+ </LibraryClassDefinitions>\r
+ <SourceFiles>\r
+ <Filename>PciCfg.dxs</Filename>\r
+ <Filename>PciCfg.c</Filename>\r
+ </SourceFiles>\r
+ <PackageDependencies>\r
+ <Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>\r
+ </PackageDependencies>\r
+ <PPIs>\r
+ <Ppi Usage="ALWAYS_PRODUCED">\r
+ <PpiCName>gEfiPciCfgPpiInServiceTableGuid</PpiCName>\r
+ </Ppi>\r
+ </PPIs>\r
+ <Externs>\r
+ <Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>\r
+ <Specification>EDK_RELEASE_VERSION 0x00020000</Specification>\r
+ <Extern>\r
+ <ModuleEntryPoint>PeimInitializePciCfg</ModuleEntryPoint>\r
+ </Extern>\r
+ </Externs>\r
+</ModuleSurfaceArea>
\ No newline at end of file
$(WORKSPACE)/MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
$(WORKSPACE)/MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
$(WORKSPACE)/MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ $(WORKSPACE)/MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf\r
$(WORKSPACE)/MdeModulePkg/Application/HelloWorld/HelloWorld.inf\r
$(WORKSPACE)/MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
$(WORKSPACE)/MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf\r
--- /dev/null
+#/** @file\r
+# Single Segment Pci Configuration PPI\r
+#\r
+# This file declares PciCfg PPI used to access PCI configuration space in PEI\r
+# Copyright (c) 2006 - 2007, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PcatSingleSegmentPciCfg2Pei\r
+ FILE_GUID = 4F1F379F-2A62-48bb-AC34-D3F135C6E2B7\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+ ENTRY_POINT = PeimInitializePciCfg\r
+\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+ PciCfg2.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
+\r
+[LibraryClasses]\r
+ PeimEntryPoint\r
+ PciLib\r
+ BaseLib\r
+ DebugLib\r
+\r
+\r
+[Ppis]\r
+ gEfiPciCfg2PpiGuid # PPI ALWAYS_PRODUCED\r
+\r
+[Depex]\r
+ TRUE\r
+\r
--- /dev/null
+/**\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/PciCfg2.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/PeimEntryPoint.h>\r
+\r
+#include <IndustryStandard\Pci.h>\r
+\r
+#define COMMON_TO_PCILIB_ADDRESS(A) (UINTN)PCI_LIB_ADDRESS( \\r
+ ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &A)->Bus, \\r
+ ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &A)->Device, \\r
+ ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &A)->Function, \\r
+ ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &A)->Register \\r
+ )\r
+\r
+\r
+/**\r
+ Reads from a given location in the PCI configuration space.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+ @param Address The physical address of the access. The format of\r
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+ @param Buffer A pointer to the buffer of data..\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
+ time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Read (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+);\r
+\r
+/**\r
+ Write to a given location in the PCI configuration space.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+ @param Address The physical address of the access. The format of\r
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+ @param Buffer A pointer to the buffer of data..\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
+ time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Write (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+);\r
+\r
+\r
+/**\r
+ PCI read-modify-write operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes. Type\r
+ EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r
+\r
+ @param Address The physical address of the access.\r
+\r
+ @param SetBits Points to value to bitwise-OR with the read configuration value.\r
+\r
+ The size of the value is determined by Width.\r
+\r
+ @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.\r
+ The size of the value is determined by Width.\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting\r
+ the operation at this time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Modify (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN CONST VOID *SetBits,\r
+ IN CONST VOID *ClearBits\r
+);\r
+\r
+\r
+\r
+/**\r
+ @par Ppi Description:\r
+ The EFI_PEI_PCI_CFG2_PPI interfaces are used to abstract\r
+ accesses to PCI controllers behind a PCI root bridge\r
+ controller.\r
+\r
+ @param Read PCI read services. See the Read() function description.\r
+\r
+ @param Write PCI write services. See the Write() function description.\r
+\r
+ @param Modify PCI read-modify-write services. See the Modify() function description.\r
+\r
+ @param Segment The PCI bus segment which the specified functions will access.\r
+\r
+**/\r
+GLOBAL_REMOVE_IF_UNREFERENCED\r
+EFI_PEI_PCI_CFG2_PPI gPciCfg2Ppi = {\r
+ PciCfg2Read,\r
+ PciCfg2Write,\r
+ PciCfg2Modify\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED\r
+EFI_PEI_PPI_DESCRIPTOR gPciCfg2PpiList = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPciCfg2PpiGuid,\r
+ &gPciCfg2Ppi\r
+};\r
+\r
+/**\r
+ Reads from a given location in the PCI configuration space.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+ @param Address The physical address of the access. The format of\r
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+ @param Buffer A pointer to the buffer of data..\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
+ time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Read (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+)\r
+{\r
+ UINTN PciLibAddress;\r
+\r
+ PciLibAddress = COMMON_TO_PCILIB_ADDRESS (Address);\r
+\r
+ if (Width == EfiPeiPciCfgWidthUint8) {\r
+ *((UINT8 *) Buffer) = PciRead8 (PciLibAddress);\r
+ } else if (Width == EfiPeiPciCfgWidthUint16) {\r
+ *((UINT16 *) Buffer) = PciRead16 (PciLibAddress);\r
+ } else if (Width == EfiPeiPciCfgWidthUint32) {\r
+ *((UINT32 *) Buffer) = PciRead32 (PciLibAddress);\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Write to a given location in the PCI configuration space.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes.\r
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+ @param Address The physical address of the access. The format of\r
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+ @param Buffer A pointer to the buffer of data..\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
+ time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Write (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+)\r
+{\r
+ UINTN PciLibAddress;\r
+\r
+ PciLibAddress = COMMON_TO_PCILIB_ADDRESS (Address);\r
+\r
+ if (Width == EfiPeiPciCfgWidthUint8) {\r
+ PciWrite8 (PciLibAddress, *((UINT8 *) Buffer));\r
+ } else if (Width == EfiPeiPciCfgWidthUint16) {\r
+ PciWrite16 (PciLibAddress, *((UINT16 *) Buffer));\r
+ } else if (Width == EfiPeiPciCfgWidthUint32) {\r
+ PciWrite32 (PciLibAddress, *((UINT32 *) Buffer));\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ PCI read-modify-write operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table\r
+ published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes. Type\r
+ EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r
+\r
+ @param Address The physical address of the access.\r
+\r
+ @param SetBits Points to value to bitwise-OR with the read configuration value.\r
+\r
+ The size of the value is determined by Width.\r
+\r
+ @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.\r
+ The size of the value is determined by Width.\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting\r
+ the operation at this time.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI \r
+PciCfg2Modify (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN CONST VOID *SetBits,\r
+ IN CONST VOID *ClearBits\r
+)\r
+{\r
+ UINTN PciLibAddress;\r
+\r
+ PciLibAddress = COMMON_TO_PCILIB_ADDRESS (Address);\r
+\r
+ if (Width == EfiPeiPciCfgWidthUint8) {\r
+ PciAndThenOr8 (PciLibAddress, ~(*(UINT8 *)ClearBits), *((UINT8 *) SetBits));\r
+ } else if (Width == EfiPeiPciCfgWidthUint16) {\r
+ PciAndThenOr16 (PciLibAddress, ~ReadUnaligned16 ((UINT16 *) ClearBits), ReadUnaligned16 ((UINT16 *) SetBits));\r
+ } else if (Width == EfiPeiPciCfgWidthUint32) {\r
+ PciAndThenOr32 (PciLibAddress, ~ReadUnaligned32 ((UINT32 *) ClearBits), ReadUnaligned32 ((UINT32 *) SetBits));\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializePciCfg (\r
+ IN EFI_FFS_FILE_HEADER *FfsHeader,\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ ASSERT ((**PeiServices).Hdr.Revision >= PEI_SERVICES_REVISION);\r
+\r
+ (**PeiServices).PciCfg = &gPciCfg2Ppi;\r
+ Status = (**PeiServices).InstallPpi (PeiServices, &gPciCfg2PpiList);\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<ModuleSurfaceArea xsi:schemaLocation="http://www.TianoCore.org/2006/Edk2.0 http://www.TianoCore.org/2006/Edk2.0/SurfaceArea.xsd" xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">\r
+ <MsaHeader>\r
+ <ModuleName>PciCfg</ModuleName>\r
+ <ModuleType>PEIM</ModuleType>\r
+ <GuidValue>27A5159D-5E61-4809-919A-422E887101EF</GuidValue>\r
+ <Version>1.0</Version>\r
+ <Abstract>Single Segment Pci Configuration PPI</Abstract>\r
+ <Description>This file declares PciCfg PPI used to access PCI configuration space in PEI</Description>\r
+ <Copyright>Copyright (c) 2006 - 2007, Intel Corporation.</Copyright>\r
+ <License>
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ </License>\r
+ <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>\r
+ </MsaHeader>\r
+ <ModuleDefinitions>\r
+ <SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>\r
+ <BinaryModule>false</BinaryModule>\r
+ <OutputFileBasename>PciCfg</OutputFileBasename>\r
+ </ModuleDefinitions>\r
+ <LibraryClassDefinitions>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>DebugLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>PciLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>PeimEntryPoint</Keyword>\r
+ </LibraryClass>\r
+ </LibraryClassDefinitions>\r
+ <SourceFiles>\r
+ <Filename>PciCfg.dxs</Filename>\r
+ <Filename>PciCfg.c</Filename>\r
+ </SourceFiles>\r
+ <PackageDependencies>\r
+ <Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>\r
+ </PackageDependencies>\r
+ <PPIs>\r
+ <Ppi Usage="ALWAYS_PRODUCED">\r
+ <PpiCName>gEfiPciCfgPpiInServiceTableGuid</PpiCName>\r
+ </Ppi>\r
+ </PPIs>\r
+ <Externs>\r
+ <Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>\r
+ <Specification>EDK_RELEASE_VERSION 0x00020000</Specification>\r
+ <Extern>\r
+ <ModuleEntryPoint>PeimInitializePciCfg</ModuleEntryPoint>\r
+ </Extern>\r
+ </Externs>\r
+</ModuleSurfaceArea>
\ No newline at end of file