/** @file\r
Enable SMM profile.\r
\r
-Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2012 - 2023, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
}\r
\r
SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;\r
+ ASSERT (SizeOfMemorySpace <= 52);\r
+\r
//\r
- // Calculate the table entries of PML4E and PDPTE.\r
+ // Calculate the table entries of PML5E, PML4E and PDPTE.\r
//\r
NumberOfPml5Entries = 1;\r
if (SizeOfMemorySpace > 48) {\r
- NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);\r
- SizeOfMemorySpace = 48;\r
+ if (Enable5LevelPaging) {\r
+ NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);\r
+ }\r
+\r
+ SizeOfMemorySpace = 48;\r
}\r
\r
NumberOfPml4Entries = 1;\r