UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)

https://bugzilla.tianocore.org/show_bug.cgi?id=176

Update CPUID leaf and sub-leaf indexes and structures as described by
Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 2A, September 2016, CPUID instruction.

Summary of incompatible changes:
1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed
from 'PQE' to 'RDT_A'.

2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring
Information' related definitions
Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to
'CPUID_INTEL_RDT_MONITORING'.
Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'.
Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'.

3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement
Information' related definitions
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to
'CPUID_INTEL_RDT_ALLOCATION'.
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to
'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'.
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'.

This commit also updates the relating codes in
UefiCpuPkg/Application/Cpuid to reflect the changes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c b/UefiCpuPkg/Application/Cpuid/Cpuid.c
index ac14c41ed650853cf74fbbe07bb2e6d30d7f5f97..2efad6840548b0d56e8eab88927b3175a0df30db 100644 (file)
--- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
+++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
@@ -88,13 +88,14 @@ CPUID_CACHE_INFO_DESCRIPTION  mCpuidCacheInfoDescription[] = {
   { 0x56 , "TLB"      , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r
   { 0x57 , "TLB"      , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r
   { 0x59 , "TLB"      , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r
   { 0x56 , "TLB"      , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r
   { 0x57 , "TLB"      , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r
   { 0x59 , "TLB"      , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r

-  { 0x5A , "TLB"      , "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r
+  { 0x5A , "TLB"      , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r

   { 0x5B , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r
   { 0x5C , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r
   { 0x5D , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r
   { 0x60 , "Cache"    , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r
   { 0x61 , "TLB"      , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r
   { 0x5B , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r
   { 0x5C , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r
   { 0x5D , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r
   { 0x60 , "Cache"    , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r
   { 0x61 , "TLB"      , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r

-  { 0x63 , "TLB"      , "Data TLB: 1 GByte pages, 4-way set associative, 4 entries" },\r
+  { 0x63 , "TLB"      , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },\r
+  { 0x64 , "TLB"      , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },\r

   { 0x66 , "Cache"    , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r
   { 0x67 , "Cache"    , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r
   { 0x68 , "Cache"    , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r
   { 0x66 , "Cache"    , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r
   { 0x67 , "Cache"    , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r
   { 0x68 , "Cache"    , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r


@@ -133,6 +134,7 @@ CPUID_CACHE_INFO_DESCRIPTION  mCpuidCacheInfoDescription[] = {
   { 0xC1 , "STLB"     , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r
   { 0xC2 , "DTLB"     , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r
   { 0xC3 , "STLB"     , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r
   { 0xC1 , "STLB"     , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r
   { 0xC2 , "DTLB"     , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r
   { 0xC3 , "STLB"     , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r

+  { 0xC4 , "DTLB"     , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },\r

   { 0xCA , "STLB"     , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r
   { 0xD0 , "Cache"    , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
   { 0xD1 , "Cache"    , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r
   { 0xCA , "STLB"     , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r
   { 0xD0 , "Cache"    , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
   { 0xD1 , "Cache"    , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r


@@ -604,18 +606,24 @@ CpuidStructuredExtendedFeatureFlags (
       PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);\r
       PRINT_BIT_FIELD (Ebx, INVPCID);\r
       PRINT_BIT_FIELD (Ebx, RTM);\r
       PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);\r
       PRINT_BIT_FIELD (Ebx, INVPCID);\r
       PRINT_BIT_FIELD (Ebx, RTM);\r

-      PRINT_BIT_FIELD (Ebx, PQM);\r
+      PRINT_BIT_FIELD (Ebx, RDT_M);\r

       PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);\r
       PRINT_BIT_FIELD (Ebx, MPX);\r
       PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);\r
       PRINT_BIT_FIELD (Ebx, MPX);\r

-      PRINT_BIT_FIELD (Ebx, PQE);\r
+      PRINT_BIT_FIELD (Ebx, RDT_A);\r

       PRINT_BIT_FIELD (Ebx, RDSEED);\r
       PRINT_BIT_FIELD (Ebx, ADX);\r
       PRINT_BIT_FIELD (Ebx, SMAP);\r
       PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);\r
       PRINT_BIT_FIELD (Ebx, RDSEED);\r
       PRINT_BIT_FIELD (Ebx, ADX);\r
       PRINT_BIT_FIELD (Ebx, SMAP);\r
       PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);\r

+      PRINT_BIT_FIELD (Ebx, CLWB);\r

       PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);\r
       PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);\r

+      PRINT_BIT_FIELD (Ebx, SHA);\r

       PRINT_BIT_FIELD (Ecx, PREFETCHWT1);\r
       PRINT_BIT_FIELD (Ecx, PREFETCHWT1);\r

+      PRINT_BIT_FIELD (Ecx, UMIP);\r

       PRINT_BIT_FIELD (Ecx, PKU);\r
       PRINT_BIT_FIELD (Ecx, OSPKE);\r
       PRINT_BIT_FIELD (Ecx, PKU);\r
       PRINT_BIT_FIELD (Ecx, OSPKE);\r

+      PRINT_BIT_FIELD (Ecx, MAWAU);\r
+      PRINT_BIT_FIELD (Ecx, RDPID);\r
+      PRINT_BIT_FIELD (Ecx, SGX_LC);\r

     }\r
   }\r
 }\r
     }\r
   }\r
 }\r


@@ -815,78 +823,81 @@ CpuidExtendedStateMainLeaf (
 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Display CPUID_PLATFORM_QOS_MONITORING enumeration sub-leaf.\r
+  Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf.\r

 \r
 **/\r
 VOID\r
 \r
 **/\r
 VOID\r

-CpuidPlatformQosMonitoringEnumerationSubLeaf (\r
+CpuidIntelRdtMonitoringEnumerationSubLeaf (\r

   VOID\r
   )\r
 {\r
   UINT32                                                  Ebx;\r
   VOID\r
   )\r
 {\r
   UINT32                                                  Ebx;\r

-  CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX  Edx;\r
+  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX     Edx;\r

 \r
 \r

-  if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {\r
+  if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r

     return;\r
   }\r
 \r
   AsmCpuidEx (\r
     return;\r
   }\r
 \r
   AsmCpuidEx (\r

-    CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,\r
+    CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r

     NULL, &Ebx, NULL, &Edx.Uint32\r
     );\r
     NULL, &Ebx, NULL, &Edx.Uint32\r
     );\r

-  Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF);\r
+  Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);\r

   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);\r
   PRINT_VALUE     (Ebx, Maximum_RMID_Range);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);\r
   PRINT_VALUE     (Ebx, Maximum_RMID_Range);\r

-  PRINT_BIT_FIELD (Edx, L3CacheQosEnforcement);\r
+  PRINT_BIT_FIELD (Edx, L3CacheRDT_M);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Display CPUID_PLATFORM_QOS_MONITORING capability sub-leaf.\r
+  Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf.\r

 \r
 **/\r
 VOID\r
 \r
 **/\r
 VOID\r

-CpuidPlatformQosMonitoringCapabilitySubLeaf (\r
+CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (\r

   VOID\r
   )\r
 {\r
   UINT32                                                 Ebx;\r
   UINT32                                                 Ecx;\r
   VOID\r
   )\r
 {\r
   UINT32                                                 Ebx;\r
   UINT32                                                 Ecx;\r

-  CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX  Edx;\r
+  CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX       Edx;\r

 \r
 \r

-  if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {\r
+  if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r

     return;\r
   }\r
 \r
   AsmCpuidEx (\r
     return;\r
   }\r
 \r
   AsmCpuidEx (\r

-    CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,\r
+    CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r

     NULL, &Ebx, &Ecx, &Edx.Uint32\r
     );\r
     NULL, &Ebx, &Ecx, &Edx.Uint32\r
     );\r

-  Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF);\r
+  Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);\r

   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);\r
   PRINT_VALUE     (Ebx, OccupancyConversionFactor);\r
   PRINT_VALUE     (Ecx, Maximum_RMID_Range);\r
   PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);\r
   PRINT_VALUE     (Ebx, OccupancyConversionFactor);\r
   PRINT_VALUE     (Ecx, Maximum_RMID_Range);\r
   PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);\r

+  PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);\r
+  PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Display CPUID_PLATFORM_QOS_ENFORCEMENT sub-leaf.\r
+  Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration\r
+  sub-leaf.\r

 \r
 **/\r
 VOID\r
 \r
 **/\r
 VOID\r

-CpuidPlatformQosEnforcementResidSubLeaf (\r
+CpuidIntelRdtAllocationL3CacheSubLeaf (\r

   VOID\r
   )\r
 {\r
   VOID\r
   )\r
 {\r

-  CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;\r
+  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX  Eax;\r

   UINT32                                            Ebx;\r
   UINT32                                            Ebx;\r

-  CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;\r
-  CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;\r
+  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX  Ecx;\r
+  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX  Edx;\r

 \r
   AsmCpuidEx (\r
 \r
   AsmCpuidEx (\r

-    CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,\r
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r

     &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
     );\r
     &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
     );\r

-  Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF);\r
+  Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);\r

   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
   PRINT_BIT_FIELD (Eax, CapacityLength);\r
   PRINT_VALUE     (Ebx, AllocationUnitBitMap);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
   PRINT_BIT_FIELD (Eax, CapacityLength);\r
   PRINT_VALUE     (Ebx, AllocationUnitBitMap);\r


@@ -896,29 +907,56 @@ CpuidPlatformQosEnforcementResidSubLeaf (
 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Display CPUID_PLATFORM_QOS_ENFORCEMENT main leaf and sub-leaf.\r
+  Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration\r
+  sub-leaf.\r

 \r
 **/\r
 VOID\r
 \r
 **/\r
 VOID\r

-CpuidPlatformQosEnforcementMainLeaf (\r
+CpuidIntelRdtAllocationL2CacheSubLeaf (\r

   VOID\r
   )\r
 {\r
   VOID\r
   )\r
 {\r

-  CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX  Ebx;\r
+  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX  Eax;\r
+  UINT32                                            Ebx;\r
+  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX  Edx;\r
+\r
+  AsmCpuidEx (\r
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
+    &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+    );\r
+  Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);\r
+  Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
+  PRINT_BIT_FIELD (Eax, CapacityLength);\r
+  PRINT_VALUE     (Ebx, AllocationUnitBitMap);\r
+  PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
+}\r
+\r
+/**\r
+  Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves.\r
+\r
+**/\r
+VOID\r
+CpuidIntelRdtAllocationMainLeaf (\r
+  VOID\r
+  )\r
+{\r
+  CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX  Ebx;\r

 \r
 \r

-  if (CPUID_PLATFORM_QOS_ENFORCEMENT > gMaximumBasicFunction) {\r
+  if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) {\r

     return;\r
   }\r
 \r
   AsmCpuidEx (\r
     return;\r
   }\r
 \r
   AsmCpuidEx (\r

-    CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,\r
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r

     NULL, &Ebx.Uint32, NULL, NULL\r
     );\r
     NULL, &Ebx.Uint32, NULL, NULL\r
     );\r

-  Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF);\r
+  Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);\r

   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx.Uint32, 0, 0);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx.Uint32, 0, 0);\r

-  PRINT_BIT_FIELD (Ebx, L3CacheQosEnforcement);\r
+  PRINT_BIT_FIELD (Ebx, L3CacheAllocation);\r
+  PRINT_BIT_FIELD (Ebx, L2CacheAllocation);\r

 \r
 \r

-  CpuidPlatformQosEnforcementResidSubLeaf ();\r
+  CpuidIntelRdtAllocationL3CacheSubLeaf ();\r
+  CpuidIntelRdtAllocationL2CacheSubLeaf ();\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -1093,6 +1131,8 @@ CpuidIntelProcessorTraceMainLeaf (
   PRINT_BIT_FIELD (Ebx, ConfigurablePsb);\r
   PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);\r
   PRINT_BIT_FIELD (Ebx, Mtc);\r
   PRINT_BIT_FIELD (Ebx, ConfigurablePsb);\r
   PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);\r
   PRINT_BIT_FIELD (Ebx, Mtc);\r

+  PRINT_BIT_FIELD (Ebx, PTWrite);\r
+  PRINT_BIT_FIELD (Ebx, PowerEventTrace);\r

   PRINT_BIT_FIELD (Ecx, RTIT);\r
   PRINT_BIT_FIELD (Ecx, ToPA);\r
   PRINT_BIT_FIELD (Ecx, SingleRangeOutput);\r
   PRINT_BIT_FIELD (Ecx, RTIT);\r
   PRINT_BIT_FIELD (Ecx, ToPA);\r
   PRINT_BIT_FIELD (Ecx, SingleRangeOutput);\r


@@ -1113,14 +1153,15 @@ CpuidTimeStampCounter (
 {\r
   UINT32  Eax;\r
   UINT32  Ebx;\r
 {\r
   UINT32  Eax;\r
   UINT32  Ebx;\r

+  UINT32  Ecx;\r

 \r
   if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {\r
     return;\r
   }\r
 \r
 \r
   if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {\r
     return;\r
   }\r
 \r

-  AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);\r
+  AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r

   Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);\r
   Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);\r

-  Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx, 0, 0);\r
+  Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx, Ecx, 0);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -1446,9 +1487,9 @@ UefiMain (
   CpuidArchitecturalPerformanceMonitoring ();\r
   CpuidExtendedTopology ();\r
   CpuidExtendedStateMainLeaf ();\r
   CpuidArchitecturalPerformanceMonitoring ();\r
   CpuidExtendedTopology ();\r
   CpuidExtendedStateMainLeaf ();\r

-  CpuidPlatformQosMonitoringEnumerationSubLeaf ();\r
-  CpuidPlatformQosMonitoringCapabilitySubLeaf ();\r
-  CpuidPlatformQosEnforcementMainLeaf ();\r
+  CpuidIntelRdtMonitoringEnumerationSubLeaf ();\r
+  CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ();\r
+  CpuidIntelRdtAllocationMainLeaf ();\r

   CpuidEnumerationOfIntelSgx ();\r
   CpuidIntelProcessorTraceMainLeaf ();\r
   CpuidTimeStampCounter ();\r
   CpuidEnumerationOfIntelSgx ();\r
   CpuidIntelProcessorTraceMainLeaf ();\r
   CpuidTimeStampCounter ();\r

diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h
index 864108da62220cf45ccfb33e3ad1b85626533741..5eb96505532d7ba0b9b62a5a782091495c375c29 100644 (file)
--- a/UefiCpuPkg/Include/Register/Cpuid.h
+++ b/UefiCpuPkg/Include/Register/Cpuid.h
@@ -17,7 +17,7 @@
 \r
   @par Specification Reference:\r
   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r
 \r
   @par Specification Reference:\r
   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r

-  December 2015, CPUID instruction.\r
+  September 2016, CPUID instruction.\r

 \r
 **/\r
 \r
 \r
 **/\r
 \r


@@ -433,11 +433,10 @@ typedef union {
     ///\r
     UINT32  PGE:1;\r
     ///\r
     ///\r
     UINT32  PGE:1;\r
     ///\r

-    /// [Bit 14] Machine Check Architecture.  The Machine Check Architecture,\r
-    /// which provides a compatible mechanism for error reporting in P6 family,\r
-    /// Pentium 4, Intel Xeon processors, and future processors, is supported.\r
-    /// The MCG_CAP MSR contains feature bits describing how many banks of error\r
-    /// reporting MSRs are supported.\r
+    /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine\r
+    /// Check Architecture of reporting machine errors is supported. The MCG_CAP\r
+    /// MSR contains feature bits describing how many banks of error reporting\r
+    /// MSRs are supported.\r

     ///\r
     UINT32  MCA:1;\r
     ///\r
     ///\r
     UINT32  MCA:1;\r
     ///\r


@@ -634,13 +633,16 @@ typedef union {
   <tr><td> 0x56 </td><td> TLB     </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>\r
   <tr><td> 0x57 </td><td> TLB     </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>\r
   <tr><td> 0x59 </td><td> TLB     </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>\r
   <tr><td> 0x56 </td><td> TLB     </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>\r
   <tr><td> 0x57 </td><td> TLB     </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>\r
   <tr><td> 0x59 </td><td> TLB     </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>\r

-  <tr><td> 0x5A </td><td> TLB     </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
+  <tr><td> 0x5A </td><td> TLB     </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r

   <tr><td> 0x5B </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>\r
   <tr><td> 0x5C </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>\r
   <tr><td> 0x5D </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>\r
   <tr><td> 0x60 </td><td> Cache   </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0x61 </td><td> TLB     </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>\r
   <tr><td> 0x5B </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>\r
   <tr><td> 0x5C </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>\r
   <tr><td> 0x5D </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>\r
   <tr><td> 0x60 </td><td> Cache   </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0x61 </td><td> TLB     </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>\r

-  <tr><td> 0x63 </td><td> TLB     </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>\r
+  <tr><td> 0x63 </td><td> TLB     </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,\r
+                                            32 entries and a separate array with 1 GByte pages, 4-way set associative,\r
+                                            4 entries</td></tr>\r
+  <tr><td> 0x64 </td><td> TLB     </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>\r

   <tr><td> 0x66 </td><td> Cache   </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0x67 </td><td> Cache   </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0x68 </td><td> Cache   </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0x66 </td><td> Cache   </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0x67 </td><td> Cache   </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0x68 </td><td> Cache   </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>\r


@@ -686,6 +688,7 @@ typedef union {
   <tr><td> 0xC2 </td><td> DTLB    </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>\r
   <tr><td> 0xC3 </td><td> STLB    </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,\r
                                             1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>\r
   <tr><td> 0xC2 </td><td> DTLB    </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>\r
   <tr><td> 0xC3 </td><td> STLB    </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,\r
                                             1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>\r

+  <tr><td> 0xC4 </td><td> DTLB    </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>\r

   <tr><td> 0xCA </td><td> STLB    </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>\r
   <tr><td> 0xD0 </td><td> Cache   </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0xD1 </td><td> Cache   </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0xCA </td><td> STLB    </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>\r
   <tr><td> 0xD0 </td><td> Cache   </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
   <tr><td> 0xD1 </td><td> Cache   </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>\r


@@ -1349,10 +1352,10 @@ typedef union {
     ///\r
     UINT32  RTM:1;\r
     ///\r
     ///\r
     UINT32  RTM:1;\r
     ///\r

-    /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)\r
-    /// capability if 1.\r
+    /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
+    /// Monitoring capability if 1.\r

     ///\r
     ///\r

-    UINT32  PQM:1;\r
+    UINT32  RDT_M:1;\r

     ///\r
     /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r
     ///\r
     ///\r
     /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r
     ///\r


@@ -1362,10 +1365,10 @@ typedef union {
     ///\r
     UINT32  MPX:1;\r
     ///\r
     ///\r
     UINT32  MPX:1;\r
     ///\r

-    /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)\r
-    /// capability if 1.\r
+    /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
+    /// Allocation capability if 1.\r

     ///\r
     ///\r

-    UINT32  PQE:1;\r
+    UINT32  RDT_A:1;\r

     UINT32  Reserved2:2;\r
     ///\r
     /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r
     UINT32  Reserved2:2;\r
     ///\r
     /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r


@@ -1386,13 +1389,22 @@ typedef union {
     /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r
     ///\r
     UINT32  CLFLUSHOPT:1;\r
     /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r
     ///\r
     UINT32  CLFLUSHOPT:1;\r

-    UINT32  Reserved4:1;\r
+    ///\r
+    /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.\r
+    ///\r
+    UINT32  CLWB:1;\r

     ///\r
     /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r
     /// extensions.\r
     ///\r
     UINT32  IntelProcessorTrace:1;\r
     ///\r
     /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r
     /// extensions.\r
     ///\r
     UINT32  IntelProcessorTrace:1;\r

-    UINT32  Reserved5:6;\r
+    UINT32  Reserved4:3;\r
+    ///\r
+    /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)\r
+    /// SHA Extensions) if 1.\r
+    ///\r
+    UINT32  SHA:1;\r
+    UINT32  Reserved5:2;\r

   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r


@@ -1414,7 +1426,11 @@ typedef union {
     /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r
     ///\r
     UINT32  PREFETCHWT1:1;\r
     /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r
     ///\r
     UINT32  PREFETCHWT1:1;\r

-    UINT32  Reserved1:2;\r
+    UINT32  Reserved1:1;\r
+    ///\r
+    /// [Bit 2] Supports user-mode instruction prevention if 1.\r
+    ///\r
+    UINT32  UMIP:1;\r

     ///\r
     /// [Bit 3] Supports protection keys for user-mode pages if 1.\r
     ///\r
     ///\r
     /// [Bit 3] Supports protection keys for user-mode pages if 1.\r
     ///\r


@@ -1424,7 +1440,22 @@ typedef union {
     /// RDPKRU/WRPKRU instructions).\r
     ///\r
     UINT32  OSPKE:1;\r
     /// RDPKRU/WRPKRU instructions).\r
     ///\r
     UINT32  OSPKE:1;\r

-    UINT32  Reserved2:27;\r
+    UINT32  Reserved2:12;\r
+    ///\r
+    /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r
+    /// in 64-bit mode.\r
+    ///\r
+    UINT32  MAWAU:5;\r
+    ///\r
+    /// [Bit 22] Supports Read Processor ID if 1.\r
+    ///\r
+    UINT32  RDPID:1;\r
+    UINT32  Reserved3:7;\r
+    ///\r
+    /// [Bit 30] Supports SGX Launch Configuration if 1.\r
+    ///\r
+    UINT32  SGX_LC:1;\r
+    UINT32  Reserved4:1;\r

   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r


@@ -1756,7 +1787,7 @@ typedef union {
                 enabled.\r
   @retval  ECX  Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
                 area) of the XSAVE/XRSTOR save area required by all supported\r
                 enabled.\r
   @retval  ECX  Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
                 area) of the XSAVE/XRSTOR save area required by all supported\r

-                features in the processor, i.e all the valid bit fields in XCR0.\r
+                features in the processor, i.e., all the valid bit fields in XCR0.\r

   @retval  EDX  Reports the supported bits of the upper 32 bits of XCR0.\r
                 XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r
 \r
   @retval  EDX  Reports the supported bits of the upper 32 bits of XCR0.\r
                 XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r
 \r


@@ -1991,45 +2022,46 @@ typedef union {
 \r
 \r
 /**\r
 \r
 \r
 /**\r

-  CPUID Platform QoS Monitoring Information\r
+  CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r

 \r
 \r

-  @param   EAX  CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
-  @param   ECX  CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
-                CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF  (0x01).\r
+  @param   EAX  CPUID_INTEL_RDT_MONITORING (0x0F)\r
+  @param   ECX  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
+                CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).\r

 \r
 **/\r
 \r
 **/\r

-#define CPUID_PLATFORM_QOS_MONITORING                       0x0F\r
+#define CPUID_INTEL_RDT_MONITORING                          0x0F\r

 \r
 /**\r
 \r
 /**\r

-  CPUID Platform QoS Monitoring Information Enumeration Sub-leaf\r
+  CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
+  Enumeration Sub-leaf\r

 \r
 \r

-  @param   EAX  CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
-  @param   ECX  CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r
+  @param   EAX  CPUID_INTEL_RDT_MONITORING (0x0F)\r
+  @param   ECX  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r

 \r
   @retval  EAX  Reserved.\r
   @retval  EBX  Maximum range (zero-based) of RMID within this physical\r
                 processor of all types.\r
   @retval  ECX  Reserved.\r
 \r
   @retval  EAX  Reserved.\r
   @retval  EBX  Maximum range (zero-based) of RMID within this physical\r
                 processor of all types.\r
   @retval  ECX  Reserved.\r

-  @retval  EDX  L3 Cache QoS Monitoring Information Enumeration described by the\r
-                type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r
+  @retval  EDX  L3 Cache Intel RDT Monitoring Information Enumeration described by\r
+                the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r

 \r
   <b>Example usage</b>\r
   @code\r
   UINT32                                                  Ebx;\r
 \r
   <b>Example usage</b>\r
   @code\r
   UINT32                                                  Ebx;\r

-  CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX  Edx;\r
+  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX     Edx;\r

 \r
   AsmCpuidEx (\r
 \r
   AsmCpuidEx (\r

-    CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,\r
+    CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r

     NULL, &Ebx, NULL, &Edx.Uint32\r
     );\r
   @endcode\r
 **/\r
     NULL, &Ebx, NULL, &Edx.Uint32\r
     );\r
   @endcode\r
 **/\r

-#define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF  0x00\r
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF     0x00\r

 \r
 /**\r
 \r
 /**\r

-  CPUID Platform QoS Monitoring Information EDX for CPUID leaf\r
-  #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
-  #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.\r
+  CPUID Intel RDT Monitoring Information EDX for CPUID leaf\r
+  #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
+  #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.\r

 **/\r
 typedef union {\r
   ///\r
 **/\r
 typedef union {\r
   ///\r


@@ -2038,47 +2070,47 @@ typedef union {
   struct {\r
     UINT32  Reserved1:1;\r
     ///\r
   struct {\r
     UINT32  Reserved1:1;\r
     ///\r

-    /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.\r
+    /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.\r

     ///\r
     ///\r

-    UINT32  L3CacheQosEnforcement:1;\r
+    UINT32  L3CacheRDT_M:1;\r

     UINT32  Reserved2:30;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r
     UINT32  Reserved2:30;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r

-} CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
+} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r

 \r
 /**\r
 \r
 /**\r

-  CPUID Platform QoS Monitoring Information Capability Sub-leaf\r
+  CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf\r

 \r
 \r

-  @param   EAX  CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
-  @param   ECX  CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)\r
+  @param   EAX  CPUID_INTEL_RDT_MONITORING (0x0F)\r
+  @param   ECX  CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)\r

 \r
   @retval  EAX  Reserved.\r
   @retval  EBX  Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r
   @retval  ECX  Maximum range (zero-based) of RMID of this resource type.\r
 \r
   @retval  EAX  Reserved.\r
   @retval  EBX  Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r
   @retval  ECX  Maximum range (zero-based) of RMID of this resource type.\r

-  @retval  EDX  L3 Cache QoS Monitoring Capability information described by the\r
-                type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.\r
+  @retval  EDX  L3 Cache Intel RDT Monitoring Capability information described by the\r
+                type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.\r

 \r
   <b>Example usage</b>\r
   @code\r
 \r
   <b>Example usage</b>\r
   @code\r

-  UINT32                                                 Ebx;\r
-  UINT32                                                 Ecx;\r
-  CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX  Edx;\r
+  UINT32                                            Ebx;\r
+  UINT32                                            Ecx;\r
+  CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX  Edx;\r

 \r
   AsmCpuidEx (\r
 \r
   AsmCpuidEx (\r

-    CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,\r
+    CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r

     NULL, &Ebx, &Ecx, &Edx.Uint32\r
     );\r
   @endcode\r
 **/\r
     NULL, &Ebx, &Ecx, &Edx.Uint32\r
     );\r
   @endcode\r
 **/\r

-#define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF   0x01\r
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF        0x01\r

 \r
 /**\r
 \r
 /**\r

-  CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf\r
-  #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
-  #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.\r
+  CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf\r
+  #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
+  #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.\r

 **/\r
 typedef union {\r
   ///\r
 **/\r
 typedef union {\r
   ///\r


@@ -2089,53 +2121,61 @@ typedef union {
     /// [Bit 0] Supports L3 occupancy monitoring if 1.\r
     ///\r
     UINT32  L3CacheOccupancyMonitoring:1;\r
     /// [Bit 0] Supports L3 occupancy monitoring if 1.\r
     ///\r
     UINT32  L3CacheOccupancyMonitoring:1;\r

-    UINT32  Reserved:31;\r
+    ///\r
+    /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.\r
+    ///\r
+    UINT32  L3CacheTotalBandwidthMonitoring:1;\r
+    ///\r
+    /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.\r
+    ///\r
+    UINT32  L3CacheLocalBandwidthMonitoring:1;\r
+    UINT32  Reserved:29;\r

   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r

-} CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;\r
+} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;\r

 \r
 \r
 /**\r
 \r
 \r
 /**\r

-  CPUID Platform QoS Enforcement Information\r
+  CPUID Intel Resource Director Technology (Intel RDT) Allocation Information\r

 \r
 \r

-  @param   EAX  CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).\r
-  @param   ECX  CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
-                CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).\r
-                Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
+  @param   EAX  CPUID_INTEL_RDT_ALLOCATION (0x10).\r
+  @param   ECX  CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r
+                CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).\r
+                CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).\r

 **/\r
 **/\r

-#define CPUID_PLATFORM_QOS_ENFORCEMENT                      0x10\r
+#define CPUID_INTEL_RDT_ALLOCATION                          0x10\r

 \r
 /**\r
 \r
 /**\r

-  CPUID Platform QoS Enforcement Information\r
+  Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf\r

 \r
 \r

-  @param   EAX  CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
-  @param   ECX  CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
+  @param   EAX  CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+  @param   ECX  CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r

 \r
   @retval  EAX  Reserved.\r
 \r
   @retval  EAX  Reserved.\r

-  @retval  EBX  L3 Cache QoS Enforcement information described by the\r
-                type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.\r
+  @retval  EBX  L3 and L2 Cache Allocation Technology information described by\r
+                the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.\r

   @retval  ECX  Reserved.\r
   @retval  EDX  Reserved.\r
 \r
   <b>Example usage</b>\r
   @code\r
   @retval  ECX  Reserved.\r
   @retval  EDX  Reserved.\r
 \r
   <b>Example usage</b>\r
   @code\r

-  CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX  Ebx;\r
+  CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX  Ebx;\r

 \r
   AsmCpuidEx (\r
 \r
   AsmCpuidEx (\r

-    CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,\r
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r

     NULL, &Ebx.Uint32, NULL, NULL\r
     );\r
   @endcode\r
 **/\r
     NULL, &Ebx.Uint32, NULL, NULL\r
     );\r
   @endcode\r
 **/\r

-#define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF            0x00\r
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF     0x00\r

 \r
 /**\r
 \r
 /**\r

-  CPUID Platform QoS Enforcement Information EBX for CPUID leaf\r
-  #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
-  #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.\r
+  CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.\r

 **/\r
 typedef union {\r
   ///\r
 **/\r
 typedef union {\r
   ///\r


@@ -2144,52 +2184,55 @@ typedef union {
   struct {\r
     UINT32  Reserved1:1;\r
     ///\r
   struct {\r
     UINT32  Reserved1:1;\r
     ///\r

-    /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.\r
+    /// [Bit 1] Supports L3 Cache Allocation Technology if 1.\r

     ///\r
     ///\r

-    UINT32  L3CacheQosEnforcement:1;\r
-    UINT32  Reserved2:30;\r
+    UINT32  L3CacheAllocation:1;\r
+    ///\r
+    /// [Bit 2] Supports L2 Cache Allocation Technology if 1.\r
+    ///\r
+    UINT32  L2CacheAllocation:1;\r
+    UINT32  Reserved2:29;\r

   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r

-} CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;\r
+} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;\r

 \r
 \r
 /**\r
 \r
 \r
 /**\r

-  CPUID Platform QoS Enforcement Information\r
+  L3 Cache Allocation Technology Enumeration Sub-leaf\r

 \r
 \r

-  @param   EAX  CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
-  @param   ECX  CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)\r
-                Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
+  @param   EAX  CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+  @param   ECX  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)\r

 \r
 \r

-  @retval  EAX  RESID L3 Cache3 QoS Enforcement information described by the\r
-                type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.\r
+  @retval  EAX  RESID L3 Cache Allocation Technology information described by\r
+                the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.\r

   @retval  EBX  Bit-granular map of isolation/contention of allocation units.\r
   @retval  EBX  Bit-granular map of isolation/contention of allocation units.\r

-  @retval  ECX  RESID L3 Cache3 QoS Enforcement information described by the\r
-                type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.\r
-  @retval  EDX  RESID L3 Cache3 QoS Enforcement information described by the\r
-                type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.\r
+  @retval  ECX  RESID L3 Cache Allocation Technology information described by\r
+                the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.\r
+  @retval  EDX  RESID L3 Cache Allocation Technology information described by\r
+                the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.\r

 \r
   <b>Example usage</b>\r
   @code\r
 \r
   <b>Example usage</b>\r
   @code\r

-  CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;\r
+  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX  Eax;\r

   UINT32                                            Ebx;\r
   UINT32                                            Ebx;\r

-  CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;\r
-  CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;\r
+  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX  Ecx;\r
+  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX  Edx;\r

 \r
   AsmCpuidEx (\r
 \r
   AsmCpuidEx (\r

-    CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,\r
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r

     &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
     );\r
   @endcode\r
 **/\r
     &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
     );\r
   @endcode\r
 **/\r

-#define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF       0x01\r
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF        0x01\r

 \r
 /**\r
 \r
 /**\r

-  CPUID Platform QoS Enforcement Information EAX for CPUID leaf\r
-  #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
-  #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+  CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r

 **/\r
 typedef union {\r
   ///\r
 **/\r
 typedef union {\r
   ///\r


@@ -2197,21 +2240,22 @@ typedef union {
   ///\r
   struct {\r
     ///\r
   ///\r
   struct {\r
     ///\r

-    /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.\r
+    /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
+    /// using minus-one notation.\r

     ///\r
     ///\r

-    UINT32  CapacityLength:4;\r
-    UINT32  Reserved:28;\r
+    UINT32  CapacityLength:5;\r
+    UINT32  Reserved:27;\r

   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r

-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;\r

 \r
 /**\r
 \r
 /**\r

-  CPUID Platform QoS Enforcement Information ECX for CPUID leaf\r
-  #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
-  #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+  CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r

 **/\r
 typedef union {\r
   ///\r
 **/\r
 typedef union {\r
   ///\r


@@ -2233,12 +2277,12 @@ typedef union {
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r

-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;\r

 \r
 /**\r
 \r
 /**\r

-  CPUID Platform QoS Enforcement Information EDX for CPUID leaf\r
-  #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
-  #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+  CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r

 **/\r
 typedef union {\r
   ///\r
 **/\r
 typedef union {\r
   ///\r


@@ -2255,7 +2299,79 @@ typedef union {
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r
   /// All bit fields as a 32-bit value\r
   ///\r
   UINT32  Uint32;\r

-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;\r
+\r
+/**\r
+  L2 Cache Allocation Technology Enumeration Sub-leaf\r
+\r
+  @param   EAX  CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+  @param   ECX  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)\r
+\r
+  @retval  EAX  RESID L2 Cache Allocation Technology information described by\r
+                the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.\r
+  @retval  EBX  Bit-granular map of isolation/contention of allocation units.\r
+  @retval  ECX  Reserved.\r
+  @retval  EDX  RESID L2 Cache Allocation Technology information described by\r
+                the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX  Eax;\r
+  UINT32                                            Ebx;\r
+  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX  Edx;\r
+\r
+  AsmCpuidEx (\r
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
+    &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+    );\r
+  @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF        0x02\r
+\r
+/**\r
+  CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
+    /// using minus-one notation.\r
+    ///\r
+    UINT32  CapacityLength:5;\r
+    UINT32  Reserved:27;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;\r
+\r
+/**\r
+  CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+  #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 15:0] Highest COS number supported for this ResID.\r
+    ///\r
+    UINT32  HighestCosNumber:16;\r
+    UINT32  Reserved:16;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;\r

 \r
 \r
 /**\r
 \r
 \r
 /**\r


@@ -2580,26 +2696,38 @@ typedef union {
   ///\r
   struct {\r
     ///\r
   ///\r
   struct {\r
     ///\r

-    /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
+    /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r

     /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
     ///\r
     UINT32  Cr3Filter:1;\r
     ///\r
     /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
     ///\r
     UINT32  Cr3Filter:1;\r
     ///\r

-    /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate\r
+    /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate\r

     /// Mode.\r
     ///\r
     UINT32  ConfigurablePsb:1;\r
     ///\r
     /// Mode.\r
     ///\r
     UINT32  ConfigurablePsb:1;\r
     ///\r

-    /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,\r
+    /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,\r

     /// and preservation of Intel PT MSRs across warm reset.\r
     ///\r
     UINT32  IpTraceStopFiltering:1;\r
     ///\r
     /// and preservation of Intel PT MSRs across warm reset.\r
     ///\r
     UINT32  IpTraceStopFiltering:1;\r
     ///\r

-    /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of\r
+    /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of\r

     /// COFI-based packets.\r
     ///\r
     UINT32  Mtc:1;\r
     /// COFI-based packets.\r
     ///\r
     UINT32  Mtc:1;\r

-    UINT32  Reserved:28;\r
+    ///\r
+    /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set\r
+    /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE\r
+    /// can generate packets.\r
+    ///\r
+    UINT32  PTWrite:1;\r
+    ///\r
+    /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set\r
+    /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet\r
+    /// generation.\r
+    ///\r
+    UINT32  PowerEventTrace:1;\r
+    UINT32  Reserved:26;\r

   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r


@@ -2629,16 +2757,16 @@ typedef union {
     ///\r
     UINT32  ToPA:1;\r
     ///\r
     ///\r
     UINT32  ToPA:1;\r
     ///\r

-    /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.\r
+    /// [Bit 2] If 1, indicates support of Single-Range Output scheme.\r

     ///\r
     UINT32  SingleRangeOutput:1;\r
     ///\r
     ///\r
     UINT32  SingleRangeOutput:1;\r
     ///\r

-    /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.\r
+    /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.\r

     ///\r
     UINT32  TraceTransportSubsystem:1;\r
     UINT32  Reserved:27;\r
     ///\r
     ///\r
     UINT32  TraceTransportSubsystem:1;\r
     UINT32  Reserved:27;\r
     ///\r

-    /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP\r
+    /// [Bit 31] If 1, generated packets which contain IP payloads have LIP\r

     /// values, which include the CS base component.\r
     ///\r
     UINT32  LIP:1;\r
     /// values, which include the CS base component.\r
     ///\r
     UINT32  LIP:1;\r


@@ -2738,13 +2866,14 @@ typedef union {
 \r
 \r
 /**\r
 \r
 \r
 /**\r

-  CPUID Time Stamp Counter Information\r
+  CPUID Time Stamp Counter and Nominal Core Crystal Clock Information\r

 \r
   @note\r
   If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r
   EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r
   crystal clock frequency.\r
 \r
   @note\r
   If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r
   EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r
   crystal clock frequency.\r

-    "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r
+  If ECX is 0, the nominal core crystal clock frequency is not enumerated.\r
+  "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r

   The core crystal clock may differ from the reference clock, bus clock, or core\r
   clock frequencies.\r
 \r
   The core crystal clock may differ from the reference clock, bus clock, or core\r
   clock frequencies.\r
 \r


@@ -2754,15 +2883,17 @@ typedef union {
                 TSC/"core crystal clock" ratio\r
   @retval  EBX  An unsigned integer which is the numerator of the\r
                 TSC/"core crystal clock" ratio.\r
                 TSC/"core crystal clock" ratio\r
   @retval  EBX  An unsigned integer which is the numerator of the\r
                 TSC/"core crystal clock" ratio.\r

-  @retval  ECX  Reserved.\r
+  @retval  ECX  An unsigned integer which is the nominal frequency\r
+                of the core crystal clock in Hz.\r

   @retval  EDX  Reserved.\r
 \r
   <b>Example usage</b>\r
   @code\r
   UINT32  Eax;\r
   UINT32  Ebx;\r
   @retval  EDX  Reserved.\r
 \r
   <b>Example usage</b>\r
   @code\r
   UINT32  Eax;\r
   UINT32  Ebx;\r

+  UINT32  Ecx;\r

 \r
 \r

-  AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);\r
+  AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r

   @endcode\r
 **/\r
 #define CPUID_TIME_STAMP_COUNTER                            0x15\r
   @endcode\r
 **/\r
 #define CPUID_TIME_STAMP_COUNTER                            0x15\r