UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler

Once the #PF handler has set the page to be 'present', there should
be a way to reset it to 'not-present'. 'TF' bit in EFLAGS can be used
for this purpose. 'TF' bit will be set in interrupted function context
so that it can be triggered once the cpu control returns back to the
instruction causing #PF and re-execute it.

This is an necessary step to implement non-stop mode for Heap Guard
and NULL Pointer Detection feature.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
index 45d647409172717fdec1e275addf4fbe7e5f68ce..6fcf5fb23fd465ccd6a8f989554dbb4864243767 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
@@ -383,6 +383,13 @@ ErrorCodeAndVectorOnStack:
     pop     dword [ebp - 4]\r
     mov     esp, ebp\r
     pop     ebp\r
+\r
+; Enable TF bit after page fault handler runs\r
+    cmp     dword [esp], 14       ; #PF?\r
+    jne     .5\r
+    bts     dword [esp + 16], 8   ; EFLAGS\r
+\r
+.5:\r
     add     esp, 8\r
     cmp     dword [esp - 16], 0   ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler\r
     jz      DoReturn\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
index 62bcedea1a29485ab68dae74c4fc104e9f7f82b4..7aac29c7e76d9527635f039fe079102b47a5ecac 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
@@ -355,10 +355,8 @@ o16 mov     [ecx + IA32_TSS._SS], ax
     movzx  ebx, word [ecx + IA32_TSS._CS]\r
     mov    [eax - 0x8], ebx                      ; create CS in old stack\r
     mov    ebx, dword [ecx + IA32_TSS.EFLAGS]\r
-    bts    ebx, 8\r
+    bts    ebx, 8                                ; Set TF\r
     mov    [eax - 0x4], ebx                      ; create eflags in old stack\r
-    mov    dword [ecx + IA32_TSS.EFLAGS], ebx    ; update eflags in old TSS\r
-    mov    eax, dword [ecx + IA32_TSS._ESP]      ; Get old stack pointer\r
     sub    eax, 0xc                              ; minus 12 byte\r
     mov    dword [ecx + IA32_TSS._ESP], eax      ; Set new stack pointer\r
 \r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
index 7b97810d10976a164688804a81519111a899e7f7..f842af23365d806ac9f920b7b4cbc030dd7fc425 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
@@ -336,6 +336,10 @@ HasErrorCode:
     pop     r15\r
 \r
     mov     rsp, rbp\r
+    cmp     qword [rbp + 8], 14 ; #PF?\r
+    jne     .1\r
+    bts     qword [rsp + 40], 8 ; RFLAGS.TF\r
+.1:\r
     pop     rbp\r
     add     rsp, 16\r
     cmp     qword [rsp - 32], 0  ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler\r