--- /dev/null
+/** @file\r
+ Entry point to the Standalone MM Foundation when initialized during the SEC\r
+ phase on ARM platforms\r
+\r
+Copyright (c) 2017 - 2018, ARM Ltd. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __STANDALONEMMCORE_ENTRY_POINT_H__\r
+#define __STANDALONEMMCORE_ENTRY_POINT_H__\r
+\r
+#include <Library/PeCoffLib.h>\r
+#include <Library/FvLib.h>\r
+\r
+#define CPU_INFO_FLAG_PRIMARY_CPU 0x00000001\r
+\r
+typedef struct {\r
+ UINT8 Type; /* type of the structure */\r
+ UINT8 Version; /* version of this structure */\r
+ UINT16 Size; /* size of this structure in bytes */\r
+ UINT32 Attr; /* attributes: unused bits SBZ */\r
+} EFI_PARAM_HEADER;\r
+\r
+typedef struct {\r
+ UINT64 Mpidr;\r
+ UINT32 LinearId;\r
+ UINT32 Flags;\r
+} EFI_SECURE_PARTITION_CPU_INFO;\r
+\r
+typedef struct {\r
+ EFI_PARAM_HEADER Header;\r
+ UINT64 SpMemBase;\r
+ UINT64 SpMemLimit;\r
+ UINT64 SpImageBase;\r
+ UINT64 SpStackBase;\r
+ UINT64 SpHeapBase;\r
+ UINT64 SpNsCommBufBase;\r
+ UINT64 SpSharedBufBase;\r
+ UINT64 SpImageSize;\r
+ UINT64 SpPcpuStackSize;\r
+ UINT64 SpHeapSize;\r
+ UINT64 SpNsCommBufSize;\r
+ UINT64 SpPcpuSharedBufSize;\r
+ UINT32 NumSpMemRegions;\r
+ UINT32 NumCpus;\r
+ EFI_SECURE_PARTITION_CPU_INFO *CpuInfo;\r
+} EFI_SECURE_PARTITION_BOOT_INFO;\r
+\r
+typedef\r
+EFI_STATUS\r
+(*PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT) (\r
+ IN UINTN EventId,\r
+ IN UINTN CpuNumber,\r
+ IN UINTN NsCommBufferAddr\r
+ );\r
+\r
+typedef struct {\r
+ PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *ArmTfCpuDriverEpPtr;\r
+} ARM_TF_CPU_DRIVER_EP_DESCRIPTOR;\r
+\r
+typedef RETURN_STATUS (*REGION_PERMISSION_UPDATE_FUNC) (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
+ );\r
+\r
+/**\r
+ Privileged firmware assigns RO & Executable attributes to all memory occupied\r
+ by the Boot Firmware Volume. This function sets the correct permissions of\r
+ sections in the Standalone MM Core module to be able to access RO and RW data\r
+ and make further progress in the boot process.\r
+\r
+ @param ImageContext Pointer to PE/COFF image context\r
+ @param SectionHeaderOffset Offset of PE/COFF image section header\r
+ @param NumberOfSections Number of Sections\r
+ @param TextUpdater Function to change code permissions\r
+ @param ReadOnlyUpdater Function to change RO permissions\r
+ @param ReadWriteUpdater Function to change RW permissions\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+UpdateMmFoundationPeCoffPermissions (\r
+ IN CONST PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,\r
+ IN UINT32 SectionHeaderOffset,\r
+ IN CONST UINT16 NumberOfSections,\r
+ IN REGION_PERMISSION_UPDATE_FUNC TextUpdater,\r
+ IN REGION_PERMISSION_UPDATE_FUNC ReadOnlyUpdater,\r
+ IN REGION_PERMISSION_UPDATE_FUNC ReadWriteUpdater\r
+ );\r
+\r
+\r
+/**\r
+ Privileged firmware assigns RO & Executable attributes to all memory occupied\r
+ by the Boot Firmware Volume. This function locates the section information of\r
+ the Standalone MM Core module to be able to change permissions of the\r
+ individual sections later in the boot process.\r
+\r
+ @param TeData Pointer to PE/COFF image data\r
+ @param ImageContext Pointer to PE/COFF image context\r
+ @param SectionHeaderOffset Offset of PE/COFF image section header\r
+ @param NumberOfSections Number of Sections\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetStandaloneMmCorePeCoffSections (\r
+ IN VOID *TeData,\r
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,\r
+ IN OUT UINT32 *SectionHeaderOffset,\r
+ IN OUT UINT16 *NumberOfSections\r
+ );\r
+\r
+\r
+/**\r
+ Privileged firmware assigns RO & Executable attributes to all memory occupied\r
+ by the Boot Firmware Volume. This function locates the Standalone MM Core\r
+ module PE/COFF image in the BFV and returns this information.\r
+\r
+ @param BfvAddress Base Address of Boot Firmware Volume\r
+ @param TeData Pointer to address for allocating memory for\r
+ PE/COFF image data\r
+ @param TeDataSize Pointer to size of PE/COFF image data\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LocateStandaloneMmCorePeCoffData (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BfvAddress,\r
+ IN OUT VOID **TeData,\r
+ IN OUT UINTN *TeDataSize\r
+ );\r
+\r
+\r
+/**\r
+ Use the boot information passed by privileged firmware to populate a HOB list\r
+ suitable for consumption by the MM Core and drivers.\r
+\r
+ @param CpuDriverEntryPoint Address of MM CPU driver entrypoint\r
+ @param PayloadBootInfo Boot information passed by privileged firmware\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+CreateHobListFromBootInfo (\r
+ IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,\r
+ IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo\r
+ );\r
+\r
+\r
+/**\r
+ The entry point of Standalone MM Foundation.\r
+\r
+ @param SharedBufAddress Pointer to the Buffer between SPM and SP.\r
+ @param cookie1.\r
+ @param cookie2.\r
+**/\r
+VOID\r
+EFIAPI\r
+_ModuleEntryPoint (\r
+ IN VOID *SharedBufAddress,\r
+ IN UINT64 SharedBufSize,\r
+ IN UINT64 cookie1,\r
+ IN UINT64 cookie2\r
+ );\r
+\r
+\r
+/**\r
+ Auto generated function that calls the library constructors for all of the module's dependent libraries.\r
+\r
+ This function must be called by _ModuleEntryPoint().\r
+ This function calls the set of library constructors for the set of library instances\r
+ that a module depends on. This includes library instances that a module depends on\r
+ directly and library instances that a module depends on indirectly through other\r
+ libraries. This function is auto generated by build tools and those build tools are\r
+ responsible for collecting the set of library instances, determine which ones have\r
+ constructors, and calling the library constructors in the proper order based upon\r
+ each of the library instances own dependencies.\r
+\r
+ @param ImageHandle The image handle of the DXE Core.\r
+ @param SystemTable A pointer to the EFI System Table.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ProcessLibraryConstructorList (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
+ );\r
+\r
+\r
+/**\r
+ Auto generated function that calls a set of module entry points.\r
+\r
+ This function must be called by _ModuleEntryPoint().\r
+ This function calls the set of module entry points.\r
+ This function is auto generated by build tools and those build tools are responsible\r
+ for collecting the module entry points and calling them in a specified order.\r
+\r
+ @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ProcessModuleEntryPointList (\r
+ IN VOID *HobStart\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Creates HOB during Standalone MM Foundation entry point\r
+ on ARM platforms.\r
+\r
+Copyright (c) 2017 - 2018, ARM Ltd. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php.\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiMm.h>\r
+\r
+#include <PiPei.h>\r
+#include <Guid/MmramMemoryReserve.h>\r
+#include <Guid/MpInformation.h>\r
+\r
+#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>\r
+#include <Library/ArmMmuLib.h>\r
+#include <Library/ArmSvcLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/SerialPortLib.h>\r
+\r
+#include <IndustryStandard/ArmStdSmc.h>\r
+\r
+extern EFI_HOB_HANDOFF_INFO_TABLE*\r
+HobConstructor (\r
+ IN VOID *EfiMemoryBegin,\r
+ IN UINTN EfiMemoryLength,\r
+ IN VOID *EfiFreeMemoryBottom,\r
+ IN VOID *EfiFreeMemoryTop\r
+ );\r
+\r
+// GUID to identify HOB with whereabouts of communication buffer with Normal\r
+// World\r
+extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;\r
+\r
+// GUID to identify HOB where the entry point of the CPU driver will be\r
+// populated to allow this entry point driver to invoke it upon receipt of an\r
+// event\r
+extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;\r
+\r
+/**\r
+ Use the boot information passed by privileged firmware to populate a HOB list\r
+ suitable for consumption by the MM Core and drivers.\r
+\r
+ @param PayloadBootInfo Boot information passed by privileged firmware\r
+\r
+**/\r
+VOID *\r
+CreateHobListFromBootInfo (\r
+ IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,\r
+ IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo\r
+)\r
+{\r
+ EFI_HOB_HANDOFF_INFO_TABLE *HobStart;\r
+ EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;\r
+ UINT32 Index;\r
+ UINT32 BufferSize;\r
+ UINT32 Flags;\r
+ EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;\r
+ EFI_MMRAM_DESCRIPTOR *MmramRanges;\r
+ EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;\r
+ MP_INFORMATION_HOB_DATA *MpInformationHobData;\r
+ EFI_PROCESSOR_INFORMATION *ProcInfoBuffer;\r
+ EFI_SECURE_PARTITION_CPU_INFO *CpuInfo;\r
+ ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;\r
+\r
+ // Create a hoblist with a PHIT and EOH\r
+ HobStart = HobConstructor (\r
+ (VOID *) PayloadBootInfo->SpMemBase,\r
+ (UINTN) PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase,\r
+ (VOID *) PayloadBootInfo->SpHeapBase,\r
+ (VOID *) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)\r
+ );\r
+\r
+ // Check that the Hoblist starts at the bottom of the Heap\r
+ ASSERT (HobStart == (VOID *) PayloadBootInfo->SpHeapBase);\r
+\r
+ // Build a Boot Firmware Volume HOB\r
+ BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);\r
+\r
+ // Build a resource descriptor Hob that describes the available physical\r
+ // memory range\r
+ Attributes = (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ );\r
+\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ Attributes,\r
+ (UINTN) PayloadBootInfo->SpMemBase,\r
+ PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase\r
+ );\r
+\r
+ // Find the size of the GUIDed HOB with MP information\r
+ BufferSize = sizeof (MP_INFORMATION_HOB_DATA);\r
+ BufferSize += sizeof (EFI_PROCESSOR_INFORMATION) * PayloadBootInfo->NumCpus;\r
+\r
+ // Create a Guided MP information HOB to enable the ARM TF CPU driver to\r
+ // perform per-cpu allocations.\r
+ MpInformationHobData = BuildGuidHob (&gMpInformationHobGuid, BufferSize);\r
+\r
+ // Populate the MP information HOB with the topology information passed by\r
+ // privileged firmware\r
+ MpInformationHobData->NumberOfProcessors = PayloadBootInfo->NumCpus;\r
+ MpInformationHobData->NumberOfEnabledProcessors = PayloadBootInfo->NumCpus;\r
+ ProcInfoBuffer = MpInformationHobData->ProcessorInfoBuffer;\r
+ CpuInfo = PayloadBootInfo->CpuInfo;\r
+\r
+ for (Index = 0; Index < PayloadBootInfo->NumCpus; Index++) {\r
+ ProcInfoBuffer[Index].ProcessorId = CpuInfo[Index].Mpidr;\r
+ ProcInfoBuffer[Index].Location.Package = GET_CLUSTER_ID(CpuInfo[Index].Mpidr);\r
+ ProcInfoBuffer[Index].Location.Core = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
+ ProcInfoBuffer[Index].Location.Thread = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
+\r
+ Flags = PROCESSOR_ENABLED_BIT | PROCESSOR_HEALTH_STATUS_BIT;\r
+ if (CpuInfo[Index].Flags & CPU_INFO_FLAG_PRIMARY_CPU) {\r
+ Flags |= PROCESSOR_AS_BSP_BIT;\r
+ }\r
+ ProcInfoBuffer[Index].StatusFlag = Flags;\r
+ }\r
+\r
+ // Create a Guided HOB to tell the ARM TF CPU driver the location and length\r
+ // of the communication buffer shared with the Normal world.\r
+ NsCommBufMmramRange = (EFI_MMRAM_DESCRIPTOR *) BuildGuidHob (\r
+ &gEfiStandaloneMmNonSecureBufferGuid,\r
+ sizeof (EFI_MMRAM_DESCRIPTOR)\r
+ );\r
+ NsCommBufMmramRange->PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
+ NsCommBufMmramRange->CpuStart = PayloadBootInfo->SpNsCommBufBase;\r
+ NsCommBufMmramRange->PhysicalSize = PayloadBootInfo->SpNsCommBufSize;\r
+ NsCommBufMmramRange->RegionState = EFI_CACHEABLE | EFI_ALLOCATED;\r
+\r
+ // Create a Guided HOB to enable the ARM TF CPU driver to share its entry\r
+ // point and populate it with the address of the shared buffer\r
+ CpuDriverEntryPointDesc = (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *) BuildGuidHob (\r
+ &gEfiArmTfCpuDriverEpDescriptorGuid,\r
+ sizeof (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR)\r
+ );\r
+\r
+ *CpuDriverEntryPoint = NULL;\r
+ CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr = CpuDriverEntryPoint;\r
+\r
+ // Find the size of the GUIDed HOB with SRAM ranges\r
+ BufferSize = sizeof (EFI_MMRAM_HOB_DESCRIPTOR_BLOCK);\r
+ BufferSize += PayloadBootInfo->NumSpMemRegions * sizeof (EFI_MMRAM_DESCRIPTOR);\r
+\r
+ // Create a GUIDed HOB with SRAM ranges\r
+ MmramRangesHob = BuildGuidHob (&gEfiMmPeiMmramMemoryReserveGuid, BufferSize);\r
+\r
+ // Fill up the number of MMRAM memory regions\r
+ MmramRangesHob->NumberOfMmReservedRegions = PayloadBootInfo->NumSpMemRegions;\r
+ // Fill up the MMRAM ranges\r
+ MmramRanges = &MmramRangesHob->Descriptor[0];\r
+\r
+ // Base and size of memory occupied by the Standalone MM image\r
+ MmramRanges[0].PhysicalStart = PayloadBootInfo->SpImageBase;\r
+ MmramRanges[0].CpuStart = PayloadBootInfo->SpImageBase;\r
+ MmramRanges[0].PhysicalSize = PayloadBootInfo->SpImageSize;\r
+ MmramRanges[0].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;\r
+\r
+ // Base and size of buffer shared with privileged Secure world software\r
+ MmramRanges[1].PhysicalStart = PayloadBootInfo->SpSharedBufBase;\r
+ MmramRanges[1].CpuStart = PayloadBootInfo->SpSharedBufBase;\r
+ MmramRanges[1].PhysicalSize = PayloadBootInfo->SpPcpuSharedBufSize * PayloadBootInfo->NumCpus;\r
+ MmramRanges[1].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;\r
+\r
+ // Base and size of buffer used for synchronous communication with Normal\r
+ // world software\r
+ MmramRanges[2].PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
+ MmramRanges[2].CpuStart = PayloadBootInfo->SpNsCommBufBase;\r
+ MmramRanges[2].PhysicalSize = PayloadBootInfo->SpNsCommBufSize;\r
+ MmramRanges[2].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;\r
+\r
+ // Base and size of memory allocated for stacks for all cpus\r
+ MmramRanges[3].PhysicalStart = PayloadBootInfo->SpStackBase;\r
+ MmramRanges[3].CpuStart = PayloadBootInfo->SpStackBase;\r
+ MmramRanges[3].PhysicalSize = PayloadBootInfo->SpPcpuStackSize * PayloadBootInfo->NumCpus;\r
+ MmramRanges[3].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;\r
+\r
+ // Base and size of heap memory shared by all cpus\r
+ MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) HobStart;\r
+ MmramRanges[4].CpuStart = (EFI_PHYSICAL_ADDRESS) HobStart;\r
+ MmramRanges[4].PhysicalSize = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) HobStart;\r
+ MmramRanges[4].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;\r
+\r
+ // Base and size of heap memory shared by all cpus\r
+ MmramRanges[5].PhysicalStart = HobStart->EfiFreeMemoryBottom;\r
+ MmramRanges[5].CpuStart = HobStart->EfiFreeMemoryBottom;\r
+ MmramRanges[5].PhysicalSize = HobStart->EfiFreeMemoryTop - HobStart->EfiFreeMemoryBottom;\r
+ MmramRanges[5].RegionState = EFI_CACHEABLE;\r
+\r
+ return HobStart;\r
+}\r
--- /dev/null
+/** @file\r
+ Locate, get and update PE/COFF permissions during Standalone MM\r
+ Foundation Entry point on ARM platforms.\r
+\r
+Copyright (c) 2017 - 2018, ARM Ltd. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php.\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiMm.h>\r
+\r
+#include <PiPei.h>\r
+#include <Guid/MmramMemoryReserve.h>\r
+#include <Guid/MpInformation.h>\r
+\r
+#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>\r
+#include <Library/ArmMmuLib.h>\r
+#include <Library/ArmSvcLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/SerialPortLib.h>\r
+\r
+#include <IndustryStandard/ArmStdSmc.h>\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+UpdateMmFoundationPeCoffPermissions (\r
+ IN CONST PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,\r
+ IN UINT32 SectionHeaderOffset,\r
+ IN CONST UINT16 NumberOfSections,\r
+ IN REGION_PERMISSION_UPDATE_FUNC TextUpdater,\r
+ IN REGION_PERMISSION_UPDATE_FUNC ReadOnlyUpdater,\r
+ IN REGION_PERMISSION_UPDATE_FUNC ReadWriteUpdater\r
+ )\r
+{\r
+ EFI_IMAGE_SECTION_HEADER SectionHeader;\r
+ RETURN_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS Base;\r
+ UINTN Size;\r
+ UINTN ReadSize;\r
+ UINTN Index;\r
+\r
+ ASSERT (ImageContext != NULL);\r
+\r
+ //\r
+ // Iterate over the sections\r
+ //\r
+ for (Index = 0; Index < NumberOfSections; Index++) {\r
+ //\r
+ // Read section header from file\r
+ //\r
+ Size = sizeof (EFI_IMAGE_SECTION_HEADER);\r
+ ReadSize = Size;\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ SectionHeaderOffset,\r
+ &Size,\r
+ &SectionHeader\r
+ );\r
+\r
+ if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
+ DEBUG ((DEBUG_ERROR,\r
+ "%a: ImageContext->ImageRead () failed (Status = %r)\n",\r
+ __FUNCTION__, Status));\r
+ return Status;\r
+ }\r
+\r
+ DEBUG ((DEBUG_INFO,\r
+ "%a: Section %d of image at 0x%lx has 0x%x permissions\n",\r
+ __FUNCTION__, Index, ImageContext->ImageAddress, SectionHeader.Characteristics));\r
+ DEBUG ((DEBUG_INFO,\r
+ "%a: Section %d of image at 0x%lx has %s name\n",\r
+ __FUNCTION__, Index, ImageContext->ImageAddress, SectionHeader.Name));\r
+ DEBUG ((DEBUG_INFO,\r
+ "%a: Section %d of image at 0x%lx has 0x%x address\n",\r
+ __FUNCTION__, Index, ImageContext->ImageAddress,\r
+ ImageContext->ImageAddress + SectionHeader.VirtualAddress));\r
+ DEBUG ((DEBUG_INFO,\r
+ "%a: Section %d of image at 0x%lx has 0x%x data\n",\r
+ __FUNCTION__, Index, ImageContext->ImageAddress, SectionHeader.PointerToRawData));\r
+\r
+ //\r
+ // If the section is marked as XN then remove the X attribute. Furthermore,\r
+ // if it is a writeable section then mark it appropriately as well.\r
+ //\r
+ if ((SectionHeader.Characteristics & EFI_IMAGE_SCN_MEM_EXECUTE) == 0) {\r
+ Base = ImageContext->ImageAddress + SectionHeader.VirtualAddress;\r
+\r
+ TextUpdater (Base, SectionHeader.Misc.VirtualSize);\r
+\r
+ if ((SectionHeader.Characteristics & EFI_IMAGE_SCN_MEM_WRITE) != 0) {\r
+ ReadWriteUpdater (Base, SectionHeader.Misc.VirtualSize);\r
+ DEBUG ((DEBUG_INFO,\r
+ "%a: Mapping section %d of image at 0x%lx with RW-XN permissions\n",\r
+ __FUNCTION__, Index, ImageContext->ImageAddress));\r
+ } else {\r
+ DEBUG ((DEBUG_INFO,\r
+ "%a: Mapping section %d of image at 0x%lx with RO-XN permissions\n",\r
+ __FUNCTION__, Index, ImageContext->ImageAddress));\r
+ }\r
+ } else {\r
+ DEBUG ((DEBUG_INFO,\r
+ "%a: Ignoring section %d of image at 0x%lx with 0x%x permissions\n",\r
+ __FUNCTION__, Index, ImageContext->ImageAddress, SectionHeader.Characteristics));\r
+ }\r
+ SectionHeaderOffset += sizeof (EFI_IMAGE_SECTION_HEADER);\r
+ }\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+LocateStandaloneMmCorePeCoffData (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BfvAddress,\r
+ IN OUT VOID **TeData,\r
+ IN OUT UINTN *TeDataSize\r
+ )\r
+{\r
+ EFI_FFS_FILE_HEADER *FileHeader = NULL;\r
+ EFI_STATUS Status;\r
+\r
+ Status = FfsFindNextFile (\r
+ EFI_FV_FILETYPE_SECURITY_CORE,\r
+ BfvAddress,\r
+ &FileHeader\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Unable to locate Standalone MM FFS file - 0x%x\n",\r
+ Status));\r
+ return Status;\r
+ }\r
+\r
+ Status = FfsFindSectionData (EFI_SECTION_PE32, FileHeader, TeData, TeDataSize);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Unable to locate Standalone MM Section data - 0x%x\n",\r
+ Status));\r
+ return Status;\r
+ }\r
+\r
+ DEBUG ((DEBUG_INFO, "Found Standalone MM PE data - 0x%x\n", *TeData));\r
+ return Status;\r
+}\r
+\r
+STATIC\r
+EFI_STATUS\r
+GetPeCoffSectionInformation (\r
+ IN CONST PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,\r
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *TmpContext,\r
+ IN OUT UINT32 *SectionHeaderOffset,\r
+ IN OUT UINT16 *NumberOfSections\r
+ )\r
+{\r
+ RETURN_STATUS Status;\r
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
+ EFI_IMAGE_OPTIONAL_HEADER_UNION HdrData;\r
+ UINTN Size;\r
+ UINTN ReadSize;\r
+\r
+ ASSERT (ImageContext != NULL);\r
+ ASSERT (TmpContext != NULL);\r
+ ASSERT (SectionHeaderOffset != NULL);\r
+ ASSERT (NumberOfSections != NULL);\r
+\r
+ //\r
+ // We need to copy ImageContext since PeCoffLoaderGetImageInfo ()\r
+ // will mangle the ImageAddress field\r
+ //\r
+ CopyMem (TmpContext, ImageContext, sizeof (*TmpContext));\r
+\r
+ if (TmpContext->PeCoffHeaderOffset == 0) {\r
+ Status = PeCoffLoaderGetImageInfo (TmpContext);\r
+ if (RETURN_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR,\r
+ "%a: PeCoffLoaderGetImageInfo () failed (Status = %r)\n",\r
+ __FUNCTION__, Status));\r
+ return Status;\r
+ }\r
+ }\r
+\r
+ if (TmpContext->IsTeImage &&\r
+ TmpContext->ImageAddress == ImageContext->ImageAddress) {\r
+ DEBUG ((DEBUG_INFO, "%a: ignoring XIP TE image at 0x%lx\n", __FUNCTION__,\r
+ ImageContext->ImageAddress));\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
+\r
+ if (TmpContext->SectionAlignment < EFI_PAGE_SIZE) {\r
+ //\r
+ // The sections need to be at least 4 KB aligned, since that is the\r
+ // granularity at which we can tighten permissions.\r
+ //\r
+ if (!TmpContext->IsTeImage) {\r
+ DEBUG ((DEBUG_WARN,\r
+ "%a: non-TE Image at 0x%lx has SectionAlignment < 4 KB (%lu)\n",\r
+ __FUNCTION__, ImageContext->ImageAddress, TmpContext->SectionAlignment));\r
+ }\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Read the PE/COFF Header. For PE32 (32-bit) this will read in too much\r
+ // data, but that should not hurt anything. Hdr.Pe32->OptionalHeader.Magic\r
+ // determines if this is a PE32 or PE32+ image. The magic is in the same\r
+ // location in both images.\r
+ //\r
+ Hdr.Union = &HdrData;\r
+ Size = sizeof (EFI_IMAGE_OPTIONAL_HEADER_UNION);\r
+ ReadSize = Size;\r
+ Status = TmpContext->ImageRead (\r
+ TmpContext->Handle,\r
+ TmpContext->PeCoffHeaderOffset,\r
+ &Size,\r
+ Hdr.Pe32\r
+ );\r
+\r
+ if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
+ DEBUG ((DEBUG_ERROR,\r
+ "%a: TmpContext->ImageRead () failed (Status = %r)\n",\r
+ __FUNCTION__, Status));\r
+ return Status;\r
+ }\r
+\r
+ ASSERT (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE);\r
+\r
+ *SectionHeaderOffset = TmpContext->PeCoffHeaderOffset + sizeof (UINT32) +\r
+ sizeof (EFI_IMAGE_FILE_HEADER);\r
+ *NumberOfSections = Hdr.Pe32->FileHeader.NumberOfSections;\r
+\r
+ switch (Hdr.Pe32->OptionalHeader.Magic) {\r
+ case EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC:\r
+ *SectionHeaderOffset += Hdr.Pe32->FileHeader.SizeOfOptionalHeader;\r
+ break;\r
+ case EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC:\r
+ *SectionHeaderOffset += Hdr.Pe32Plus->FileHeader.SizeOfOptionalHeader;\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ }\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetStandaloneMmCorePeCoffSections (\r
+ IN VOID *TeData,\r
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,\r
+ IN OUT UINT32 *SectionHeaderOffset,\r
+ IN OUT UINT16 *NumberOfSections\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ PE_COFF_LOADER_IMAGE_CONTEXT TmpContext;\r
+\r
+ // Initialize the Image Context\r
+ ZeroMem (ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));\r
+ ImageContext->Handle = TeData;\r
+ ImageContext->ImageRead = PeCoffLoaderImageReadFromMemory;\r
+\r
+ DEBUG ((DEBUG_INFO, "Found Standalone MM PE data - 0x%x\n", TeData));\r
+\r
+ Status = PeCoffLoaderGetImageInfo (ImageContext);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Unable to locate Standalone MM Core PE-COFF Image information - 0x%x\n", Status));\r
+ return Status;\r
+ }\r
+\r
+ Status = GetPeCoffSectionInformation (ImageContext, &TmpContext, SectionHeaderOffset, NumberOfSections);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Unable to locate Standalone MM Core PE-COFF Section information - 0x%x\n", Status));\r
+ return Status;\r
+ }\r
+\r
+ DEBUG ((DEBUG_INFO, "Standalone MM Core PE-COFF SectionHeaderOffset - 0x%x, NumberOfSections - %d\n",\r
+ *SectionHeaderOffset, *NumberOfSections));\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+ Entry point to the Standalone MM Foundation when initialized during the SEC\r
+ phase on ARM platforms\r
+\r
+Copyright (c) 2017 - 2018, ARM Ltd. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php.\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiMm.h>\r
+\r
+#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>\r
+\r
+#include <PiPei.h>\r
+#include <Guid/MmramMemoryReserve.h>\r
+#include <Guid/MpInformation.h>\r
+\r
+#include <Library/ArmMmuLib.h>\r
+#include <Library/ArmSvcLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/SerialPortLib.h>\r
+\r
+#include <IndustryStandard/ArmStdSmc.h>\r
+#include <IndustryStandard/ArmMmSvc.h>\r
+\r
+#define SPM_MAJOR_VER_MASK 0xFFFF0000\r
+#define SPM_MINOR_VER_MASK 0x0000FFFF\r
+#define SPM_MAJOR_VER_SHIFT 16\r
+\r
+CONST UINT32 SPM_MAJOR_VER = 0;\r
+CONST UINT32 SPM_MINOR_VER = 1;\r
+\r
+CONST UINT8 BOOT_PAYLOAD_VERSION = 1;\r
+\r
+PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT CpuDriverEntryPoint = NULL;\r
+\r
+/**\r
+ Retrieve a pointer to and print the boot information passed by privileged\r
+ secure firmware\r
+\r
+ @param SharedBufAddress The pointer memory shared with privileged firmware\r
+\r
+**/\r
+EFI_SECURE_PARTITION_BOOT_INFO *\r
+GetAndPrintBootinformation (\r
+ IN VOID *SharedBufAddress\r
+)\r
+{\r
+ EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo;\r
+ EFI_SECURE_PARTITION_CPU_INFO *PayloadCpuInfo;\r
+ UINTN Index;\r
+\r
+ PayloadBootInfo = (EFI_SECURE_PARTITION_BOOT_INFO *) SharedBufAddress;\r
+\r
+ if (PayloadBootInfo == NULL) {\r
+ DEBUG ((DEBUG_ERROR, "PayloadBootInfo NULL\n"));\r
+ return NULL;\r
+ }\r
+\r
+ if (PayloadBootInfo->Header.Version != BOOT_PAYLOAD_VERSION) {\r
+ DEBUG ((DEBUG_ERROR, "Boot Information Version Mismatch. Current=0x%x, Expected=0x%x.\n",\r
+ PayloadBootInfo->Header.Version, BOOT_PAYLOAD_VERSION));\r
+ return NULL;\r
+ }\r
+\r
+ DEBUG ((DEBUG_INFO, "NumSpMemRegions - 0x%x\n", PayloadBootInfo->NumSpMemRegions));\r
+ DEBUG ((DEBUG_INFO, "SpMemBase - 0x%lx\n", PayloadBootInfo->SpMemBase));\r
+ DEBUG ((DEBUG_INFO, "SpMemLimit - 0x%lx\n", PayloadBootInfo->SpMemLimit));\r
+ DEBUG ((DEBUG_INFO, "SpImageBase - 0x%lx\n", PayloadBootInfo->SpImageBase));\r
+ DEBUG ((DEBUG_INFO, "SpStackBase - 0x%lx\n", PayloadBootInfo->SpStackBase));\r
+ DEBUG ((DEBUG_INFO, "SpHeapBase - 0x%lx\n", PayloadBootInfo->SpHeapBase));\r
+ DEBUG ((DEBUG_INFO, "SpNsCommBufBase - 0x%lx\n", PayloadBootInfo->SpNsCommBufBase));\r
+ DEBUG ((DEBUG_INFO, "SpSharedBufBase - 0x%lx\n", PayloadBootInfo->SpSharedBufBase));\r
+\r
+ DEBUG ((DEBUG_INFO, "SpImageSize - 0x%x\n", PayloadBootInfo->SpImageSize));\r
+ DEBUG ((DEBUG_INFO, "SpPcpuStackSize - 0x%x\n", PayloadBootInfo->SpPcpuStackSize));\r
+ DEBUG ((DEBUG_INFO, "SpHeapSize - 0x%x\n", PayloadBootInfo->SpHeapSize));\r
+ DEBUG ((DEBUG_INFO, "SpNsCommBufSize - 0x%x\n", PayloadBootInfo->SpNsCommBufSize));\r
+ DEBUG ((DEBUG_INFO, "SpPcpuSharedBufSize - 0x%x\n", PayloadBootInfo->SpPcpuSharedBufSize));\r
+\r
+ DEBUG ((DEBUG_INFO, "NumCpus - 0x%x\n", PayloadBootInfo->NumCpus));\r
+ DEBUG ((DEBUG_INFO, "CpuInfo - 0x%p\n", PayloadBootInfo->CpuInfo));\r
+\r
+ PayloadCpuInfo = (EFI_SECURE_PARTITION_CPU_INFO *) PayloadBootInfo->CpuInfo;\r
+\r
+ if (PayloadCpuInfo == NULL) {\r
+ DEBUG ((DEBUG_ERROR, "PayloadCpuInfo NULL\n"));\r
+ return NULL;\r
+ }\r
+\r
+ for (Index = 0; Index < PayloadBootInfo->NumCpus; Index++) {\r
+ DEBUG ((DEBUG_INFO, "Mpidr - 0x%lx\n", PayloadCpuInfo[Index].Mpidr));\r
+ DEBUG ((DEBUG_INFO, "LinearId - 0x%x\n", PayloadCpuInfo[Index].LinearId));\r
+ DEBUG ((DEBUG_INFO, "Flags - 0x%x\n", PayloadCpuInfo[Index].Flags));\r
+ }\r
+\r
+ return PayloadBootInfo;\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+DelegatedEventLoop (\r
+ IN ARM_SVC_ARGS *EventCompleteSvcArgs\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN SvcStatus;\r
+\r
+ while (TRUE) {\r
+ ArmCallSvc (EventCompleteSvcArgs);\r
+\r
+ DEBUG ((DEBUG_INFO, "Received delegated event\n"));\r
+ DEBUG ((DEBUG_INFO, "X0 : 0x%x\n", (UINT32) EventCompleteSvcArgs->Arg0));\r
+ DEBUG ((DEBUG_INFO, "X1 : 0x%x\n", (UINT32) EventCompleteSvcArgs->Arg1));\r
+ DEBUG ((DEBUG_INFO, "X2 : 0x%x\n", (UINT32) EventCompleteSvcArgs->Arg2));\r
+ DEBUG ((DEBUG_INFO, "X3 : 0x%x\n", (UINT32) EventCompleteSvcArgs->Arg3));\r
+\r
+ Status = CpuDriverEntryPoint (\r
+ EventCompleteSvcArgs->Arg0,\r
+ EventCompleteSvcArgs->Arg3,\r
+ EventCompleteSvcArgs->Arg1\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Failed delegated event 0x%x, Status 0x%x\n",\r
+ EventCompleteSvcArgs->Arg0, Status));\r
+ }\r
+\r
+ switch (Status) {\r
+ case EFI_SUCCESS:\r
+ SvcStatus = ARM_SVC_SPM_RET_SUCCESS;\r
+ break;\r
+ case EFI_INVALID_PARAMETER:\r
+ SvcStatus = ARM_SVC_SPM_RET_INVALID_PARAMS;\r
+ break;\r
+ case EFI_ACCESS_DENIED:\r
+ SvcStatus = ARM_SVC_SPM_RET_DENIED;\r
+ break;\r
+ case EFI_OUT_OF_RESOURCES:\r
+ SvcStatus = ARM_SVC_SPM_RET_NO_MEMORY;\r
+ break;\r
+ case EFI_UNSUPPORTED:\r
+ SvcStatus = ARM_SVC_SPM_RET_NOT_SUPPORTED;\r
+ break;\r
+ default:\r
+ SvcStatus = ARM_SVC_SPM_RET_NOT_SUPPORTED;\r
+ break;\r
+ }\r
+\r
+ EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;\r
+ EventCompleteSvcArgs->Arg1 = SvcStatus;\r
+ }\r
+}\r
+\r
+STATIC\r
+EFI_STATUS\r
+GetSpmVersion (VOID)\r
+{\r
+ EFI_STATUS Status;\r
+ UINT16 SpmMajorVersion;\r
+ UINT16 SpmMinorVersion;\r
+ UINT32 SpmVersion;\r
+ ARM_SVC_ARGS SpmVersionArgs;\r
+\r
+ SpmVersionArgs.Arg0 = ARM_SVC_ID_SPM_VERSION_AARCH32;\r
+\r
+ ArmCallSvc (&SpmVersionArgs);\r
+\r
+ SpmVersion = SpmVersionArgs.Arg0;\r
+\r
+ SpmMajorVersion = ((SpmVersion & SPM_MAJOR_VER_MASK) >> SPM_MAJOR_VER_SHIFT);\r
+ SpmMinorVersion = ((SpmVersion & SPM_MINOR_VER_MASK) >> 0);\r
+\r
+ // Different major revision values indicate possibly incompatible functions.\r
+ // For two revisions, A and B, for which the major revision values are\r
+ // identical, if the minor revision value of revision B is greater than\r
+ // the minor revision value of revision A, then every function in\r
+ // revision A must work in a compatible way with revision B.\r
+ // However, it is possible for revision B to have a higher\r
+ // function count than revision A.\r
+ if ((SpmMajorVersion == SPM_MAJOR_VER) &&\r
+ (SpmMinorVersion >= SPM_MINOR_VER))\r
+ {\r
+ DEBUG ((DEBUG_INFO, "SPM Version: Major=0x%x, Minor=0x%x\n",\r
+ SpmMajorVersion, SpmMinorVersion));\r
+ Status = EFI_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ DEBUG ((DEBUG_INFO, "Incompatible SPM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n",\r
+ SpmMajorVersion, SpmMinorVersion, SPM_MAJOR_VER, SPM_MINOR_VER));\r
+ Status = EFI_UNSUPPORTED;\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ The entry point of Standalone MM Foundation.\r
+\r
+ @param SharedBufAddress Pointer to the Buffer between SPM and SP.\r
+ @param cookie1.\r
+ @param cookie2.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+_ModuleEntryPoint (\r
+ IN VOID *SharedBufAddress,\r
+ IN UINT64 SharedBufSize,\r
+ IN UINT64 cookie1,\r
+ IN UINT64 cookie2\r
+ )\r
+{\r
+ PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
+ EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo;\r
+ ARM_SVC_ARGS InitMmFoundationSvcArgs = {0};\r
+ EFI_STATUS Status;\r
+ UINT32 SectionHeaderOffset;\r
+ UINT16 NumberOfSections;\r
+ VOID *HobStart;\r
+ VOID *TeData;\r
+ UINTN TeDataSize;\r
+\r
+ Status = SerialPortInitialize ();\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // Get Secure Partition Manager Version Information\r
+ Status = GetSpmVersion ();\r
+ if (EFI_ERROR (Status)) {\r
+ goto finish;\r
+ }\r
+\r
+ PayloadBootInfo = GetAndPrintBootinformation (SharedBufAddress);\r
+ if (PayloadBootInfo == NULL) {\r
+ Status = EFI_UNSUPPORTED;\r
+ goto finish;\r
+ }\r
+\r
+ // Locate PE/COFF File information for the Standalone MM core module\r
+ Status = LocateStandaloneMmCorePeCoffData (\r
+ (EFI_FIRMWARE_VOLUME_HEADER *) PayloadBootInfo->SpImageBase,\r
+ &TeData,\r
+ &TeDataSize\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto finish;\r
+ }\r
+\r
+ // Obtain the PE/COFF Section information for the Standalone MM core module\r
+ Status = GetStandaloneMmCorePeCoffSections (\r
+ TeData,\r
+ &ImageContext,\r
+ &SectionHeaderOffset,\r
+ &NumberOfSections\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto finish;\r
+ }\r
+\r
+ // Update the memory access permissions of individual sections in the\r
+ // Standalone MM core module\r
+ Status = UpdateMmFoundationPeCoffPermissions (\r
+ &ImageContext,\r
+ SectionHeaderOffset,\r
+ NumberOfSections,\r
+ ArmSetMemoryRegionNoExec,\r
+ ArmSetMemoryRegionReadOnly,\r
+ ArmClearMemoryRegionReadOnly\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto finish;\r
+ }\r
+\r
+ //\r
+ // Create Hoblist based upon boot information passed by privileged software\r
+ //\r
+ HobStart = CreateHobListFromBootInfo (&CpuDriverEntryPoint, PayloadBootInfo);\r
+\r
+ //\r
+ // Call the MM Core entry point\r
+ //\r
+ ProcessModuleEntryPointList (HobStart);\r
+\r
+ ASSERT_EFI_ERROR (CpuDriverEntryPoint);\r
+ DEBUG ((DEBUG_INFO, "Shared Cpu Driver EP 0x%lx\n", (UINT64) CpuDriverEntryPoint));\r
+\r
+finish:\r
+ InitMmFoundationSvcArgs.Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;\r
+ InitMmFoundationSvcArgs.Arg1 = Status;\r
+ DelegatedEventLoop (&InitMmFoundationSvcArgs);\r
+ ASSERT_EFI_ERROR (0);\r
+}\r
--- /dev/null
+## @file\r
+# Module entry point library for DXE core.\r
+#\r
+# Copyright (c) 2017 - 2018, ARM Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x0001001A\r
+ BASE_NAME = StandaloneMmCoreEntryPoint\r
+ FILE_GUID = C97AC593-109A-4C63-905C-675FDE2689E8\r
+ MODULE_TYPE = MM_CORE_STANDALONE\r
+ VERSION_STRING = 1.0\r
+ PI_SPECIFICATION_VERSION = 0x00010032\r
+ LIBRARY_CLASS = StandaloneMmCoreEntryPoint|MM_CORE_STANDALONE\r
+\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+#\r
+\r
+[Sources.AARCH64]\r
+ AArch64/StandaloneMmCoreEntryPoint.c\r
+ AArch64/SetPermissions.c\r
+ AArch64/CreateHobList.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ StandaloneMmPkg/StandaloneMmPkg.dec\r
+\r
+[Packages.AARCH64]\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ DebugLib\r
+\r
+[LibraryClasses.AARCH64]\r
+ ArmMmuLib\r
+ ArmSvcLib\r
+\r
+[Guids]\r
+ gMpInformationHobGuid\r
+ gEfiMmPeiMmramMemoryReserveGuid\r
+ gEfiStandaloneMmNonSecureBufferGuid\r
+ gEfiArmTfCpuDriverEpDescriptorGuid\r
projects / mirror_edk2.git / commitdiff