IntelFsp2Pkg: Added changes to enable FPDT performance measurements

IntelFsp2Pkg:
1.Defined performance measure mask to mask the Perf id (Bits 63:56) of the
Perf Data from FSP Global data.
2.Replaced the hard coded perf ids to use the standard defines
from FspStatuscode.h
3.Add the PerfData form Fsp Global data ( for TempRaminit entry,
TempramInit exit, memoryinit entry) to FPDT entries

IntelFsp2WrapperPkg:
  Moved the code to add the FSP FPDT records and wrapper FPDT records
from ReadytoBoot event to EndofFirmware event

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/FspGlobalData.h
index 8ac3199bab9147542a7545f326c10debb770e272..7de26606a7fbca49e5d203ba057bbb260d2cd4ce 100644 (file)
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -38,6 +38,7 @@ typedef struct  {
 \r
 #define FSP_GLOBAL_DATA_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'D')\r
 #define FSP_PERFORMANCE_DATA_SIGNATURE  SIGNATURE_32 ('P', 'E', 'R', 'F')\r
+#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF\r
 \r
 typedef struct  {\r
    UINT32             Signature;\r

diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf b/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
index d04689ef88894ce1de58d1d83c8d22c71cd9bc62..907482daed15564e86fdb6d83716eb5c8b60d213 100644 (file)
--- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
+++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
@@ -44,6 +44,10 @@
 [Guids]\r
   gFspPerformanceDataGuid                                   ## CONSUMES ## GUID\r
   gFspEventEndOfFirmwareGuid                                ## PRODUCES ## GUID\r
+  gEfiEventReadyToBootGuid                                  ## CONSUMES ## Event\r
+\r
+[Protocols]\r
+  gEfiPciEnumerationCompleteProtocolGuid                    ## CONSUMES\r
 \r
 [FixedPcd]\r
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry        ## CONSUMES\r

diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
index 66b6cdb87881d889ebafb9d41ad7e68b2ac4080c..755e84f20cc05b69c4ea7d58b325758252730ed0 100644 (file)
--- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
+++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
@@ -121,15 +121,12 @@ FspSiliconInitDone (
   //\r
   SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT);\r
   DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - End\n"));\r
-\r
-  PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, 0x907F);\r
-\r
+  PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
   REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
   SetFspApiReturnStatus (EFI_SUCCESS);\r
 \r
   Pei2LoaderSwitchStack();\r
 \r
-  PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, 0x6000);\r
 }\r
 \r
 /**\r
@@ -143,6 +140,7 @@ FspMemoryInitDone (
   IN OUT VOID   **HobListPtr\r
   )\r
 {\r
+  FSP_GLOBAL_DATA   *FspData;\r
   //\r
   // Calling use FspMemoryInit API\r
   // Update HOB and return the control directly\r
@@ -155,8 +153,13 @@ FspMemoryInitDone (
   // This is the end of the FspMemoryInit API\r
   // Give control back to the boot loader\r
   //\r
-  SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT);\r
   DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspMemoryInitApi() - End\n"));\r
+  SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT);\r
+  FspData = GetFspGlobalDataPointer ();\r
+  PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[0] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE| FSP_STATUS_CODE_API_ENTRY);\r
+  PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[1] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
+  PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[2] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+  PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
   REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
   SetFspApiReturnStatus (EFI_SUCCESS);\r
   Pei2LoaderSwitchStack ();\r
@@ -166,14 +169,16 @@ FspMemoryInitDone (
   //\r
   if (GetFspApiCallingIndex () == TempRamExitApiIndex) {\r
     SetPhaseStatusCode (FSP_STATUS_CODE_TEMP_RAM_EXIT);\r
-    REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
     SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY);\r
+    PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+    REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
     DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - Begin\n"));\r
   } else {\r
-    SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);\r
-    DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - Begin\n"));\r
     SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT);\r
+    SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);\r
+    PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
     REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+    DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - Begin\n"));\r
   }\r
 }\r
 \r
@@ -192,16 +197,18 @@ FspTempRamExitDone (
   // This is the end of the TempRamExit API\r
   // Give control back to the boot loader\r
   //\r
-  SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT);\r
   DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - End\n"));\r
+  SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT);\r
+  PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
   REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
   SetFspApiReturnStatus (EFI_SUCCESS);\r
   Pei2LoaderSwitchStack ();\r
 \r
   SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT);\r
   SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);\r
-  DEBUG ((DEBUG_INFO | DEBUG_INIT, "SiliconInitApi() - Begin\n"));\r
+  PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
   REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "SiliconInitApi() - Begin\n"));\r
 }\r
 \r
 /**\r
@@ -229,12 +236,15 @@ FspWaitForNotify (
 \r
     if (NotificationCount == 0) {\r
       SetPhaseStatusCode (FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION);\r
+      PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
     } else if (NotificationCount == 1) {\r
       SetPhaseStatusCode (FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION);\r
+      PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
     } else if (NotificationCount == 2) {\r
       SetPhaseStatusCode (FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION);\r
+      PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
     }\r
 \r
@@ -262,10 +272,13 @@ FspWaitForNotify (
     SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT + Count);\r
 \r
     if ((NotificationCount - 1) == 0) {\r
+      PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
     } else if ((NotificationCount - 1) == 1) {\r
+      PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
     } else if ((NotificationCount - 1) == 2) {\r
+      PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
     }\r
     Pei2LoaderSwitchStack();\r

diff --git a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c
index 0797f44a6835d5031de5d931b7abc8667c3786bb..a69263278db1c7511d9f3661312d5b2bf6ab241d 100644 (file)
--- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c
+++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c
@@ -25,6 +25,7 @@
 #include <Library/FspWrapperPlatformLib.h>\r
 #include <Library/PerformanceLib.h>\r
 #include <Library/HobLib.h>\r
+#include <FspStatusCode.h>\r
 \r
 typedef\r
 EFI_STATUS\r
@@ -91,9 +92,9 @@ OnPciEnumerationComplete (
   }\r
 \r
   NotifyPhaseParams.Phase = EnumInitPhaseAfterPciEnumeration;\r
-  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x6000);\r
+  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
   Status = CallFspNotifyPhase (&NotifyPhaseParams);\r
-  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x607F);\r
+  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
 \r
   //\r
   // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status\r
@@ -130,16 +131,13 @@ OnReadyToBoot (
 {\r
   NOTIFY_PHASE_PARAMS               NotifyPhaseParams;\r
   EFI_STATUS                        Status;\r
-  ADD_PERFORMANCE_RECORD_PROTOCOL   *AddPerfRecordInterface;\r
-  EFI_PEI_HOB_POINTERS              Hob;\r
-  VOID                              **FspHobListPtr;\r
 \r
   gBS->CloseEvent (Event);\r
 \r
   NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;\r
-  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x4000);\r
+  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
   Status = CallFspNotifyPhase (&NotifyPhaseParams);\r
-  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x407F);\r
+  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
 \r
   //\r
   // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status\r
@@ -154,23 +152,6 @@ OnReadyToBoot (
   } else {\r
     DEBUG((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot Success.\n"));\r
   }\r
-\r
-  Status = gBS->LocateProtocol (\r
-                  &gAddPerfRecordProtocolGuid,\r
-                  NULL,\r
-                  (VOID**) &AddPerfRecordInterface\r
-                  );\r
-  if (EFI_ERROR (Status)) {\r
-    DEBUG((DEBUG_INFO, "gAddPerfRecordProtocolGuid - Locate protocol failed\n"));\r
-    return;\r
-  } else {\r
-    Hob.Raw = GetHobList ();\r
-    if (Hob.Raw != NULL) {\r
-      Hob.Raw = GetNextGuidHob (&gFspHobGuid, Hob.Raw);\r
-      FspHobListPtr = GET_GUID_HOB_DATA(Hob.Raw);\r
-      AddPerfRecordInterface->AddPerformanceRecords((VOID *)(UINTN)(((UINT32)(UINTN)*FspHobListPtr) & 0xFFFFFFFF));\r
-    }\r
-  }\r
 }\r
 \r
 /**\r
@@ -189,15 +170,18 @@ OnEndOfFirmware (
   IN VOID       *Context\r
   )\r
 {\r
-  NOTIFY_PHASE_PARAMS NotifyPhaseParams;\r
-  EFI_STATUS          Status;\r
+  NOTIFY_PHASE_PARAMS               NotifyPhaseParams;\r
+  EFI_STATUS                        Status;\r
+  ADD_PERFORMANCE_RECORD_PROTOCOL   *AddPerfRecordInterface;\r
+  EFI_PEI_HOB_POINTERS              Hob;\r
+  VOID                              **FspHobListPtr;\r
 \r
   gBS->CloseEvent (Event);\r
 \r
   NotifyPhaseParams.Phase = EnumInitPhaseEndOfFirmware;\r
-  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x2000);\r
+  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
   Status = CallFspNotifyPhase (&NotifyPhaseParams);\r
-  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x207F);\r
+  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
 \r
   //\r
   // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status\r
@@ -212,6 +196,21 @@ OnEndOfFirmware (
   } else {\r
     DEBUG((DEBUG_INFO, "FSP NotifyPhase EndOfFirmware Success.\n"));\r
   }\r
+  Status = gBS->LocateProtocol (\r
+                  &gAddPerfRecordProtocolGuid,\r
+                  NULL,\r
+                  (VOID**) &AddPerfRecordInterface\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    DEBUG((DEBUG_INFO, "gAddPerfRecordProtocolGuid - Locate protocol failed\n"));\r
+    return;\r
+  } else {\r
+    Hob.Raw = GetFirstGuidHob (&gFspHobGuid);\r
+    if (Hob.Raw != NULL) {\r
+      FspHobListPtr = GET_GUID_HOB_DATA (Hob.Raw);\r
+      AddPerfRecordInterface->AddPerformanceRecords ((VOID *)(UINTN)(((UINT32)(UINTN)*FspHobListPtr) & 0xFFFFFFFF));\r
+    }\r
+  }\r
 }\r
 \r
 /**\r

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 0f6a7bdf40555bb7c5f5acb62dc8eb27fc5b4422..f1d1cd642181dbefee8a1f1f4593c7191eeaf6ba 100644 (file)
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -38,6 +38,7 @@
 #include <Ppi/SecPlatformInformation.h>\r
 #include <Library/FspWrapperApiTestLib.h>\r
 #include <FspEas.h>\r
+#include <FspStatusCode.h>\r
 \r
 extern EFI_GUID gFspHobGuid;\r
 \r
@@ -89,8 +90,8 @@ PeiFspMemoryInit (
   TimeStampCounterStart = AsmReadTsc ();\r
   Status = CallFspMemoryInit (FspmUpdDataPtr, &FspHobListPtr);\r
   // Create hobs after memory initialization and not in temp RAM. Hence passing the recorded timestamp here\r
-  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, TimeStampCounterStart, 0xD000);\r
-  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0xD07F);\r
+  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, TimeStampCounterStart, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
   DEBUG ((DEBUG_INFO, "Total time spent executing FspMemoryInitApi: %d millisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCounterStart), 1000000)));\r
 \r
   //\r

diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 1701b63cffc189e0ac5aca23d84e5307dd849661..ddc19c7e8f69ceb760782ebebd12bcc7ed8c10f8 100644 (file)
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -38,6 +38,7 @@
 #include <Ppi/SecPlatformInformation.h>\r
 #include <Library/FspWrapperApiTestLib.h>\r
 #include <FspEas.h>\r
+#include <FspStatusCode.h>\r
 \r
 extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc;\r
 extern EFI_GUID                  gFspHobGuid;\r
@@ -253,9 +254,9 @@ PeiMemoryDiscoveredNotify (
   UpdateFspsUpdData ((VOID *)FspsUpdDataPtr);\r
 \r
   TimeStampCounterStart = AsmReadTsc ();\r
-  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x9000);\r
+  PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
   Status = CallFspSiliconInit ((VOID *)FspsUpdDataPtr);\r
-  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x907F);\r
+  PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
   DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d millisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCounterStart), 1000000)));\r
 \r
   //\r