// }\r
//\r
\r
-/**\r
- Return the size of argument that has been aligned to sizeof (UINTN).\r
-\r
- @param n The parameter size is to be aligned.\r
-\r
- @return The aligned size\r
-**/\r
-#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))\r
-\r
#if defined(__GNUC__)\r
//\r
-// Use GCC builtin macros for variable argument lists.\r
+// Use GCC built-in macros for variable argument lists.\r
//\r
typedef __builtin_va_list VA_LIST;\r
\r
#define VA_END(Marker) __builtin_va_end (Marker)\r
\r
#else\r
+/**\r
+ Return the size of argument that has been aligned to sizeof (UINTN).\r
+\r
+ @param n The parameter size to be aligned.\r
+\r
+ @return The aligned size\r
+**/\r
+#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))\r
+\r
///\r
/// Pointer to the start of a variable argument list. Same as CHAR8 *.\r
///\r
\r
#endif\r
\r
-///\r
-/// Pointer to the start of a variable argument list stored in a memory buffer. Same as UINT8 *.\r
-///\r
-typedef UINTN *BASE_LIST;\r
-\r
-/**\r
- Returns an argument of a specified type from a variable argument list and updates \r
- the pointer to the variable argument list to point to the next argument. \r
-\r
- This function returns an argument of the type specified by TYPE from the beginning \r
- of the variable argument list specified by Marker. Marker is then updated to point \r
- to the next argument in the variable argument list. The method for computing the \r
- pointer to the next argument in the argument list is CPU specific following the EFIAPI ABI.\r
-\r
- @param Marker Pointer to the beginning of a variable argument list.\r
- @param TYPE The type of argument to retrieve from the beginning \r
- of the variable argument list.\r
- \r
- @return An argument of the type specified by TYPE.\r
-\r
-**/\r
-#define BASE_ARG(Marker, TYPE) (*(TYPE *)((UINT8 *)(Marker = (BASE_LIST)((UINT8 *)Marker + _INT_SIZE_OF (TYPE))) - _INT_SIZE_OF (TYPE)))\r
-\r
/**\r
Macro that returns the byte offset of a field in a data structure. \r
\r
\r
This function computes the offset, in bytes, of field specified by Field from the beginning \r
of the data structure specified by TYPE. This offset is subtracted from Record, and is \r
- used to return a pointer to a data structure of the type specified by TYPE.If the data type \r
+ used to return a pointer to a data structure of the type specified by TYPE. If the data type \r
specified by TYPE does not contain the field specified by Field, then the module will not compile. \r
\r
@param Record Pointer to the field specified by Field within a data structure of type TYPE. \r
/** @file\r
Processor or compiler specific defines and types for EBC.\r
\r
- We currently only have one EBC complier so there may be some Intel compiler\r
+ We currently only have one EBC compiler so there may be some Intel compiler\r
specific functions in this file.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation<BR> \r
/** @file\r
GUID used as an FV filename for A Priori file. The A Priori file contains a\r
list of FV filenames that the DXE dispatcher will schedule reguardless of\r
- the dependency grammer.\r
+ the dependency grammar.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
/** @file\r
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.SetInfo()\r
and EFI_FILE_PROTOCOL.GetInfo() to set or get generic file information.\r
- This guid is defined in UEFI specification.\r
+ This GUID is defined in UEFI specification.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
/** @file\r
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo()\r
or EFI_FILE_PROTOCOL.SetInfo() to get or set information about the system's volume.\r
- This guid is defined in UEFI specification.\r
+ This GUID is defined in UEFI specification.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
/** @file\r
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo()\r
or EFI_FILE_PROTOCOL.SetInfo() to get or set the system's volume label.\r
- This guid is defined in UEFI specification.\r
+ This GUID is defined in UEFI specification.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
/** @file\r
GUIDs used for MPS entries in the UEFI 2.0 system table\r
- ACPI is the primary means of exporting MP information to the OS. MPS obly was\r
+ ACPI is the primary means of exporting MPS information to the OS. MPS only was\r
included to support Itanium-based platform power on. So don't use it if you don't have too.\r
\r
Copyright (c) 2006, Intel Corporation \r
/** @file\r
- Processor or Compiler specific defines and types for Ia32 architecture.\r
+ Processor or Compiler specific defines and types for IA-32 architecture.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation<BR> \r
All rights reserved. This program and the accompanying materials \r
#endif\r
\r
//\r
-// Macros for GNU assembly code\r
+// For symbol name in GNU assembly code, an extra "_" is necessary\r
//\r
#if defined(__GNUC__)\r
#if defined(linux)\r
#else\r
#define ASM_PFX(name) _##name\r
#endif \r
- ///\r
- /// For GNU assembly code, .global or .globl can declare global symbols.\r
- /// Define this macro to unify the usage.\r
- ///\r
- #define ASM_GLOBAL .globl\r
#endif\r
\r
/**\r
Return the pointer to the first instruction of a function given a function pointer.\r
- On IA32 CPU architectures, these two pointer values are the same, \r
+ On IA-32 CPU architectures, these two pointer values are the same, \r
so the implementation of this macro is very simple.\r
\r
@param FunctionPointer A pointer to a function.\r
/**\r
PAL Procedure - PAL_CACHE_FLUSH.\r
\r
- Flush the instruction or data caches. It is required by IPF.\r
+ Flush the instruction or data caches. It is required by Itanium processors.\r
The PAL procedure supports the Static Registers calling\r
convention. It could be called at virtual mode and physical\r
mode.\r
PAL Procedure - PAL_CACHE_INFO.\r
\r
Return detailed instruction or data cache information. It is\r
- required by IPF. The PAL procedure supports the Static\r
+ required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at virtual\r
mode and physical mode.\r
\r
PAL Procedure - PAL_CACHE_INIT.\r
\r
Initialize the instruction or data caches. It is required by\r
- IPF. The PAL procedure supports the Static Registers calling\r
+ Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_CACHE_INIT within the list of PAL\r
PAL Procedure - PAL_CACHE_PROT_INFO.\r
\r
Return instruction or data cache protection information. It is\r
- required by IPF. The PAL procedure supports the Static\r
+ required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode and Virtual mode.\r
\r
PAL Procedure - PAL_CACHE_SUMMARY.\r
\r
Return a summary of the cache hierarchy. It is required by\r
- IPF. The PAL procedure supports the Static Registers calling\r
+ Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and Virtual\r
mode.\r
\r
PAL Procedure - PAL_MEM_ATTRIB.\r
\r
Return a list of supported memory attributes.. It is required\r
- by IPF. The PAL procedure supports the Static Registers calling\r
+ by Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and Virtual\r
mode.\r
\r
\r
Used in architected sequence to transition pages from a\r
cacheable, speculative attribute to an uncacheable attribute.\r
- It is required by IPF. The PAL procedure supports the Static\r
+ It is required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode and Virtual mode.\r
\r
PAL Procedure - PAL_PTCE_INFO.\r
\r
Return information needed for ptc.e instruction to purge\r
- entire TC. It is required by IPF. The PAL procedure supports\r
+ entire TC. It is required by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical mode and Virtual mode.\r
\r
PAL Procedure - PAL_VM_INFO.\r
\r
Return detailed information about virtual memory features\r
- supported in the processor. It is required by IPF. The PAL\r
+ supported in the processor. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
PAL Procedure - PAL_VM_PAGE_SIZE.\r
\r
Return virtual memory TC and hardware walker page sizes\r
- supported in the processor. It is required by IPF. The PAL\r
+ supported in the processor. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
PAL Procedure - PAL_VM_SUMMARY.\r
\r
Return summary information about virtual memory features\r
- supported in the processor. It is required by IPF. The PAL\r
+ supported in the processor. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
PAL Procedure - PAL_VM_TR_READ.\r
\r
Read contents of a translation register. It is required by\r
- IPF. The PAL procedure supports the Stacked Register calling\r
+ Itanium processors. The PAL procedure supports the Stacked Register calling\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_VM_TR_READ within the list\r
PAL Procedure - PAL_BUS_GET_FEATURES.\r
\r
Return configurable processor bus interface features and their\r
- current settings. It is required by IPF. The PAL procedure\r
+ current settings. It is required by Itanium processors. The PAL procedure\r
supports the Stacked Register calling convention. It could be\r
called at physical mode.\r
\r
PAL Procedure - PAL_BUS_SET_FEATURES.\r
\r
Enable or disable configurable features in processor bus\r
- interface. It is required by IPF. It is required by IPF. The PAL procedure\r
+ interface. It is required by Itanium processors. The PAL procedure\r
supports the Static Registers calling convention. It could be\r
called at physical mode.\r
\r
PAL Procedure - PAL_DEBUG_INFO.\r
\r
Return the number of instruction and data breakpoint\r
- registers. It is required by IPF. It is required by IPF. The\r
+ registers. It is required by Itanium processors. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
PAL Procedure - PAL_FIXED_ADDR.\r
\r
Return the fixed component of a processor's directed address.\r
- It is required by IPF. It is required by IPF. The PAL\r
+ It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
\r
Return ratio of processor, bus, and interval time counter to\r
processor input clock or output clock for platform use, if\r
- generated by the processor. It is required by IPF. The PAL\r
+ generated by the processor. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
PAL Procedure - PAL_PERF_MON_INFO.\r
\r
Return the number and type of performance monitors. It is\r
- required by IPF. The PAL procedure supports the Static\r
+ required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode and virtual mode.\r
\r
PAL Procedure - PAL_PLATFORM_ADDR.\r
\r
Specify processor interrupt block address and I/O port space\r
- address. It is required by IPF. The PAL procedure supports the\r
+ address. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
\r
PAL Procedure - PAL_PROC_GET_FEATURES.\r
\r
Return configurable processor features and their current\r
- setting. It is required by IPF. The PAL procedure supports the\r
+ setting. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
\r
PAL Procedure - PAL_PROC_SET_FEATURES.\r
\r
Enable or disable configurable processor features. It is\r
- required by IPF. The PAL procedure supports the Static\r
+ required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode.\r
\r
/**\r
PAL Procedure - PAL_REGISTER_INFO.\r
\r
- Return AR and CR register information. It is required by IPF.\r
+ Return AR and CR register information. It is required by Itanium processors.\r
The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
/**\r
PAL Procedure - PAL_RSE_INFO.\r
\r
- Return RSE information. It is required by IPF. The PAL\r
+ Return RSE information. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
/**\r
PAL Procedure - PAL_VERSION.\r
\r
- Return version of PAL code. It is required by IPF. The PAL\r
+ Return version of PAL code. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
PAL Procedure - PAL_MC_CLEAR_LOG.\r
\r
Clear all error information from processor error logging\r
- registers. It is required by IPF. The PAL procedure supports\r
+ registers. It is required by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
\r
PAL Procedure - PAL_MC_DRAIN.\r
\r
Ensure that all operations that could cause an MCA have\r
- completed. It is required by IPF. The PAL procedure supports\r
+ completed. It is required by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
\r
PAL Procedure - PAL_MC_ERROR_INFO.\r
\r
Return Processor Machine Check Information and Processor\r
- Static State for logging by SAL. It is required by IPF. The\r
+ Static State for logging by SAL. It is required by Itanium processors. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical and virtual mode.\r
\r
PAL Procedure - PAL_MC_EXPECTED.\r
\r
Set/Reset Expected Machine Check Indicator. It is required by\r
- IPF. The PAL procedure supports the Static Registers calling\r
+ Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_MC_EXPECTED within the list of PAL\r
PAL Procedure - PAL_MC_REGISTER_MEM.\r
\r
Register min-state save area with PAL for machine checks and\r
- inits. It is required by IPF. The PAL procedure supports the\r
+ inits. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
\r
PAL Procedure - PAL_MC_RESUME.\r
\r
Restore minimal architected state and return to interrupted\r
- process. It is required by IPF. The PAL procedure supports the\r
+ process. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
\r
PAL Procedure - PAL_HALT_INFO.\r
\r
Return the low power capabilities of the processor. It is\r
- required by IPF. The PAL procedure supports the\r
+ required by Itanium processors. The PAL procedure supports the\r
Stacked Registers calling convention. It could be called at\r
physical and virtual mode.\r
\r
PAL Procedure - PAL_HALT_LIGHT.\r
\r
Enter the low power LIGHT HALT state. It is required by\r
- IPF. The PAL procedure supports the Static Registers calling\r
+ Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical and virtual mode.\r
\r
@param Index Index of PAL_HALT_LIGHT within the list of PAL\r
PAL Procedure - PAL_CACHE_LINE_INIT.\r
\r
Initialize tags and data of a cache line for processor\r
- testing. It is required by IPF. The PAL procedure supports the\r
+ testing. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical and virtual mode.\r
\r
Returns alignment and size requirements needed for the memory\r
buffer passed to the PAL_TEST_PROC procedure as well as\r
information on self-test control words for the processor self\r
- tests. It is required by IPF. The PAL procedure supports the\r
+ tests. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
\r
/**\r
PAL Procedure - PAL_TEST_PROC.\r
\r
- Perform late processor self test. It is required by IPF. The\r
+ Perform late processor self test. It is required by Itanium processors. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
\r
PAL Procedure - PAL_COPY_INFO.\r
\r
Return information needed to relocate PAL procedures and PAL\r
- PMI code to memory. It is required by IPF. The PAL procedure\r
+ PMI code to memory. It is required by Itanium processors. The PAL procedure\r
supports the Static Registers calling convention. It could be\r
called at physical mode.\r
\r
PAL Procedure - PAL_COPY_PAL.\r
\r
Relocate PAL procedures and PAL PMI code to memory. It is\r
- required by IPF. The PAL procedure supports the Stacked\r
+ required by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at physical\r
mode.\r
\r
PAL Procedure - PAL_PMI_ENTRYPOINT.\r
\r
Register PMI memory entrypoints with processor. It is required\r
- by IPF. The PAL procedure supports the Stacked Registers\r
+ by Itanium processors. The PAL procedure supports the Stacked Registers\r
calling convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_PMI_ENTRYPOINT within the list of\r
PAL Procedure - PAL_BRAND_INFO.\r
\r
Provides processor branding information. It is optional by\r
- IPF. The PAL procedure supports the Stacked Registers calling\r
+ Itanium processors. The PAL procedure supports the Stacked Registers calling\r
convention. It could be called at physical and Virtual mode.\r
\r
@param Index Index of PAL_BRAND_INFO within the list of PAL\r
PAL Procedure - PAL_GET_HW_POLICY.\r
\r
Returns the current hardware resource sharing policy of the\r
- processor. It is optional by IPF. The PAL procedure supports\r
+ processor. It is optional by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical and Virtual mode.\r
\r
PAL Procedure - PAL_SET_HW_POLICY.\r
\r
Sets the current hardware resource sharing policy of the\r
- processor. It is optional by IPF. The PAL procedure supports\r
+ processor. It is optional by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical and Virtual mode.\r
\r
\r
Injects the requested processor error or returns information\r
on the supported injection capabilities for this particular\r
- processor implementation. It is optional by IPF. The PAL\r
+ processor implementation. It is optional by Itanium processors. The PAL\r
procedure supports the Stacked Registers calling convention.\r
It could be called at physical and Virtual mode.\r
\r
PAL Procedure - PAL_GET_PSTATE.\r
\r
Returns the performance index of the processor. It is optional\r
- by IPF. The PAL procedure supports the Stacked Registers\r
+ by Itanium processors. The PAL procedure supports the Stacked Registers\r
calling convention. It could be called at physical and Virtual\r
mode.\r
\r
PAL Procedure - PAL_PSTATE_INFO.\r
\r
Returns information about the P-states supported by the\r
- processor. It is optional by IPF. The PAL procedure supports\r
+ processor. It is optional by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called\r
at physical and Virtual mode.\r
\r
PAL Procedure - PAL_SET_PSTATE.\r
\r
To request a processor transition to a given P-state. It is\r
- optional by IPF. The PAL procedure supports the Stacked\r
+ optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at physical\r
and Virtual mode.\r
\r
PAL Procedure - PAL_SHUTDOWN.\r
\r
Put the logical processor into a low power state which can be\r
- exited only by a reset event. It is optional by IPF. The PAL\r
+ exited only by a reset event. It is optional by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode.\r
\r
PAL Procedure - PAL_MEMORY_BUFFER.\r
\r
Provides cacheable memory to PAL for exclusive use during\r
- runtime. It is optional by IPF. The PAL procedure supports the\r
+ runtime. It is optional by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
\r
PAL Procedure - PAL_VP_CREATE.\r
\r
Initializes a new vpd for the operation of a new virtual\r
- processor in the virtual environment. It is optional by IPF.\r
+ processor in the virtual environment. It is optional by Itanium processors.\r
The PAL procedure supports the Stacked Registers calling\r
convention. It could be called at Virtual mode.\r
\r
PAL Procedure - PAL_VP_ENV_INFO.\r
\r
Returns the parameters needed to enter a virtual environment.\r
- It is optional by IPF. The PAL procedure supports the Stacked\r
+ It is optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
mode.\r
\r
PAL Procedure - PAL_VP_EXIT_ENV.\r
\r
Allows a logical processor to exit a virtual environment.\r
- It is optional by IPF. The PAL procedure supports the Stacked\r
+ It is optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
mode.\r
\r
PAL Procedure - PAL_VP_INIT_ENV.\r
\r
Allows a logical processor to enter a virtual environment. It\r
- is optional by IPF. The PAL procedure supports the Stacked\r
+ is optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
mode.\r
\r
\r
Register a different host IVT and/or a different optional\r
virtualization intercept handler for the virtual processor\r
- specified by vpd. It is optional by IPF. The PAL procedure\r
+ specified by vpd. It is optional by Itanium processors. The PAL procedure\r
supports the Stacked Registers calling convention. It could be\r
called at Virtual mode.\r
\r
PAL Procedure - PAL_VP_RESTORE.\r
\r
Restores virtual processor state for the specified vpd on the\r
- logical processor. It is optional by IPF. The PAL procedure\r
+ logical processor. It is optional by Itanium processors. The PAL procedure\r
supports the Stacked Registers calling convention. It could be\r
called at Virtual mode.\r
\r
PAL Procedure - PAL_VP_SAVE.\r
\r
Saves virtual processor state for the specified vpd on the\r
- logical processor. It is optional by IPF. The PAL procedure\r
+ logical processor. It is optional by Itanium processors. The PAL procedure\r
supports the Stacked Registers calling convention. It could be\r
called at Virtual mode.\r
\r
PAL Procedure - PAL_VP_TERMINATE.\r
\r
Terminates operation for the specified virtual processor. It\r
- is optional by IPF. The PAL procedure supports the Stacked\r
+ is optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
mode.\r
\r
/** @file\r
- Support for The latest PCI standard.\r
+ Support for the latest PCI standard.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation\r
All rights reserved. This program and the accompanying materials \r
///\r
typedef UINT32 TPM_NV_INDEX;\r
///\r
-/// The family ID. Families ID's are automatically assigned a sequence number by the TPM. \r
+/// The family ID. Family IDs are automatically assigned a sequence number by the TPM. \r
/// A trusted process can set the FamilyID value in an individual row to NULL, which \r
/// invalidates that row. The family ID resets to NULL on each change of TPM Owner.\r
///\r
/** @file\r
- Processor or Compiler specific defines and types for Intel Itanium(TM).\r
+ Processor or Compiler specific defines and types for Intel Itanium(TM) processors.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
\r
\r
///\r
-/// Define the processor type so other code can make processor based choices\r
+/// Define the processor type so other code can make processor-based choices\r
///\r
#define MDE_CPU_IPF\r
\r
\r
//\r
// Can not cast a function pointer to a data pointer. We need to do this on\r
-// IPF to get access to the PLABEL.\r
+// Itanium processors to get access to the PLABEL.\r
//\r
#pragma warning ( disable : 4514 )\r
\r
\r
#if defined(_MSC_EXTENSIONS)\r
//\r
- // use Microsoft C complier dependent integer width types\r
+ // use Microsoft C compiler dependent integer width types\r
//\r
\r
///\r
#define GLOBAL_REMOVE_IF_UNREFERENCED\r
#endif\r
\r
-///\r
-/// For GNU assembly code, .global or .globl can declare global symbols.\r
-/// Define this macro to unify the usage.\r
-///\r
-#define ASM_GLOBAL .globl\r
-\r
///\r
/// A pointer to a function in IPF points to a plabel.\r
///\r
\r
/**\r
Return the pointer to the first instruction of a function given a function pointer.\r
- For Itanium CPUs, all function calls are made through a PLABEL, so a pointer to a function \r
+ For Itanium processors, all function calls are made through a PLABEL, so a pointer to a function \r
is actually a pointer to a PLABEL. The pointer to the first instruction of the function \r
is contained within the PLABEL. This macro may be used to retrieve a pointer to the first \r
instruction of a function independent of the CPU architecture being used. This is very \r
/** @file\r
Provides string functions, linked list functions, math functions, synchronization\r
- functions, and CPU architecture specific functions.\r
+ functions, and CPU architecture-specific functions.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
#define __BASE_LIB__\r
\r
//\r
-// Definitions for architecture specific types\r
+// Definitions for architecture-specific types\r
//\r
#if defined (MDE_CPU_IA32)\r
///\r
-/// IA32 context buffer used by SetJump() and LongJump()\r
+/// IA-32 architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT32 Ebx;\r
#if defined (MDE_CPU_IPF)\r
\r
///\r
-/// IPF context buffer used by SetJump() and LongJump()\r
+/// Itanium architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT64 F2[2];\r
\r
#if defined (MDE_CPU_X64)\r
///\r
-/// x64 context buffer used by SetJump() and LongJump()\r
+/// x64 architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT64 Rbx;\r
calls to LongJump() cause a non-zero value to be returned by SetJump().\r
\r
If JumpBuffer is NULL, then ASSERT().\r
- For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
\r
NOTE: The structure BASE_LIBRARY_JUMP_BUFFER is CPU architecture specific.\r
The same structure must never be used for more than one CPU architecture context.\r
the state of JumpBuffer.\r
\r
If JumpBuffer is NULL, then ASSERT().\r
- For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
If Value is 0, then ASSERT().\r
\r
@param JumpBuffer A pointer to CPU context buffer.\r
by Context1 and Context2. Context1 and Context2 are optional and may\r
be NULL. The function EntryPoint must never return. This function\r
supports a variable number of arguments following the NewStack parameter.\r
- These additional arguments are ignored on IA-32, x64, and EBC.\r
- IPF CPUs expect one additional parameter of type VOID * that specifies\r
+ These additional arguments are ignored on IA-32, x64, and EBC architectures.\r
+ Itanium processors expect one additional parameter of type VOID * that specifies\r
the new backing store pointer.\r
\r
If EntryPoint is NULL, then ASSERT().\r
function.\r
@param NewStack A pointer to the new stack to use for the EntryPoint\r
function.\r
- @param ... This variable argument list is ignored for IA32, x64, and EBC. \r
- For IPF, this variable argument list is expected to contain \r
+ @param ... This variable argument list is ignored for IA-32, x64, and EBC architectures. \r
+ For Itanium processors, this variable argument list is expected to contain \r
a single parameter of type VOID * that specifies the new backing \r
store pointer.\r
\r
line containing Address + Length - 1 is flushed. This function may choose to flush \r
the entire cache if that is more efficient than flushing the specified range. If \r
Length is 0, the no cache lines are flushed. Address is returned. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
Executes a FC instruction\r
Executes a FC instruction on the cache line specified by Address.\r
The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on IPF.\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
\r
@param Address The Address of cache line to be flushed.\r
\r
Executes a FC.I instruction.\r
Executes a FC.I instruction on the cache line specified by Address.\r
The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on IPF.\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
\r
@param Address The Address of cache line to be flushed.\r
\r
No parameter checking is performed on Index. If the Index value is beyond the\r
implemented CPUID register range, a Reserved Register/Field fault may occur. The caller\r
must either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults. This function is only available on IPF.\r
+ catch the faults. This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Processor Identifier Register index to read.\r
\r
\r
/**\r
Reads the current value of 64-bit Processor Status Register (PSR).\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of PSR.\r
\r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults. This function is only available on IPF.\r
+ fault handlers to catch the faults. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PSR.\r
\r
Reads the current value of 64-bit Kernel Register #0 (KR0).\r
\r
Reads and returns the current value of KR0. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR0.\r
\r
Reads the current value of 64-bit Kernel Register #1 (KR1).\r
\r
Reads and returns the current value of KR1. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR1.\r
\r
Reads the current value of 64-bit Kernel Register #2 (KR2).\r
\r
Reads and returns the current value of KR2. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR2.\r
\r
Reads the current value of 64-bit Kernel Register #3 (KR3).\r
\r
Reads and returns the current value of KR3. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR3.\r
\r
Reads the current value of 64-bit Kernel Register #4 (KR4).\r
\r
Reads and returns the current value of KR4. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR4.\r
\r
Reads the current value of 64-bit Kernel Register #5 (KR5).\r
\r
Reads and returns the current value of KR5. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR5.\r
\r
Reads the current value of 64-bit Kernel Register #6 (KR6).\r
\r
Reads and returns the current value of KR6. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR6.\r
\r
Reads the current value of 64-bit Kernel Register #7 (KR7).\r
\r
Reads and returns the current value of KR7. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR7.\r
\r
Write the current value of 64-bit Kernel Register #0 (KR0).\r
\r
Writes the current value of KR0. The 64-bit value written to \r
- the KR0 is returned. This function is only available on IPF.\r
+ the KR0 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR0.\r
\r
Write the current value of 64-bit Kernel Register #1 (KR1).\r
\r
Writes the current value of KR1. The 64-bit value written to \r
- the KR1 is returned. This function is only available on IPF.\r
+ the KR1 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR1.\r
\r
Write the current value of 64-bit Kernel Register #2 (KR2).\r
\r
Writes the current value of KR2. The 64-bit value written to \r
- the KR2 is returned. This function is only available on IPF.\r
+ the KR2 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR2.\r
\r
Write the current value of 64-bit Kernel Register #3 (KR3).\r
\r
Writes the current value of KR3. The 64-bit value written to \r
- the KR3 is returned. This function is only available on IPF.\r
+ the KR3 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR3.\r
\r
Write the current value of 64-bit Kernel Register #4 (KR4).\r
\r
Writes the current value of KR4. The 64-bit value written to \r
- the KR4 is returned. This function is only available on IPF.\r
+ the KR4 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR4.\r
\r
Write the current value of 64-bit Kernel Register #5 (KR5).\r
\r
Writes the current value of KR5. The 64-bit value written to \r
- the KR5 is returned. This function is only available on IPF.\r
+ the KR5 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR5.\r
\r
Write the current value of 64-bit Kernel Register #6 (KR6).\r
\r
Writes the current value of KR6. The 64-bit value written to \r
- the KR6 is returned. This function is only available on IPF.\r
+ the KR6 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR6.\r
\r
Write the current value of 64-bit Kernel Register #7 (KR7).\r
\r
Writes the current value of KR7. The 64-bit value written to \r
- the KR7 is returned. This function is only available on IPF.\r
+ the KR7 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR7.\r
\r
Reads the current value of Interval Timer Counter Register (ITC).\r
\r
Reads and returns the current value of ITC.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITC.\r
\r
Reads the current value of Interval Timer Vector Register (ITV).\r
\r
Reads and returns the current value of ITV. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITV.\r
\r
Reads the current value of Interval Timer Match Register (ITM).\r
\r
Reads and returns the current value of ITM.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITM.\r
**/\r
Writes the current value of 64-bit Interval Timer Counter Register (ITC).\r
\r
Writes the current value of ITC. The 64-bit value written to the ITC is returned. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITC.\r
\r
Writes the current value of 64-bit Interval Timer Match Register (ITM).\r
\r
Writes the current value of ITM. The 64-bit value written to the ITM is returned. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITM.\r
\r
reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITV.\r
\r
/**\r
Reads the current value of Default Control Register (DCR).\r
\r
- Reads and returns the current value of DCR. This function is only available on IPF.\r
+ Reads and returns the current value of DCR. This function is only available on Itanium processors.\r
\r
@return The current value of DCR.\r
\r
/**\r
Reads the current value of Interruption Vector Address Register (IVA).\r
\r
- Reads and returns the current value of IVA. This function is only available on IPF.\r
+ Reads and returns the current value of IVA. This function is only available on Itanium processors.\r
\r
@return The current value of IVA.\r
**/\r
/**\r
Reads the current value of Page Table Address Register (PTA).\r
\r
- Reads and returns the current value of PTA. This function is only available on IPF.\r
+ Reads and returns the current value of PTA. This function is only available on Itanium processors.\r
\r
@return The current value of PTA.\r
\r
reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to DCR.\r
\r
Writes the current value of IVA. The 64-bit value written to the IVA is returned. \r
The size of vector table is 32 K bytes and is 32 K bytes aligned\r
the low 15 bits of Value is ignored when written.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to IVA.\r
\r
reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PTA.\r
\r
/**\r
Reads the current value of Local Interrupt ID Register (LID).\r
\r
- Reads and returns the current value of LID. This function is only available on IPF.\r
+ Reads and returns the current value of LID. This function is only available on Itanium processors.\r
\r
@return The current value of LID.\r
\r
/**\r
Reads the current value of External Interrupt Vector Register (IVR).\r
\r
- Reads and returns the current value of IVR. This function is only available on IPF. \r
+ Reads and returns the current value of IVR. This function is only available on Itanium processors. \r
\r
@return The current value of IVR.\r
\r
/**\r
Reads the current value of Task Priority Register (TPR).\r
\r
- Reads and returns the current value of TPR. This function is only available on IPF. \r
+ Reads and returns the current value of TPR. This function is only available on Itanium processors. \r
\r
@return The current value of TPR.\r
\r
/**\r
Reads the current value of External Interrupt Request Register #0 (IRR0).\r
\r
- Reads and returns the current value of IRR0. This function is only available on IPF. \r
+ Reads and returns the current value of IRR0. This function is only available on Itanium processors. \r
\r
@return The current value of IRR0.\r
\r
/**\r
Reads the current value of External Interrupt Request Register #1 (IRR1).\r
\r
- Reads and returns the current value of IRR1. This function is only available on IPF. \r
+ Reads and returns the current value of IRR1. This function is only available on Itanium processors. \r
\r
@return The current value of IRR1.\r
\r
/**\r
Reads the current value of External Interrupt Request Register #2 (IRR2).\r
\r
- Reads and returns the current value of IRR2. This function is only available on IPF.\r
+ Reads and returns the current value of IRR2. This function is only available on Itanium processors.\r
\r
@return The current value of IRR2.\r
\r
/**\r
Reads the current value of External Interrupt Request Register #3 (IRR3).\r
\r
- Reads and returns the current value of IRR3. This function is only available on IPF. \r
+ Reads and returns the current value of IRR3. This function is only available on Itanium processors. \r
\r
@return The current value of IRR3.\r
\r
/**\r
Reads the current value of Performance Monitor Vector Register (PMV).\r
\r
- Reads and returns the current value of PMV. This function is only available on IPF. \r
+ Reads and returns the current value of PMV. This function is only available on Itanium processors. \r
\r
@return The current value of PMV.\r
\r
/**\r
Reads the current value of Corrected Machine Check Vector Register (CMCV).\r
\r
- Reads and returns the current value of CMCV. This function is only available on IPF.\r
+ Reads and returns the current value of CMCV. This function is only available on Itanium processors.\r
\r
@return The current value of CMCV.\r
\r
/**\r
Reads the current value of Local Redirection Register #0 (LRR0).\r
\r
- Reads and returns the current value of LRR0. This function is only available on IPF. \r
+ Reads and returns the current value of LRR0. This function is only available on Itanium processors. \r
\r
@return The current value of LRR0.\r
\r
/**\r
Reads the current value of Local Redirection Register #1 (LRR1).\r
\r
- Reads and returns the current value of LRR1. This function is only available on IPF.\r
+ Reads and returns the current value of LRR1. This function is only available on Itanium processors.\r
\r
@return The current value of LRR1.\r
\r
reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LID.\r
\r
reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to TPR.\r
\r
/**\r
Performs a write operation on End OF External Interrupt Register (EOI).\r
\r
- Writes a value of 0 to the EOI Register. This function is only available on IPF.\r
+ Writes a value of 0 to the EOI Register. This function is only available on Itanium processors.\r
\r
**/\r
VOID\r
to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PMV.\r
\r
to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to CMCV.\r
\r
to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LRR0.\r
\r
to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LRR1.\r
\r
is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
occur. The caller must either guarantee that Index is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Instruction Breakpoint Register index to read.\r
\r
the implemented DBR register range, a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Index is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Data Breakpoint Register index to read.\r
\r
register set is implementation dependent. No parameter checking is performed\r
on Index. If the Index value is beyond the implemented PMC register range,\r
zero value will be returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Configuration Register index to read.\r
\r
register set is implementation dependent. No parameter checking is performed\r
on Index. If the Index value is beyond the implemented PMD register range,\r
zero value will be returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Data Register index to read.\r
\r
is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
occur. The caller must either guarantee that Index is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Instruction Breakpoint Register index to write.\r
@param Value The 64-bit value to write to IBR.\r
DBR register range, a Reserved Register/Field fault may occur. The caller must\r
either guarantee that Index is valid, or the caller must set up fault handlers to\r
catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Data Breakpoint Register index to write.\r
@param Value The 64-bit value to write to DBR.\r
counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation\r
dependent. No parameter checking is performed on Index. If the Index value is\r
beyond the implemented PMC register range, the write is ignored.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Configuration Register index to write.\r
@param Value The 64-bit value to write to PMC.\r
performance counters (PMC/PMD pairs). The remainder of PMC and PMD register set\r
is implementation dependent. No parameter checking is performed on Index. If the\r
Index value is beyond the implemented PMD register range, the write is ignored.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Data Register index to write.\r
@param Value The 64-bit value to write to PMD.\r
Reads the current value of 64-bit Global Pointer (GP).\r
\r
Reads and returns the current value of GP.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of GP.\r
\r
\r
Writes the current value of GP. The 64-bit value written to the GP is returned.\r
No parameter checking is performed on Value.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to GP.\r
\r
Reads the current value of 64-bit Stack Pointer (SP).\r
\r
Reads and returns the current value of SP.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of SP.\r
\r
\r
Reads and returns the control register specified by Index. The valid Index valued are defined\r
above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.\r
+ If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on Itanium processors.\r
\r
@param Index The index of the control register to read.\r
\r
\r
Reads and returns the application register specified by Index. The valid Index valued are defined\r
above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.\r
+ If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on Itanium processors.\r
\r
@param Index The index of the application register to read.\r
\r
parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on IPF.\r
+ only available on Itanium processors.\r
\r
@param Index The 8-bit Machine Specific Register index to read.\r
\r
parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on IPF.\r
+ only available on Itanium processors.\r
\r
@param Index The 8-bit Machine Specific Register index to write.\r
@param Value The 64-bit value to write to the Machine Specific Register.\r
If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.\r
If the CPU is not in physical mode or virtual mode, then it is in mixed mode,\r
and -1 is returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@retval 1 The CPU is in virtual mode.\r
@retval 0 The CPU is in physical mode.\r
argument return value may be returned or undefined result may occur during the\r
execution of the procedure. If the PalEntryPoint does not point to a valid\r
PAL entry point then the system behavior is undefined. This function is only\r
- available on IPF.\r
+ available on Itanium processors.\r
\r
@param PalEntryPoint The PAL procedure calls entry point.\r
@param Index The PAL procedure Index number.\r
\r
#if defined (MDE_CPU_IA32)\r
///\r
-/// Byte packed structure for an IA32 Interrupt Gate Descriptor\r
+/// Byte packed structure for an IA-32 Interrupt Gate Descriptor\r
///\r
typedef union {\r
struct {\r
aligned on a cache line boundary, then the entire instruction cache line\r
containing Address + Length -1 is invalidated. This function may choose to\r
invalidate the entire instruction cache if that is more efficient than\r
- invalidating the specified range. If Length is 0, the no instruction cache\r
+ invalidating the specified range. If Length is 0, then no instruction cache\r
lines are invalidated. Address is returned.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
line containing Address + Length -1 is written back and invalidated. This\r
function may choose to write back and invalidate the entire data cache if\r
that is more efficient than writing back and invalidating the specified\r
- range. If Length is 0, the no data cache lines are written back and\r
+ range. If Length is 0, then no data cache lines are written back and\r
invalidated. Address is returned.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
cache line boundary, then the entire data cache line containing Address +\r
Length -1 is written back. This function may choose to write back the entire\r
data cache if that is more efficient than writing back the specified range.\r
- If Length is 0, the no data cache lines are written back. This function may\r
+ If Length is 0, then no data cache lines are written back. This function may\r
also invalidate all the data cache lines in the specified range of the cache\r
coherency domain of the calling CPU. Address is returned.\r
\r
in the Base Library due to dependencies on the PAL Library\r
\r
The CPU Library provides services to flush CPU TLBs and place the CPU in a sleep state.\r
- The implementation of these services on Itanium CPUs requires the use of PAL Calls.\r
+ The implementation of these services on Itanium processors requires the use of PAL Calls.\r
PAL Calls require PEI and DXE specific mechanisms to look up PAL Entry Point.\r
As a result, these services could not be defined in the Base Library.\r
\r
/** \r
Internal worker macro that calls DebugAssert().\r
\r
- This macro calls DebugAssert() passing in the filename, line number, and \r
- expression that evailated to FALSE.\r
+ This macro calls DebugAssert(), passing in the filename, line number, and an\r
+ expression that evaluated to FALSE.\r
\r
- @param Expression Boolean expression that evailated to FALSE\r
+ @param Expression Boolean expression that evaluated to FALSE\r
\r
**/\r
#define _ASSERT(Expression) DebugAssert (__FILE__, __LINE__, #Expression)\r
\r
\r
/** \r
- Macro that calls DebugAssert() if a expression evaluates to FALSE.\r
+ Macro that calls DebugAssert() if an expression evaluates to FALSE.\r
\r
If the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set, \r
then this macro evaluates the Boolean expression specified by Expression. If \r
\r
**/\r
\r
-#ifndef __DXE_SERVICES_LIB_H__\r
-#define __DXE_SERVICES_LIB_H__\r
+#ifndef __PI_LIB_H__\r
+#define __PI_LIB_H__\r
+\r
+#include <Pi/PiFirmwareFile.h>\r
+\r
\r
/**\r
- Searches all the availables firmware volumes and returns the first matching FFS section. \r
+ Searches all the available firmware volumes and returns the first matching FFS section. \r
\r
This function searches all the firmware volumes for FFS files with an FFS filename specified by NameGuid. \r
- The order that the firmware volumes is searched is not deterministic. For each FFS file found a search \r
+ The order in which the firmware volumes are searched is not deterministic. For each FFS file found, a search \r
is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances \r
of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer. \r
Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size. \r
@param SectionType Indicates the FFS section type to search for within the FFS file specified by NameGuid.\r
@param SectionInstance Indicates which section instance within the FFS file specified by NameGuid to retrieve.\r
@param Buffer On output, a pointer to a callee allocated buffer containing the FFS file section that was found. \r
- Is it the caller's responsibility to free this buffer using FreePool().\r
+ It is the caller's responsibility to free this buffer using FreePool().\r
@param Size On output, a pointer to the size, in bytes, of Buffer.\r
\r
@retval EFI_SUCCESS The specified FFS section was returned.\r
Searches the firmware volume that the currently executing module was loaded from and returns the first matching FFS section. \r
\r
This function searches the firmware volume that the currently executing module was loaded \r
- from for an FFS file with an FFS filename specified by NameGuid. If the FFS file is found a search \r
+ from for an FFS file with an FFS filename specified by NameGuid. If the FFS file is found, a search \r
is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance \r
instances of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer.\r
Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size. \r
@param SectionType Indicates the FFS section type to search for within the FFS file specified by NameGuid.\r
@param SectionInstance Indicates which section instance within the FFS file specified by NameGuid to retrieve.\r
@param Buffer On output, a pointer to a callee allocated buffer containing the FFS file section that was found. \r
- Is it the caller's responsibility to free this buffer using FreePool().\r
+ It is the caller's responsibility to free this buffer using FreePool().\r
@param Size On output, a pointer to the size, in bytes, of Buffer.\r
\r
\r
@param SectionInstance Indicates which section instance to retrieve within the FFS file \r
that the currently executing module was loaded from.\r
@param Buffer On output, a pointer to a callee allocated buffer containing the FFS file section that was found. \r
- Is it the caller's responsibility to free this buffer using FreePool().\r
+ It is the caller's responsibility to free this buffer using FreePool().\r
@param Size On output, a pointer to the size, in bytes, of Buffer.\r
\r
@retval EFI_SUCCESS The specified FFS section was returned.\r
Provides library services to make PAL Calls.\r
\r
The PAL Library provides a service to make a PAL CALL. This service is identical\r
- in functionality to AsmPalCall() in the Itanium specific functions of the Base Library.\r
- The only difference is that the PAL Entry Point is not passed in. Implementations\r
+ in functionality to AsmPalCall() in the functions of the Base Library specific to Intel Itanium architecture.\r
+ The only difference is that the PAL Entry Point is not passed in. Implementations\r
of this library class must manage PAL Entry Point on their own. For example, a PEI\r
implementation can use a PPI to lookup the PAL Entry Point, and a DXE implementation\r
can contain a constructor to look up the PAL Entry Point from a HOB. This library class \r
- is only available on IPF.\r
+ is only available on Intel Itanium-based platforms.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials \r
may cause undefined results. For those parameters defined as reserved or some fields\r
defined as reserved must be zero filled or the invalid argument return value may be\r
returned or undefined result may occur during the execution of the procedure.\r
- This function is only available on IPF.\r
+ This function is only available on Intel Itanium-based platforms.\r
\r
@param Index The PAL procedure Index number.\r
@param Arg2 The 2nd parameter for PAL procedure calls.\r
/** @file\r
Provides library services to get and set Platform Configuration Database entries.\r
\r
- PCD Library Class provides PCD usage macro interface for all PCD types.\r
- It should be included at any module who use PCD. If module use dynamic/dynamicex\r
- PCD, module should be linked to PEIM/DXE library instance to access that PCD.\r
- If module uses PatchableInModule type PCD, also need library instance produce\r
- LibPatchPcdSetPtr() interface. For FeatureFlag/Fixed PCD, macro interface is\r
- translated to an variable or macro which is auto-generated by build tool in\r
+ PCD Library Class provides a PCD usage macro interface for all PCD types.\r
+ It should be included in any module that uses PCD. If a module uses dynamic/dynamicex\r
+ PCD, module should be linked to a PEIM/DXE library instance to access that PCD.\r
+ If a module uses PatchableInModule type PCD, it also needs the library instance to produce\r
+ LibPatchPcdSetPtr() interface. For FeatureFlag/Fixed PCD, the macro interface is\r
+ translated to n variable or macro that is auto-generated by build tool in\r
module's autogen.h/autogen.c.\r
The PcdGetXX(), PcdSetXX(), PcdToken(), and PcdGetNextTokenSpace() operations are \r
only available prior to ExitBootServices(). If access to PCD values are required \r
@param SkuId The SKU value that will be used when the PCD service retrieves and sets values\r
associated with a PCD token.\r
\r
- @return Return the SKU ID that just be set.\r
+ @return Return the SKU ID that was set.\r
\r
**/\r
UINTN\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The 8-bit value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
UINT8\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The 16-bit value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
UINT16\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The 32-bit value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
UINT32\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The 64-bit value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
UINT64\r
@param[in, out] SizeOfBuffer The size, in bytes, of Buffer.\r
@param[in] Buffer A pointer to the buffer to set.\r
\r
- @return Return the pointer for the buffer been set.\r
+ @return Return the pointer for the buffer that was set.\r
\r
**/\r
VOID *\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The boolean value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
BOOLEAN\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The 8-bit value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
UINT8\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The 16-bit value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
UINT16\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The 32-bit value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
UINT32\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The 64-bit value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
UINT64\r
@param[in, out] SizeOfBuffer The size, in bytes, of Buffer.\r
@param[in] Buffer A pointer to the buffer to set.\r
\r
- @return Return the pinter to the buffer been set.\r
+ @return Return the pointer to the buffer that was set.\r
\r
**/\r
VOID *\r
@param[in] TokenNumber The PCD token number to set a current value for.\r
@param[in] Value The Boolean value to set.\r
\r
- @return Return the value been set.\r
+ @return Return the value that was set.\r
\r
**/\r
BOOLEAN\r
/**\r
This notification function serves two purposes.\r
\r
- Firstly, it notifies the module which did the registration that the value of this\r
+ Firstly, it notifies the module that did the registration that the value of this\r
PCD token has been set.\r
- Secondly, it provides a mechanism for the module which did the registration to intercept\r
+ Secondly, it provides a mechanism for the module that did the registration to intercept\r
the set operation and override the value been set if necessary. After the invocation of\r
the callback function, TokenData will be used by PCD service PEIM or driver to modify th\r
internal data in PCD database. \r
@param[in, out] SizeOfBuffer A pointer to the size, in bytes, of Buffer.\r
@param[in] Buffer A pointer to the buffer to used to set the target variable.\r
\r
- @return Return the pointer to the buffer been set.\r
+ @return Return the pointer to the buffer that was set.\r
\r
**/\r
VOID *\r
Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.\r
\r
This library is identical to the PCI Library, except the access method for performing PCI \r
- configuration cycles must be though I/O ports 0xCF8 and 0xCFC. This library only allows \r
+ configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows \r
access to PCI Segment #0.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
Provides services to access PCI Configuration Space using the MMIO PCI Express window.\r
\r
This library is identical to the PCI Library, except the access method for performing PCI \r
- configuration cycles must be though the 256 MB PCI Express MMIO window whose base address\r
+ configuration cycles must be through the 256 MB PCI Express MMIO window whose base address\r
is defined by PcdPciExpressBaseAddress.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value, followed a bitwise OR with another 8-bit value.\r
+ value, followed by a bitwise OR with another 8-bit value.\r
\r
Reads the 8-bit PCI configuration register specified by Address, performs a\r
bitwise AND between the read result and the value specified by AndData,\r
Provides services to load and relocate a PE/COFF image.\r
\r
The PE/COFF Loader Library abstracts the implementation of a PE/COFF loader for\r
- IA-32, x86, IPF, and EBC processor types. The library functions are memory based \r
+ IA-32, x86, IPF, and EBC processor types. The library functions are memory-based \r
and can be ported easily to any environment.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation \r
of ImageContext as the relocation base address. The caller must allocate the relocation\r
fixup log buffer and fill in the FixupData field of ImageContext prior to calling this function.\r
\r
- The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, \r
+ The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, \r
ImageSize, DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, \r
DebugDirectoryEntryRva, EntryPoint, FixupDataSize, CodeView, PdbPointer, and FixupData of \r
the ImageContext structure must be valid prior to invoking this service.\r
specified by the ImageAddress and ImageSize fields of ImageContext. The caller must allocate\r
the load buffer and fill in the ImageAddress and ImageSize fields prior to calling this function.\r
The EntryPoint, FixupDataSize, CodeView, PdbPointer and HiiResourceData fields of ImageContext are computed.\r
- The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, ImageSize, \r
+ The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, ImageSize, \r
DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and DebugDirectoryEntryRva \r
fields of the ImageContext structure must be valid prior to invoking this service.\r
\r
This is the default implementation of a PE_COFF_LOADER_READ_FILE function \r
that assumes FileHandle pointer to the beginning of a PE/COFF image. \r
This function reads contents of the PE/COFF image that starts at the system memory \r
- address specified by FileHandle. The read operation copies ReadSize bytes from the \r
+ address specified by FileHandle. The read operation copies ReadSize bytes from the \r
PE/COFF image starting at byte offset FileOffset into the buffer specified by Buffer. \r
The size of the buffer actually read is returned in ReadSize.\r
\r
\r
This function reapplies relocation fixups to the PE/COFF image specified by ImageBase \r
and ImageSize so the image will execute correctly when the PE/COFF image is mapped \r
- to the address specified by VirtualImageBase. RelocationData must be identical \r
+ to the address specified by VirtualImageBase. RelocationData must be identical \r
to the FiuxupData buffer from the PE_COFF_LOADER_IMAGE_CONTEXT structure \r
after this PE/COFF image was relocated with PeCoffLoaderRelocateImage().\r
\r
module depends on. This include library instances that a module depends on directly and library\r
instances that a module depends on indirectly through other libraries. \r
This function is autogenerated by build tools and those build tools are responsible for collecting\r
- the set of library instances, determine which ones have constructors, and calling the library\r
- constructors in the proper order based upon each of the library instances own dependencies.\r
+ the set of library instances, determining which ones have constructors, and calling the library\r
+ constructors in the proper order based upon the dependencies of each of the library instances.\r
The PEI Core must call this function with a NULL FileHandle value as soon as the initial PEI\r
Services Table has been established.\r
\r
#define POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED 0x00000010\r
\r
/**\r
- Sends an 32-bit value to a POST card.\r
+ Sends a 32-bit value to a POST card.\r
\r
Sends the 32-bit value specified by Value to a POST card, and returns Value. \r
Some implementations of this library function may perform I/O operations \r
display the 32-bit value on the status reporting device.\r
\r
PostCode() must actively prevent recursion. If PostCode() is called while \r
- processing another any other Post Code Library function, then \r
+ processing another Post Code Library function, then \r
PostCode() must return Value immediately.\r
\r
@param Value The 32-bit value to write to the POST card.\r
\r
\r
/**\r
- Sends an 32-bit value to a POST and associated ASCII string.\r
+ Sends a 32-bit value to a POST and associated ASCII string.\r
\r
Sends the 32-bit value specified by Value to a POST card, and returns Value.\r
If Description is not NULL, then the ASCII string specified by Description is \r
\r
\r
/**\r
- Sends an 32-bit value to a POST card.\r
+ Sends a 32-bit value to a POST card.\r
\r
If POST codes are enabled in PcdPostCodeProperyMask, then call PostCode() \r
passing in Value. Value is returned.\r
#define POST_CODE(Value) PostCodeEnabled() ? PostCode(Value) : Value\r
\r
/**\r
- Sends an 32-bit value to a POST and associated ASCII string.\r
+ Sends a 32-bit value to a POST and associated ASCII string.\r
\r
If POST codes and POST code descriptions are enabled in \r
PcdPostCodeProperyMask, then call PostCodeWithDescription() passing in \r
defined as reserved or some fields defined as reserved must be\r
zero filled or the invalid argument return value may be returned\r
or undefined result may occur during the execution of the procedure.\r
- This function is only available on IPF.\r
+ This function is only available on Intel Itanium-based platforms.\r
\r
@param Index The SAL procedure Index number\r
@param Arg2 The 2nd parameter for SAL procedure calls\r
@param Buffer Pointer to the data buffer to store the data read from the serial device.\r
@param NumberOfBytes Number of bytes which will be read.\r
\r
- @retval 0 Read data failed, No data is to be read.\r
+ @retval 0 Read data failed, no data is to be read.\r
@retval >0 Actual number of bytes read from serial device.\r
\r
**/\r
\r
\r
/**\r
- Retrieves the architecture specific spin lock alignment requirements for\r
+ Retrieves the architecture-specific spin lock alignment requirements for\r
optimal spin lock performance.\r
\r
This function retrieves the spin lock alignment requirements for optimal\r
consumers of the spin lock synchronization functions to obtain optimal spin\r
lock performance.\r
\r
- @return The architecture specific spin lock alignment.\r
+ @return The architecture-specific spin lock alignment.\r
\r
**/\r
UINTN\r
\r
\r
/**\r
- Performs an atomic increment of an 32-bit unsigned integer.\r
+ Performs an atomic increment of a 32-bit unsigned integer.\r
\r
Performs an atomic increment of the 32-bit unsigned integer specified by\r
Value and returns the incremented value. The increment operation must be\r
\r
\r
/**\r
- Performs an atomic decrement of an 32-bit unsigned integer.\r
+ Performs an atomic decrement of a 32-bit unsigned integer.\r
\r
Performs an atomic decrement of the 32-bit unsigned integer specified by\r
Value and returns the decremented value. The decrement operation must be\r
@param SourceSize The size, in bytes, of the source buffer.\r
@param DestinationSize A pointer to the size, in bytes, of the uncompressed buffer\r
that will be generated when the compressed buffer specified\r
- by Source and SourceSize is decompressed..\r
+ by Source and SourceSize is decompressed.\r
@param ScratchSize A pointer to the size, in bytes, of the scratch buffer that\r
is required to decompress the compressed buffer specified \r
by Source and SourceSize.\r
based on a specified GUID.\r
\r
This function searches the list of configuration tables stored in the EFI System Table\r
- for a table with a GUID that matches TableGuid. If a match is found, then a pointer to\r
- the configuration table is returned in Table., and EFI_SUCCESS is returned. If a matching GUID\r
+ for a table with a GUID that matches TableGuid. If a match is found, then a pointer to\r
+ the configuration table is returned in Table, and EFI_SUCCESS is returned. If a matching GUID\r
is not found, then EFI_NOT_FOUND is returned.\r
If TableGuid is NULL, then ASSERT().\r
If Table is NULL, then ASSERT().\r
This library function abstracts validating a device path node.\r
Check the MEDIA_FW_VOL_FILEPATH_DEVICE_PATH data structure to see if it's valid. \r
If it is valid, then return the GUID file name from the device path node. Otherwise, \r
- return NULL. This device path changed in the DXE CIS version 0.92 in a non back ward \r
+ return NULL. This device path changed in the DXE CIS version 0.92 in a non backward \r
compatible way to not conflict with the UEFI 2.0 specification. This function abstracts \r
the differences from the caller.\r
If FvDevicePathNode is NULL, then ASSERT().\r
Unicode characters displayed, not including partial characters that may be clipped \r
by the right edge of the display. If the length of the formatted Unicode string is\r
greater than PcdUefiLibMaxPrintBufferSize, then at most the first \r
- PcdUefiLibMaxPrintBufferSize characters are printed.The EFI_HII_FONT_PROTOCOL\r
- StringToImage() service is used to convert the string to a bitmap using the glyphs \r
- registered with the HII database. No wrapping is performed, so any portions of the \r
- string the fall outside the active display region will not be displayed. Please see \r
- Section 27.2.6 of the UEFI Specification for a description of the supported string\r
- format including the set of control codes supported by the StringToImage() service.\r
+ PcdUefiLibMaxPrintBufferSize characters are printed. The EFI_HII_FONT_PROTOCOL\r
+ is used to convert the string to a bitmap using the glyphs registered with the \r
+ HII database. No wrapping is performed, so any portions of the string the fall\r
+ outside the active display region will not be displayed.\r
\r
If a graphics console device is not associated with the ConsoleOutputHandle \r
defined in the EFI_SYSTEM_TABLE then no string is printed, and 0 is returned.\r
ASCII characters displayed, not including partial characters that may be clipped \r
by the right edge of the display. If the length of the formatted ASCII string is\r
greater than PcdUefiLibMaxPrintBufferSize, then at most the first \r
- PcdUefiLibMaxPrintBufferSize characters are printed.The EFI_HII_FONT_PROTOCOL\r
- StringToImage() service is used to convert the string to a bitmap using the glyphs \r
- registered with the HII database. No wrapping is performed, so any portions of the \r
- string the fall outside the active display region will not be displayed. Please see \r
- Section 27.2.6 of the UEFI Specification for a description of the supported string\r
- format including the set of control codes supported by the StringToImage() service.\r
+ PcdUefiLibMaxPrintBufferSize characters are printed. The EFI_HII_FONT_PROTOCOL\r
+ is used to convert the string to a bitmap using the glyphs registered with the \r
+ HII database. No wrapping is performed, so any portions of the string the fall\r
+ outside the active display region will not be displayed.\r
\r
If a graphics console device is not associated with the ConsoleOutputHandle \r
defined in the EFI_SYSTEM_TABLE then no string is printed, and 0 is returned.\r
Initializes a driver by installing the Driver Binding Protocol together with the\r
optional Component Name, optional Driver Configure and optional Driver Diagnostic\r
Protocols onto the driver's DriverBindingHandle. If DriverBindingHandle is NULL,\r
- then the protocols are installed onto a newly created handle. DriverBindingHandle\r
+ then the protocols are installed onto a newly created handle. DriverBindingHandle\r
is typically the same as the driver's ImageHandle, but it can be different if the\r
driver produces multiple Driver Binding Protocols. \r
If DriverBinding is NULL, then ASSERT(). \r
information returned by GetTime() are the values that were last set via SetTime().\r
The GetTime() function should take approximately the same amount of time to read the time each\r
time it is called. All reported device capabilities are to be rounded up.\r
- During runtime, if a PC-AT CMOS device is present in the platform the caller must synchronize\r
+ During runtime, if a PC-AT CMOS device is present in the platform, the caller must synchronize\r
access to the device before calling GetTime().\r
\r
@param Time A pointer to storage to receive a snapshot of the current time.\r
to loop based on the current time. For example, if the device does not support a hardware reset\r
for the sub-resolution time, the code is not to implement the feature by waiting for the time to\r
wrap.\r
- During runtime, if a PC-AT CMOS device is present in the platform the caller must synchronize\r
+ During runtime, if a PC-AT CMOS device is present in the platform, the caller must synchronize\r
access to the device before calling SetTime().\r
\r
@param Time A pointer to the current time. Type EFI_TIME is defined in the GetTime()\r
This service is a wrapper for the UEFI Runtime Service GetVariable().\r
\r
Each vendor may create and manage its own variables without the risk of name conflicts by\r
- using a unique VendorGuid. When a variable is set its Attributes are supplied to indicate\r
+ using a unique VendorGuid. When a variable is set, its Attributes are supplied to indicate\r
how the data variable should be stored and maintained by the system. The attributes affect\r
when the variable may be accessed and volatility of the data. Any attempts to access a variable\r
that does not have the attribute set for runtime access will yield the EFI_NOT_FOUND error.\r
Variables are stored by the firmware and may maintain their values across power cycles. Each vendor\r
may create and manage its own variables without the risk of name conflicts by using a unique VendorGuid.\r
\r
- @param VariableName the name of the vendor's variable, it's a\r
+ @param VariableName the name of the vendor's variable, as a\r
Null-Terminated Unicode String\r
@param VendorGuid Unify identifier for vendor.\r
@param Attributes Point to memory location to return the attributes of variable. If the point\r
@param ListHead Head of linked list to convert.\r
\r
@retval EFI_SUCCESS Success to execute the function.\r
- @retval !EFI_SUCCESS Failed to e3xecute the function.\r
+ @retval !EFI_SUCCESS Failed to execute the function.\r
\r
**/\r
EFI_STATUS\r
/** @file\r
- Provides the functions to submit Scsi commands defined in SCSI-2 specification for scsi device.\r
+ Provides the functions to submit Scsi commands defined in SCSI-2 specification for SCSI devices.\r
\r
This library class provides the functions to submit SCSI commands defined in SCSI-2 specification\r
for hard drive, CD and DVD devices that are the most common SCSI boot targets used by UEFI platforms.\r
/** @file\r
- Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec\r
- and the standard requests defined in Usb 1.1 spec.\r
+ Provides most USB APIs to support the Hid requests defined in USB Hid 1.1 spec\r
+ and the standard requests defined in USB 1.1 spec.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
#define __USB_DXE_LIB_H__\r
\r
#include <Protocol/UsbIo.h>\r
+#include <IndustryStandard/Usb.h>\r
\r
/**\r
Get the descriptor of the specified USB HID interface.\r
\r
- Submit a USB get HID descriptor request for the USB device specified by UsbIo\r
- and Interface and return the HID descriptor in HidDescriptor.\r
+ Submit a UsbGetHidDescriptor() request for the USB device specified by UsbIo\r
+ and Interface, and return the HID descriptor in HidDescriptor.\r
If UsbIo is NULL, then ASSERT().\r
If HidDescriptor is NULL, then ASSERT().\r
\r
Get the report descriptor of the specified USB HID interface.\r
\r
Submit a USB get HID report descriptor request for the USB device specified by\r
- UsbIo and Interface and return the report descriptor in DescriptorBuffer.\r
+ UsbIo and Interface, and return the report descriptor in DescriptorBuffer.\r
If UsbIo is NULL, then ASSERT().\r
If DescriptorBuffer is NULL, then ASSERT().\r
\r
Get the HID protocol of the specified USB HID interface.\r
\r
Submit a USB get HID protocol request for the USB device specified by UsbIo\r
- and Interface and return the protocol retrieved in Protocol.\r
+ and Interface, and return the protocol retrieved in Protocol.\r
If UsbIo is NULL, then ASSERT().\r
If Protocol is NULL, then ASSERT().\r
\r
Set the HID protocol of the specified USB HID interface.\r
\r
Submit a USB set HID protocol request for the USB device specified by UsbIo\r
- and Interface and set the protocol to the value specified by Protocol.\r
+ and Interface, and set the protocol to the value specified by Protocol.\r
If UsbIo is NULL, then ASSERT().\r
\r
@param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.\r
Get the status of the specified device.\r
\r
Submit a USB device get status request for the USB device specified by UsbIo,\r
- Recipient, and Target and place the result in the buffer specified by DeviceStatus.\r
+ Recipient, and Target, and place the result in the buffer specified by DeviceStatus.\r
The status of the transfer is returned in Status.\r
If UsbIo is NULL, then ASSERT().\r
If DeviceStatus is NULL, then ASSERT().\r
/**\r
Retrieves a 16-bit value for a given PCD token.\r
\r
- Retrieves the current 16-bits value for a PCD token number. \r
+ Retrieves the current 16-bit value for a PCD token number. \r
If the TokenNumber is invalid, the results are unpredictable.\r
\r
@param[in] TokenNumber The PCD token number. \r
/**\r
Retrieves a 32-bit value for a given PCD token.\r
\r
- Retrieves the current 32-bits value for a PCD token number. \r
+ Retrieves the current 32-bit value for a PCD token number. \r
If the TokenNumber is invalid, the results are unpredictable.\r
\r
@param[in] TokenNumber The PCD token number. \r
/**\r
Retrieves a 64-bit value for a given PCD token.\r
\r
- Retrieves the current 64-bits value for a PCD token number. \r
+ Retrieves the current 64-bit value for a PCD token number. \r
If the TokenNumber is invalid, the results are unpredictable.\r
\r
@param[in] TokenNumber The PCD token number. \r
/** @file\r
This file declares Status Code PPI.\r
- This ppi provides service that allows PEIMs to report status codes.\r
+ This ppi provides a service that allows PEIMs to report status codes.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
//\r
\r
///\r
-/// This PPI provides the sevice to report status code.\r
+/// This PPI provides the service to report status code.\r
/// There can be only one instance of this service in the system.\r
///\r
typedef struct {\r
///\r
/// This key is affected by the caps lock so that if a keyboard driver\r
/// would need to disambiguate between a key which had a "1" defined\r
-/// versus a "a" character. Having this bit turned on would tell\r
+/// versus an "a" character. Having this bit turned on would tell\r
/// the keyboard driver to use the appropriate shifted state or not.\r
///\r
#define EFI_AFFECTED_BY_CAPS_LOCK 0x0002\r
//\r
// Keys that have multiple control functions based on modifier\r
// settings are handled in the keyboard driver implementation.\r
-// For instance PRINT_KEY might have a modifier held down and\r
+// For instance, PRINT_KEY might have a modifier held down and\r
// is still a nonprinting character, but might have an alternate\r
// control function like SYSREQUEST\r
//\r
///\r
EfiResetWarm,\r
///\r
- /// Used to induce en entry into power state equivalent to the ACPI G2/S5 or G3\r
+ /// Used to induce an entry into the power state equivalent to the ACPI G2/S5 or G3\r
/// state. If the system does not support this reset type, then when the system\r
/// is rebooted, it should exhibit the EfiResetCold attributes.\r
///\r
/** @file\r
- Processor or Compiler specific defines and types x64 (Intel(r) EM64T, AMD64).\r
+ Processor or Compiler specific defines and types x64 (Intel 64, AMD64).\r
\r
Copyright (c) 2006 - 2009, Intel Corporation<BR> \r
All rights reserved. This program and the accompanying materials \r
#endif\r
\r
//\r
-// Macros for GNU assembly code\r
+// For symbol name in GNU assembly code, an extra "_" is necessary\r
//\r
#if defined(__GNUC__)\r
#if defined(linux)\r
#define ASM_PFX(name) name\r
#else\r
#define ASM_PFX(name) _##name\r
- #endif \r
- ///\r
- /// For GNU assembly code, .global or .globl can declare global symbols.\r
- /// Define this macro to unify the usage.\r
- ///\r
- #define ASM_GLOBAL .globl\r
+ #endif \r
#endif\r
\r
/**\r
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