ArmPlatformPkg: Unify the Secure and Normal FD and FV PCD naming

With this change, we now have these following PCDs values to define the
location of the Secure and Normal firmwares:
- gArmTokenSpaceGuid.PcdSecureFd(BaseAddress|Size)
- gArmTokenSpaceGuid.PcdSecureFv(BaseAddress|Size)
- gArmTokenSpaceGuid.PcdNormalFd(BaseAddress|Size)
- gArmTokenSpaceGuid.PcdNormalFv(BaseAddress|Size)

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11806 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 0357810c56ad26ed0d8b71340298ea766e340256..9f4673c3ba5c31b08af6a2683472d6a18715ec4b 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -87,12 +87,16 @@
   #\r
   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r
   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
+  gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F\r
+  gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
 \r
   #\r
   # ARM Normal (or Non Secure) Firmware PCDs\r
   #\r
   gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0|UINT32|0x0000002B\r
   gArmTokenSpaceGuid.PcdNormalFdSize|0|UINT32|0x0000002C\r
+  gArmTokenSpaceGuid.PcdNormalFvBaseAddress|0|UINT32|0x0000002D\r
+  gArmTokenSpaceGuid.PcdNormalFvSize|0|UINT32|0x0000002E\r
 \r
   # System Memory (DRAM): These PCDs define the region of in-built system memory\r
   # Some platforms can get DRAM extensions, these additional regions will be declared\r

diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
index 1439116f71962c5fcd48c2d44b39de79d300b82e..6fbea18b29ae1ec299645b8b7ea23ac348b46211 100644 (file)
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
@@ -340,10 +340,6 @@
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000  # Top of SEC Stack for Normal World\r
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000     # Size of SEC Stack for Normal World\r
 \r
-  # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize\r
-  gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000       # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase\r
-  gArmTokenSpaceGuid.PcdNormalFdSize|0x00100000              # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
-  \r
   # System Memory (256MB) \r
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0x70000000\r
   gArmTokenSpaceGuid.PcdSystemMemorySize|0x10000000\r

diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
index 2811f93a51a6eae5e801a2b543397d3a0e191e38..dcd75e000faf1d2e6b76284875c40b9a6d99d65e 100644 (file)
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
@@ -344,10 +344,6 @@
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000     # Top of SEC Stack for Normal World
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000        # Stack for each of the 4 CPU cores
 
-  # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
-  gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000       # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
-  gArmTokenSpaceGuid.PcdNormalFdSize|0x00100000              # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
-  
   # System Memory (256MB) 
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0x70000000
   gArmTokenSpaceGuid.PcdSystemMemorySize|0x10000000

diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf
index 1ee92ea6c2b80325ccf63b49d150378e3972230b..6e639fc8a06a87cb9a27ae2b090c955d29255d3d 100644 (file)
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf
@@ -27,8 +27,8 @@
 
 
 [FD.ArmRealViewEb_EFI]
-BaseAddress   = 0x40000000  # The base address of the FLASH Device.
-Size          = 0x00200000  # The size in bytes of the FLASH Device
+BaseAddress   = 0x40000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress
+Size          = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize
 ErasePolarity = 1
 BlockSize     = 0x00010000
 NumBlocks     = 0x20
@@ -50,11 +50,11 @@ NumBlocks     = 0x20
 ################################################################################
 
 0x00000000|0x00050000
-gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize
 FV = FVMAIN_SEC
 
 0x00050000|0x00100000
-gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvSize
 FV = FVMAIN_COMPACT
 
 ################################################################################

diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf
index 5856d51fcf8b89be3db21ccad713101ad827cd30..763437726253f77ffcbdc9b5c063a3468a00f1a3 100644 (file)
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf
@@ -27,8 +27,8 @@
 \r
 \r
 [FD.ArmRealViewEb_EFI]\r
-BaseAddress   = 0x40000000  # The base address of the FLASH Device.\r
-Size          = 0x00200000  # The size in bytes of the FLASH Device\r
+BaseAddress   = 0x40000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
+Size          = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize\r
 ErasePolarity = 1\r
 BlockSize     = 0x00010000\r
 NumBlocks     = 0x20\r
@@ -50,11 +50,11 @@ NumBlocks     = 0x20
 ################################################################################\r
 \r
 0x00000000|0x00050000\r
-gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize\r
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize\r
 FV = FVMAIN_SEC\r
 \r
 0x00050000|0x00100000\r
-gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
+gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvSize\r
 FV = FVMAIN_COMPACT\r
 \r
 ################################################################################\r

diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf
index b344217523a35472bbb1ec076ff638b30634fce2..55e4e073ea3b90879c1294b3f5fbac2bd956df3a 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf
@@ -27,10 +27,10 @@
 
 [FD.Sec_ArmVExpress_EFI]
 BaseAddress   = 0x44000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress  #The base address of the Secure FLASH Device.
-Size          = 0x00200000|gArmTokenSpaceGuid.PcdSecureFdSize         #The size in bytes of the Secure FLASH Device
+Size          = 0x00080000|gArmTokenSpaceGuid.PcdSecureFdSize         #The size in bytes of the Secure FLASH Device
 ErasePolarity = 1
 BlockSize     = 0x00001000
-NumBlocks     = 0x200
+NumBlocks     = 0x80
 
 ################################################################################
 #
@@ -48,8 +48,8 @@ NumBlocks     = 0x200
 #
 ################################################################################
 
-0x00000000|0x00200000
-gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize
+0x00000000|0x00080000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize
 FV = FVMAIN_SEC
 
 
@@ -83,7 +83,7 @@ NumBlocks     = 0x200
 ################################################################################
 
 0x00000000|0x00200000
-gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvBaseSize
 FV = FVMAIN_COMPACT
 
 
@@ -147,11 +147,10 @@ READ_LOCK_STATUS   = TRUE
   INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
   INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
   INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
-  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
   INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
   INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
   INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf

diff --git a/ArmPlatformPkg/PlatformPei/PlatformPei.c b/ArmPlatformPkg/PlatformPei/PlatformPei.c
index f3e96782f1e66a355f2e897096385ebfd853c242..4c0ae2141dce66d2601f2f7f3786c4b85f8bcb89 100644 (file)
--- a/ArmPlatformPkg/PlatformPei/PlatformPei.c
+++ b/ArmPlatformPkg/PlatformPei/PlatformPei.c
@@ -78,7 +78,7 @@ Returns:
 \r
   BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
   \r
-  BuildFvHob (FixedPcdGet32(PcdFlashFvMainBase), FixedPcdGet32(PcdFlashFvMainSize));\r
+  BuildFvHob (PcdGet32(PcdNormalFvBaseAddress), PcdGet32(PcdNormalFvSize));\r
   \r
   BootMode  = ArmPlatformGetBootMode ();\r
   Status    = (**PeiServices).SetBootMode (PeiServices, (UINT8) BootMode);\r

diff --git a/ArmPlatformPkg/PlatformPei/PlatformPei.inf b/ArmPlatformPkg/PlatformPei/PlatformPei.inf
index c35889a9688f86133d0a7c6a8010d71adda847ec..92cf3aa4dc55abb5cc81edfaac7776d2875b071b 100644 (file)
--- a/ArmPlatformPkg/PlatformPei/PlatformPei.inf
+++ b/ArmPlatformPkg/PlatformPei/PlatformPei.inf
@@ -47,10 +47,12 @@
   gEfiPeiBootInRecoveryModePpiGuid              # PPI SOMETIMES_PRODUCED\r
 \r
 [FixedPcd]\r
-  gArmTokenSpaceGuid.PcdNormalFdBaseAddress  # The base address of the FLASH Device.\r
-  gArmTokenSpaceGuid.PcdNormalFdSize         # The size in bytes of the FLASH Device\r
-  gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase\r
-  gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
+  gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
+  gArmTokenSpaceGuid.PcdNormalFdSize\r
+  \r
+  gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
+  gArmTokenSpaceGuid.PcdNormalFvSize\r
+  \r
   gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize\r
   gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize\r
   \r

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 2a4ee61954557096555ea2265c4d45a1df4b764b..2e6477d550c1b5731e6379141843bf4ec3b4ab3c 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -77,8 +77,8 @@ VOID primary_main (
        // Note also:  HOBs (pei temp ram) MUST be above stack\r
        //\r
        SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
-    SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFdBaseAddress);\r
-    SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFdSize);\r
+    SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
+    SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
        SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
        SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
        SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r

diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
index ac7b16a5c6d77addf8953cd7d10732bc3a48c150..15e7629c864a3da78145af0de9a76529f4015988 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
@@ -39,8 +39,8 @@ VOID primary_main (
        // Note also:  HOBs (pei temp ram) MUST be above stack\r
        //\r
        SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
-    SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFdBaseAddress);\r
-    SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFdSize);\r
+    SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
+    SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
        SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
        SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
        SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
index ffa4a46da988e7a8659af37b2a6153193f08e9f8..d61a15bded350171736fc2b733e31ba872bbf4ad 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
@@ -35,8 +35,8 @@ ASM_PFX(_ModuleEntryPoint):
 
 _SetupStack:
   # Setup Stack for the 4 CPU cores
-  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase) ,r1)
-  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize) ,r2)
+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase), r1)
+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize), r2)
   
   mov     r3,r0         @ r3 = core_id
   mul     r3,r3,r2      @ r3 = core_id * stack_size = offset from the stack base
@@ -55,7 +55,7 @@ _AllocateGlobalPeiVariables:
 
 _PrepareArguments:
   # The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
-  LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
+  LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2)
   add   r2, r2, #4
   ldr   r1, [r2]
 

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
index 231c14e36bae2c73a0e346dee0073e74fff9bc34..e214ed3744f755372abecc39d83b823d6430840e 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
@@ -53,7 +53,7 @@ _AllocateGlobalPeiVariables
 \r
 _PrepareArguments\r
   // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
-  LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)\r
+  LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2)\r
   add   r2, r2, #4\r
   ldr   r1, [r2]\r
 \r

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
index 4ca81f5a406c298fb46fd52cc2e2c9e4e3773eff..917da5dca080de886433bd854e2ad0689ff6f5c5 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
@@ -53,8 +53,8 @@
   gArmPlatformTokenSpaceGuid.PcdStandalone\r
   \r
 [FixedPcd]\r
-  gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
-  gArmTokenSpaceGuid.PcdNormalFdSize\r
+  gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
+  gArmTokenSpaceGuid.PcdNormalFvSize\r
 \r
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase\r
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize\r

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
index c14e7353c6fb30533b05dfd33ced7054e456c439..aeaa0db8ad6e24d42f1ba1b3c4ce4a0369fb1171 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
@@ -42,7 +42,6 @@
   IoLib\r
   ArmLib\r
   ArmPlatformLib\r
-  SerialPortLib\r
 \r
 [Ppis]\r
   gEfiTemporaryRamSupportPpiGuid\r
@@ -51,8 +50,8 @@
   gArmPlatformTokenSpaceGuid.PcdStandalone\r
   \r
 [FixedPcd]\r
-  gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
-  gArmTokenSpaceGuid.PcdNormalFdSize\r
+  gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
+  gArmTokenSpaceGuid.PcdNormalFvSize\r
 \r
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase\r
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize\r

diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index b8e52255207af7d7db171e40d5d916f6e37eccbc..64cf0f0d7ebe5aad99a564509dc5e85379aaf0be 100644 (file)
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -121,18 +121,18 @@ CEntryPoint (
     // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
     if (FeaturePcdGet(PcdSkipPeiCore) || !FeaturePcdGet(PcdStandalone)) {
       // Initialize system memory (DRAM)
-      ArmPlatformInitializeSystemMemory();
+      ArmPlatformInitializeSystemMemory ();
     }
 
     // Some platform can change their physical memory mapping
-    ArmPlatformBootRemapping();
+    ArmPlatformBootRemapping ();
   }
 
   // Test if Trustzone is supported on this platform
   if (ArmPlatformTrustzoneSupported()) {
     if (FixedPcdGet32(PcdMPCoreSupport)) {
       // Setup SMP in Non Secure world
-      ArmSetupSmpNonSecure(CoreId);
+      ArmSetupSmpNonSecure (CoreId);
     }
 
     // Enter Monitor Mode
@@ -206,7 +206,7 @@ CEntryPoint (
   // If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
   if (FeaturePcdGet(PcdStandalone) == FALSE) {
     if (CoreId == ARM_PRIMARY_CORE) {
-      UINTN*   StartAddress = (UINTN*)PcdGet32(PcdNormalFdBaseAddress);
+      UINTN*   StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
 
       // Patch the DRAM to make an infinite loop at the start address
       *StartAddress = 0xEAFFFFFE; // opcode for while(1)
@@ -215,7 +215,7 @@ CEntryPoint (
       SerialPortWrite ((UINT8 *) Buffer, CharCount);
 
       // To enter into Non Secure state, we need to make a return from exception
-      return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
+      return_from_exception(PcdGet32(PcdNormalFvBaseAddress));
     } else {
       // When the primary core is stopped by the hardware debugger to copy the firmware
       // into DRAM. The secondary cores are still running. As soon as the first bytes of
@@ -229,7 +229,7 @@ CEntryPoint (
     }
   } else {
     // To enter into Non Secure state, we need to make a return from exception
-    return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
+    return_from_exception(PcdGet32(PcdNormalFvBaseAddress));
   }
   //-------------------- Non Secure Mode ---------------------
 
@@ -247,7 +247,7 @@ NonSecureWaitForFirmware (
   VOID (*secondary_start)(VOID);
 
   // The secondary cores will execute the firmware once wake from WFI.
-  secondary_start = (VOID (*)())PcdGet32(PcdNormalFdBaseAddress);
+  secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress);
 
   ArmCallWFI();
 

diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf
index 38bd8b9be30d7f9a9ffdd1b568ace5d0360bef45..d36fc0c777d697655b415e9d560177cc88eccfee 100644 (file)
--- a/ArmPlatformPkg/Sec/Sec.inf
+++ b/ArmPlatformPkg/Sec/Sec.inf
@@ -52,7 +52,7 @@
   gArmTokenSpaceGuid.PcdVFPEnabled
   gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
   
-  gArmTokenSpaceGuid.PcdNormalFdBaseAddress
+  gArmTokenSpaceGuid.PcdNormalFvBaseAddress
   
   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize