PLATFORM_VERSION = 0.1\r
DSC_SPECIFICATION = 0x00010005\r
OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)\r
- SUPPORTED_ARCHITECTURES = ARM\r
+ SUPPORTED_ARCHITECTURES = ARM|AARCH64\r
BUILD_TARGETS = DEBUG|RELEASE\r
SKUID_IDENTIFIER = DEFAULT\r
FLASH_DEFINITION = ArmPlatformPkg/ArmPlatformPkg-2ndstage.fdf\r
\r
[LibraryClasses.common]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf\r
ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf\r
\r
!if $(TARGET) == RELEASE\r
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf\r
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf\r
\r
+[LibraryClasses.ARM]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf\r
+\r
+[LibraryClasses.AARCH64]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf\r
+\r
[LibraryClasses.common.SEC]\r
ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf\r
\r
#/** @file\r
#\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
\r
- # Stack for CPU Cores in Secure Monitor Mode\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
-\r
# Stack for CPU Cores in Non Secure Mode\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
\r
gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
- \r
+\r
+[PcdsFixedAtBuild.ARM]\r
+ # Stack for CPU Cores in Secure Monitor Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
+\r
+[PcdsFixedAtBuild.AARCH64]\r
+ # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
+ # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
+ # and PcdCPUCoreSecSecondaryStackSize\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
+\r
PLATFORM_VERSION = 0.1\r
DSC_SPECIFICATION = 0x00010005\r
OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)\r
- SUPPORTED_ARCHITECTURES = ARM\r
+ SUPPORTED_ARCHITECTURES = ARM|AARCH64\r
BUILD_TARGETS = DEBUG|RELEASE\r
SKUID_IDENTIFIER = DEFAULT\r
FLASH_DEFINITION = ArmPlatformPkg/ArmPlatformPkg.fdf\r
\r
[LibraryClasses.common]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf\r
ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf\r
\r
!if $(TARGET) == RELEASE\r
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf\r
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf\r
\r
+[LibraryClasses.ARM]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf\r
+\r
+[LibraryClasses.AARCH64]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf\r
+\r
[LibraryClasses.common.SEC]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
ArmPlatformSecLib|ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullSec.inf\r
ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullSec.inf\r
ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf\r
DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf\r
DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf\r
\r
+[LibraryClasses.ARM.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
+\r
+[LibraryClasses.AARCH64.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf\r
+\r
[LibraryClasses.common.PEI_CORE]\r
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
#\r
NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r
\r
+[LibraryClasses.AARCH64]\r
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r
+\r
[BuildOptions]\r
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7\r
\r
--- /dev/null
+//\r
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Library/ArmLib.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+\r
+ASM_PFX(ArmPlatformPeiBootAction):\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 4) + CoreId\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and x1, x0, #ARM_CORE_MASK\r
+ and x0, x0, #ARM_CLUSTER_MASK\r
+ add x0, x1, x0, LSR #6\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r
+ ldrh w0, [x0]\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1)\r
+ ldrh w1, [x1]\r
+ and x0, x0, x1\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x1)\r
+ ldrh w1, [x1]\r
+ cmp w0, w1\r
+ mov x0, #1\r
+ mov x1, #0\r
+ csel x0, x0, x1, eq\r
+ ret\r
Arm/ArmPlatformHelper.S | GCC\r
Arm/ArmPlatformHelper.asm | RVCT\r
\r
+[Sources.AArch64]\r
+ AArch64/ArmPlatformHelper.S | GCC\r
+\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdSystemMemoryBase\r
gArmTokenSpaceGuid.PcdSystemMemorySize\r
Arm/ArmPlatformHelper.S | GCC\r
Arm/ArmPlatformHelper.asm | RVCT\r
\r
+[Sources.AArch64]\r
+ AArch64/ArmPlatformHelper.S | GCC\r
+\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdSystemMemoryBase\r
gArmTokenSpaceGuid.PcdSystemMemorySize\r
--- /dev/null
+//\r
+// Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
+GCC_ASM_EXPORT(ArmSecMpCoreSecondariesWrite)\r
+GCC_ASM_EXPORT(ArmSecMpCoreSecondariesRead)\r
+\r
+/**\r
+ Call at the beginning of the platform boot up\r
+\r
+ This function allows the firmware platform to do extra actions at the early\r
+ stage of the platform power up.\r
+\r
+ Note: This function must be implemented in assembler as there is no stack set up yet\r
+\r
+**/\r
+ASM_PFX(ArmPlatformSecBootAction):\r
+ ret\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ASM_PFX(ArmPlatformSecBootMemoryInit):\r
+ // The SMC does not need to be initialized for RTSM\r
+ ret\r
+\r
+/* Write the flag register used to start Secondary cores */\r
+ASM_PFX(ArmSecMpCoreSecondariesWrite):\r
+ // Write to the CPU Mailbox\r
+ ret\r
+\r
+\r
+/* Read the flag register used to start Secondary cores */\r
+ASM_PFX(ArmSecMpCoreSecondariesRead):\r
+ // Return the value from the CPU Mailbox\r
+ mov x0, #0\r
+ ret\r
Arm/ArmPlatformLibNullBoot.asm | RVCT\r
Arm/ArmPlatformLibNullBoot.S | GCC\r
\r
+[Sources.AARCH64]\r
+ AArch64/ArmPlatformLibNullBoot.S | GCC\r
+\r
+\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
\r
--- /dev/null
+//\r
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformStackSet)\r
+GCC_ASM_EXPORT(ArmPlatformStackSetPrimary)\r
+GCC_ASM_EXPORT(ArmPlatformStackSetSecondary)\r
+\r
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_IMPORT(ArmPlatformGetPrimaryCoreMpId)\r
+\r
+GCC_ASM_IMPORT(gPcd_FixedAtBuild_PcdCoreCount)\r
+\r
+//VOID\r
+//ArmPlatformStackSet (\r
+// IN UINTN StackBase,\r
+// IN UINTN MpId,\r
+// IN UINTN PrimaryStackSize,\r
+// IN UINTN SecondaryStackSize\r
+// );\r
+ASM_PFX(ArmPlatformStackSet):\r
+ // Save parameters\r
+ mov x6, x3\r
+ mov x5, x2\r
+ mov x4, x1\r
+ mov x3, x0\r
+\r
+ // Save the Link register\r
+ mov x7, x30\r
+\r
+ // Identify Stack\r
+ mov x0, x1\r
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
+ cmp x0, #1\r
+\r
+ // Restore parameters\r
+ mov x0, x3\r
+ mov x1, x4\r
+ mov x2, x5\r
+ mov x3, x6\r
+\r
+ // Restore the Link register\r
+ mov x30, x7\r
+\r
+ // Should be ASM_PFX(ArmPlatformStackSetPrimary) but generate linker error 'unsupported ELF EM_AARCH64'\r
+ b.eq ArmPlatformStackSetPrimaryL\r
+ // Should be ASM_PFX(ArmPlatformStackSetSecondary) but generate linker error 'unsupported ELF EM_AARCH64'\r
+ b.ne ArmPlatformStackSetSecondaryL\r
+\r
+//VOID\r
+//ArmPlatformStackSetPrimary (\r
+// IN UINTN StackBase,\r
+// IN UINTN MpId,\r
+// IN UINTN PrimaryStackSize,\r
+// IN UINTN SecondaryStackSize\r
+// );\r
+ArmPlatformStackSetPrimaryL:\r
+ASM_PFX(ArmPlatformStackSetPrimary):\r
+ // Save the Link register\r
+ mov x4, x30\r
+\r
+ // Add stack of primary stack to StackBase\r
+ add x0, x0, x2\r
+\r
+ // Compute SecondaryCoresCount * SecondaryCoreStackSize\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, x1)\r
+ ldr w1, [x1]\r
+ sub x1, x1, #1\r
+ mul x3, x3, x1\r
+\r
+ // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize))\r
+ add sp, x0, x3\r
+\r
+ br x4\r
+\r
+//VOID\r
+//ArmPlatformStackSetSecondary (\r
+// IN UINTN StackBase,\r
+// IN UINTN MpId,\r
+// IN UINTN PrimaryStackSize,\r
+// IN UINTN SecondaryStackSize\r
+// );\r
+ArmPlatformStackSetSecondaryL:\r
+ASM_PFX(ArmPlatformStackSetSecondary):\r
+ // Save the Link register\r
+ mov x4, x30\r
+ mov sp, x0\r
+\r
+ // Get Core Position\r
+ mov x0, x1\r
+ bl ASM_PFX(ArmPlatformGetCorePosition)\r
+ mov x5, x0\r
+\r
+ // Get Primary Core Position\r
+ bl ASM_PFX(ArmPlatformGetPrimaryCoreMpId)\r
+ bl ASM_PFX(ArmPlatformGetCorePosition)\r
+\r
+ // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1)\r
+ cmp x5, x0\r
+ b.ls 1f\r
+ // Decrement the position if after the primary core\r
+ sub x5, x5, #1\r
+1:\r
+ add x5, x5, #1\r
+\r
+ // Compute top of the secondary stack\r
+ mul x3, x3, x5\r
+\r
+ // Set stack\r
+ add sp, sp, x3\r
+\r
+ br x4\r
//\r
-// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// Identify Stack\r
// Mask for ClusterId|CoreId\r
LoadConstantToReg (0xFFFF, r4)\r
- and r1, r1, r4\r
+ and r1, r1, r4\r
// Is it the Primary Core ?\r
LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r4)\r
- ldr r4, [r4]\r
+ ldr r4, [r4]\r
cmp r1, r4\r
- beq ASM_PFX(ArmPlatformStackSetPrimary)\r
+ beq ASM_PFX(ArmPlatformStackSetPrimary)\r
bne ASM_PFX(ArmPlatformStackSetSecondary)\r
\r
//VOID\r
// IN UINTN SecondaryStackSize\r
// );\r
ASM_PFX(ArmPlatformStackSetPrimary):\r
- mov r4, lr\r
+ mov r4, lr\r
\r
// Add stack of primary stack to StackBase\r
- add r0, r0, r2\r
+ add r0, r0, r2\r
\r
// Compute SecondaryCoresCount * SecondaryCoreStackSize\r
LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, r1)\r
- ldr r1, [r1]\r
- sub r1, #1\r
- mul r3, r3, r1\r
+ ldr r1, [r1]\r
+ sub r1, #1\r
+ mul r3, r3, r1\r
\r
// Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize))\r
- add sp, r0, r3\r
+ add sp, r0, r3\r
\r
bx r4\r
\r
// IN UINTN SecondaryStackSize\r
// );\r
ASM_PFX(ArmPlatformStackSetSecondary):\r
- mov r4, lr\r
+ mov r4, lr\r
mov sp, r0\r
\r
// Get Core Position\r
- mov r0, r1\r
+ mov r0, r1\r
bl ASM_PFX(ArmPlatformGetCorePosition)\r
- mov r5, r0\r
+ mov r5, r0\r
\r
// Get Primary Core Position\r
LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
- ldr r0, [r0]\r
+ ldr r0, [r0]\r
bl ASM_PFX(ArmPlatformGetCorePosition)\r
\r
// Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1)\r
- cmp r5, r0\r
+ cmp r5, r0\r
subhi r5, r5, #1\r
- add r5, r5, #1\r
+ add r5, r5, #1\r
\r
// Compute top of the secondary stack\r
- mul r3, r3, r5\r
+ mul r3, r3, r5\r
\r
// Set stack\r
- add sp, sp, r3\r
+ add sp, sp, r3\r
\r
bx r4\r
\r
Arm/ArmPlatformStackLib.asm | RVCT\r
Arm/ArmPlatformStackLib.S | GCC\r
\r
+[Sources.AARCH64]\r
+ AArch64/ArmPlatformStackLib.S | GCC\r
+\r
[FixedPcd]\r
gArmPlatformTokenSpaceGuid.PcdCoreCount\r
\r
--- /dev/null
+/** @file\r
+* Main file supporting the Monitor World on ARM PLatforms\r
+*\r
+* Copyright (c) 2012-2013, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+VOID\r
+ArmSecureMonitorWorldInitialize (\r
+ VOID\r
+ )\r
+{\r
+ // Do not touch the EL3 Exception Vector Table Register.\r
+ // The default default DebugAgentLib could have already set its own vector\r
+ // into EL3 to catch abort exceptions.\r
+}\r
--- /dev/null
+/** @file\r
+* Main file supporting the Monitor World on ARM PLatforms\r
+*\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmTrustedMonitorLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)\r
+\r
+VOID\r
+MonitorVectorTable (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+ArmSecureMonitorWorldInitialize (\r
+ VOID\r
+ )\r
+{\r
+ // Ensure the Monitor Table is 32bit aligned\r
+ ASSERT (((UINTN)&MonitorVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+\r
+ // Write the Monitor Mode Vector Table Address\r
+ ArmWriteMVBar ((UINTN) &MonitorVectorTable);\r
+}\r
+\r
+++ /dev/null
-/** @file\r
-* Main file supporting the Monitor World on ARM PLatforms\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmTrustedMonitorLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)\r
-\r
-VOID\r
-MonitorVectorTable (\r
- VOID\r
- );\r
-\r
-VOID\r
-ArmSecureMonitorWorldInitialize (\r
- VOID\r
- )\r
-{\r
- // Ensure the Monitor Table is 32bit aligned\r
- ASSERT (((UINTN)&MonitorVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
-\r
- // Write the Monitor Mode Vector Table Address\r
- ArmWriteMVBar ((UINTN) &MonitorVectorTable);\r
-}\r
-\r
VERSION_STRING = 1.0\r
LIBRARY_CLASS = ArmTrustedMonitorLib\r
\r
-[Sources.common]\r
- ArmTrustedMonitorLibNull.c\r
-\r
[Sources.ARM]\r
+ Arm/ArmTrustedMonitorLibNull.c\r
Arm/MonitorTable.asm | RVCT\r
Arm/MonitorTable.S | GCC\r
\r
+[Sources.AARCH64]\r
+ AArch64/ArmTrustedMonitorLibNull.c\r
+\r
[Packages]\r
ArmPkg/ArmPkg.dec\r
ArmPlatformPkg/ArmPlatformPkg.dec\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Chipset/AArch64.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/EblCmdLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+EFI_STATUS\r
+EblDumpMmu (\r
+ IN UINTN Argc,\r
+ IN CHAR8 **Argv\r
+ )\r
+{\r
+ AsciiPrint ("\nNot supported on this platform.\n");\r
+\r
+ return EFI_SUCCESS;\r
+}\r
[Sources.ARM]\r
Arm/EblCmdMmu.c\r
\r
+[Sources.AARCH64]\r
+ AArch64/EblCmdMmu.c\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
--- /dev/null
+/** @file\r
+* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
+*\r
+* Copyright (c) 2012-2013, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/PrintLib.h>\r
+#include <Library/SerialPortLib.h>\r
+\r
+#include "PrePeiCore.h"\r
+\r
+VOID\r
+PeiCommonExceptionEntry (\r
+ IN UINT32 Entry,\r
+ IN UINTN LR\r
+ )\r
+{\r
+ CHAR8 Buffer[100];\r
+ UINTN CharCount;\r
+\r
+ switch (Entry) {\r
+ case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Synchronous Exception at 0x%X\n\r", LR);\r
+ break;\r
+ case EXCEPT_AARCH64_IRQ:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r", LR);\r
+ break;\r
+ case EXCEPT_AARCH64_FIQ:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r", LR);\r
+ break;\r
+ case EXCEPT_AARCH64_SERROR:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SError/Abort Exception at 0x%X\n\r", LR);\r
+ break;\r
+ default:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r", LR);\r
+ break;\r
+ }\r
+\r
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
+\r
+ while(1);\r
+}\r
+\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 11\r
+\r
+ASM_GLOBAL ASM_PFX(PeiVectorTable)\r
+\r
+//============================================================\r
+//Default Exception Handlers\r
+//============================================================\r
+\r
+ASM_PFX(PeiVectorTable):\r
+\r
+\r
+#define TO_HANDLER \\r
+ EL1_OR_EL2(x1) \\r
+1: mrs x1, elr_el1 /* EL1 Exception Link Register */ ;\\r
+ b 3f ;\\r
+2: mrs x1, elr_el2 /* EL2 Exception Link Register */ ;\\r
+3: bl ASM_PFX(PeiCommonExceptionEntry) ;\r
+\r
+\r
+//\r
+// Default Exception handlers: There is no plan to return from any of these exceptions.\r
+// No context saving at all.\r
+//\r
+\r
+.align 7\r
+_DefaultSyncExceptHandler_t:\r
+ mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
+ TO_HANDLER\r
+\r
+.align 7\r
+_DefaultIrq_t:\r
+ mov x0, #EXCEPT_AARCH64_IRQ\r
+ TO_HANDLER\r
+\r
+.align 7\r
+_DefaultFiq_t:\r
+ mov x0, #EXCEPT_AARCH64_FIQ\r
+ TO_HANDLER\r
+\r
+.align 7\r
+_DefaultSError_t:\r
+ mov x0, #EXCEPT_AARCH64_SERROR\r
+ TO_HANDLER\r
+\r
+.align 7\r
+_DefaultSyncExceptHandler_h:\r
+ mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
+ TO_HANDLER\r
+\r
+.align 7\r
+_DefaultIrq_h:\r
+ mov x0, #EXCEPT_AARCH64_IRQ\r
+ TO_HANDLER\r
+\r
+.align 7\r
+_DefaultFiq_h:\r
+ mov x0, #EXCEPT_AARCH64_FIQ\r
+ TO_HANDLER\r
+\r
+.align 7\r
+_DefaultSError_h:\r
+ mov x0, #EXCEPT_AARCH64_SERROR\r
+ TO_HANDLER\r
+\r
+dead:\r
+ b dead\r
--- /dev/null
+#========================================================================================\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http:#opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#=======================================================================================\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Chipset/AArch64.h>\r
+\r
+#start of the code section\r
+.text\r
+.align 3\r
+\r
+ASM_GLOBAL ASM_PFX(SetupExceptionLevel1)\r
+ASM_GLOBAL ASM_PFX(SetupExceptionLevel2)\r
+\r
+// Setup EL1 while in EL1\r
+ASM_PFX(SetupExceptionLevel1):\r
+ mov x5, x30 // Save LR\r
+\r
+ mov x0, #CPACR_CP_FULL_ACCESS\r
+ bl ASM_PFX(ArmWriteCpacr) // Disable copro traps to EL1\r
+\r
+ ret x5\r
+\r
+// Setup EL2 while in EL2\r
+ASM_PFX(SetupExceptionLevel2):\r
+ msr sctlr_el2, xzr\r
+ mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
+\r
+ // Send all interrupts to their respective Exception levels for EL2\r
+ orr x0, x0, #(1 << 3) // Enable EL2 FIQ\r
+ orr x0, x0, #(1 << 4) // Enable EL2 IRQ\r
+ orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort\r
+ msr hcr_el2, x0 // Write back our settings\r
+\r
+ msr cptr_el2, xzr // Disable copro traps to EL2\r
+\r
+ ret\r
+\r
+dead:\r
+ b dead\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
+GCC_ASM_IMPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
+\r
+StartupAddr: .dword CEntryPoint\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+ // Do early platform specific actions\r
+ bl ASM_PFX(ArmPlatformPeiBootAction)\r
+\r
+// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect\r
+// and configure the system accordingly. EL2 is default if possible.\r
+// If we started in EL3 we need to switch and run at EL2.\r
+// If we are running at EL2 stay in EL2\r
+// If we are starting at EL1 stay in EL1.\r
+\r
+// If started at EL3 Sec is run and switches to EL2 before jumping to PEI.\r
+// If started at EL1 or EL2 Sec jumps directly to PEI without making any\r
+// changes.\r
+\r
+// Which EL are we running at? Every EL needs some level of setup...\r
+ EL1_OR_EL2_OR_EL3(x0)\r
+1:bl ASM_PFX(SetupExceptionLevel1)\r
+ b ASM_PFX(MainEntryPoint)\r
+2:bl ASM_PFX(SetupExceptionLevel2)\r
+ b ASM_PFX(MainEntryPoint)\r
+3:// If we are at EL3 we die.\r
+ b dead\r
+\r
+ASM_PFX(MainEntryPoint):\r
+ // Identify CPU ID\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ // Keep a copy of the MpId register value\r
+ mov x5, x0\r
+\r
+ // Is it the Primary Core ?\r
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
+\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), x1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)\r
+ add x1, x1, x2\r
+\r
+ // x0 is equal to 1 if I am the primary core\r
+ cmp x0, #1\r
+ b.eq _SetupPrimaryCoreStack\r
+\r
+_SetupSecondaryCoreStack:\r
+ // x1 contains the base of the secondary stacks\r
+\r
+ // Get the Core Position\r
+ mov x6, x1 // Save base of the secondary stacks\r
+ mov x0, x5\r
+ bl ASM_PFX(ArmPlatformGetCorePosition)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add x0, x0, #1\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x2)\r
+ mul x0, x0, x2\r
+ // SP = StackBase + StackOffset\r
+ add sp, x6, x0\r
+\r
+_PrepareArguments:\r
+ // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
+ LoadConstantToReg (FixedPcdGet64(PcdFvBaseAddress), x2)\r
+ add x2, x2, #8\r
+ ldr x1, [x2]\r
+\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr x3, StartupAddr\r
+\r
+ // Jump to PrePeiCore C code\r
+ // x0 = mp_id\r
+ // x1 = pei_core_address\r
+ mov x0, x5\r
+ blr x3\r
+\r
+_SetupPrimaryCoreStack:\r
+ // x1 contains the top of the primary stack\r
+ LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), x2)\r
+\r
+ // The reserved space for global variable must be 16-bytes aligned for pushing\r
+ // 128-bit variable on the stack\r
+ SetPrimaryStack (x1, x2, x3, x4)\r
+ b _PrepareArguments\r
+\r
+dead:\r
+ b dead\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.text\r
+.align 3\r
+\r
+ASM_GLOBAL ASM_PFX(SecSwitchStack)\r
+\r
+\r
+\r
+#/**\r
+# This allows the caller to switch the stack and return\r
+#\r
+# @param StackDelta Signed amount by which to modify the stack pointer\r
+#\r
+# @return Nothing. Goes to the Entry Point passing in the new parameters\r
+#\r
+#**/\r
+#VOID\r
+#EFIAPI\r
+#SecSwitchStack (\r
+# VOID *StackDelta\r
+# )#\r
+#\r
+ASM_PFX(SecSwitchStack):\r
+ mov x1, sp\r
+ add x1, x0, x1\r
+ mov sp, x1\r
+ ret\r
+\r
//\r
\r
// Write VBAR - The Exception Vector table must be aligned to its requirement\r
- ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+ //TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64\r
+ //ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
ArmWriteVBar ((UINTN)PeiVectorTable);\r
\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
Arm/Exception.asm | RVCT\r
Arm/Exception.S | GCC\r
\r
+[Sources.AARCH64]\r
+ AArch64/ArchPrePeiCore.c\r
+ AArch64/PrePeiCoreEntryPoint.S | GCC\r
+ AArch64/SwitchStack.S | GCC\r
+ AArch64/Exception.S | GCC\r
+ AArch64/Helper.S | GCC\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
Arm/SwitchStack.S | GCC\r
Arm/Exception.asm | RVCT\r
Arm/Exception.S | GCC\r
- \r
+\r
+[Sources.AARCH64]\r
+ AArch64/ArchPrePeiCore.c\r
+ AArch64/PrePeiCoreEntryPoint.S | GCC\r
+ AArch64/SwitchStack.S | GCC\r
+ AArch64/Exception.S | GCC\r
+ AArch64/Helper.S | GCC\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include "PrePi.h"\r
+\r
+#include <Chipset/AArch64.h>\r
+\r
+VOID\r
+ArchInitialize (\r
+ VOID\r
+ )\r
+{\r
+ // Enable Floating Point\r
+ if (FixedPcdGet32 (PcdVFPEnabled)) {\r
+ ArmEnableVFP ();\r
+ }\r
+\r
+ if (ArmReadCurrentEL () == AARCH64_EL2) {\r
+ // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2\r
+ ArmWriteHcr (ARM_HCR_TGE);\r
+ }\r
+}\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+#include <Chipset/ArmV7.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
+GCC_ASM_IMPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_IMPORT(ArmPlatformStackSet)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
+\r
+StartupAddr: .dword ASM_PFX(CEntryPoint)\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+ // Do early platform specific actions\r
+ bl ASM_PFX(ArmPlatformPeiBootAction)\r
+\r
+ // Get ID of this CPU in Multicore system\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ // Keep a copy of the MpId register value\r
+ mov x10, x0\r
+\r
+_SetSVCMode:\r
+// Check if we can install the stack at the top of the System Memory or if we need\r
+// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
+// at the top of the DRAM)\r
+_SetupStackPosition:\r
+ // Compute Top of System Memory\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), x1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), x2)\r
+ sub x2, x2, #1\r
+ add x1, x1, x2 // x1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
+\r
+ // Calculate Top of the Firmware Device\r
+ LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), x2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdFdSize), x3)\r
+ sub x3, x3, #1\r
+ add x3, x3, x2 // x3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
+\r
+ // UEFI Memory Size (stacks are allocated in this region)\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), x4)\r
+\r
+ //\r
+ // Reserve the memory for the UEFI region (contain stacks on its top)\r
+ //\r
+\r
+ // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
+ subs x0, x1, x3 // x0 = SystemMemoryTop - FdTop\r
+ b.mi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
+ cmp x0, x4\r
+ b.ge _SetupStack\r
+\r
+ // Case the top of stacks is the FdBaseAddress\r
+ mov x1, x2\r
+\r
+_SetupStack:\r
+ // x1 contains the top of the stack (and the UEFI Memory)\r
+\r
+ // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
+ // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
+ // top of the memory space)\r
+ adds x11, x1, #1\r
+ b.cs _SetupOverflowStack\r
+\r
+_SetupAlignedStack:\r
+ mov x1, x11\r
+ b _GetBaseUefiMemory\r
+\r
+_SetupOverflowStack:\r
+ // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
+ // aligned (4KB)\r
+ LoadConstantToReg (EFI_PAGE_MASK, x11)\r
+ and x11, x11, x1\r
+ sub x1, x1, x11\r
+\r
+_GetBaseUefiMemory:\r
+ // Calculate the Base of the UEFI Memory\r
+ sub x11, x1, x4\r
+\r
+_GetStackBase:\r
+ // r1 = The top of the Mpcore Stacks\r
+ // Stack for the primary core = PrimaryCoreStack\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)\r
+ sub x12, x1, x2\r
+\r
+ // Stack for the secondary core = Number of Cores - 1\r
+ LoadConstantToReg (FixedPcdGet32(PcdCoreCount), x0)\r
+ sub x0, x0, #1\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x1)\r
+ mul x1, x1, x0\r
+ sub x12, x12, x1\r
+\r
+ // x12 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
+ mov x0, x12\r
+ mov x1, x10\r
+ //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x3)\r
+ bl ASM_PFX(ArmPlatformStackSet)\r
+\r
+ // Is it the Primary Core ?\r
+ mov x0, x10\r
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
+ cmp x0, #1\r
+ bne _PrepareArguments\r
+\r
+_ReserveGlobalVariable:\r
+ LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), x0)\r
+ // InitializePrimaryStack($GlobalVariableSize, $Tmp1, $Tmp2)\r
+ InitializePrimaryStack(x0, x1, x2)\r
+\r
+_PrepareArguments:\r
+ mov x0, x10\r
+ mov x1, x11\r
+ mov x2, x12\r
+ mov x3, sp\r
+\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr x4, StartupAddr\r
+\r
+ // Jump to PrePiCore C code\r
+ // x0 = MpId\r
+ // x1 = UefiMemoryBase\r
+ // x2 = StacksBase\r
+ // x3 = GlobalVariableBase\r
+ blr x4\r
+\r
+_NeverReturn:\r
+ b _NeverReturn\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include "PrePi.h"\r
+\r
+VOID\r
+ArchInitialize (\r
+ VOID\r
+ )\r
+{\r
+ // Enable program flow prediction, if supported.\r
+ ArmEnableBranchPrediction ();\r
+\r
+ if (FixedPcdGet32 (PcdVFPEnabled)) {\r
+ ArmEnableVFP ();\r
+ }\r
+}\r
+\r
MainMPCore.c\r
\r
[Sources.ARM]\r
+ Arm/ArchPrePi.c\r
Arm/ModuleEntryPoint.S | GCC\r
Arm/ModuleEntryPoint.asm | RVCT\r
+\r
+[Sources.AArch64]\r
+ AArch64/ArchPrePi.c\r
+ AArch64/ModuleEntryPoint.S | GCC\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
MainUniCore.c\r
\r
[Sources.ARM]\r
+ Arm/ArchPrePi.c\r
Arm/ModuleEntryPoint.S | GCC\r
Arm/ModuleEntryPoint.asm | RVCT\r
+\r
+[Sources.AArch64]\r
+ AArch64/ArchPrePi.c\r
+ AArch64/ModuleEntryPoint.S | GCC\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
((FixedPcdGet32 (PcdFdBaseAddress) >= FixedPcdGet32 (PcdSystemMemoryBase)) &&\r
((UINT32)(FixedPcdGet32 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT32)(FixedPcdGet32 (PcdSystemMemoryBase) + FixedPcdGet32 (PcdSystemMemorySize)))));\r
\r
- // Enable program flow prediction, if supported.\r
- ArmEnableBranchPrediction ();\r
-\r
- if (FixedPcdGet32(PcdVFPEnabled)) {\r
- ArmEnableVFP();\r
- }\r
+ // Initialize the architecture specific bits\r
+ ArchInitialize ();\r
\r
// Initialize the Serial Port\r
SerialPortInitialize ();\r
OUT VOID **Ppi\r
);\r
\r
+// Initialize the Architecture specific controllers\r
+VOID\r
+ArchInitialize (\r
+ VOID\r
+ );\r
+\r
#endif /* _PREPI_H_ */\r
--- /dev/null
+#========================================================================================\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http:#opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#=======================================================================================\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Chipset/AArch64.h>\r
+\r
+#start of the code section\r
+.text\r
+.align 3\r
+\r
+ASM_GLOBAL ASM_PFX(SetupExceptionLevel3)\r
+ASM_GLOBAL ASM_PFX(SwitchToNSExceptionLevel1)\r
+ASM_GLOBAL ASM_PFX(enter_monitor_mode)\r
+ASM_GLOBAL ASM_PFX(return_from_exception)\r
+ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)\r
+ASM_GLOBAL ASM_PFX(set_non_secure_mode)\r
+\r
+ASM_PFX(SetupExceptionLevel3):\r
+ mrs x0, scr_el3 // Read EL3 Secure Configuration Register\r
+ orr x0, x0, #1 // EL0 an EL1 cannot access secure memory\r
+\r
+ // Send all interrupts to their respective Exception levels for EL3\r
+ bic x0, x0, #(1 << 1) // IRQ\r
+ bic x0, x0, #(1 << 2) // FIQ\r
+ bic x0, x0, #(1 << 3) // Serror and Abort\r
+ orr x0, x0, #(1 << 8) // Enable HVC\r
+ orr x0, x0, #(1 << 10) // Make next level down 64Bit. This is EL2 in the case of the Model.\r
+ // We need a nice way to detect this.\r
+ msr scr_el3, x0 // Write back our settings\r
+\r
+ msr cptr_el3, xzr // Disable copro traps to EL3\r
+\r
+ // Check for the primary CPU to avoid a race on the distributor registers.\r
+ mrs x0, mpidr_el1\r
+ tst x0, #15\r
+ b.ne 1f // secondary CPU\r
+\r
+ LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)\r
+ mov w0, #3 // EnableGrp0 | EnableGrp1\r
+ str w0, [x1]\r
+\r
+1: LoadConstantToReg (FixedPcdGet32(PcdGicDistributorBase), x1)\r
+ add x1, x1, #0x80\r
+ mov w0, #~0 // Grp1 interrupts\r
+ str w0, [x1], #4\r
+ b.ne 2f // Only local interrupts for secondary CPUs\r
+ str w0, [x1], #4\r
+ str w0, [x1], #4\r
+\r
+2: LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)\r
+ ldr w0, [x1]\r
+ mov w0, #3 // EnableGrp0 | EnableGrp1\r
+ str w0, [x1]\r
+\r
+ mov w0, #1 << 7 // allow NS access to GICC_PMR\r
+ str w0, [x1, #4] // GICC_PMR\r
+\r
+ ret\r
+\r
+// Switch from EL3 to NS-EL1\r
+ASM_PFX(SwitchToNSExceptionLevel1):\r
+ // Now setup our EL1. Controlled by EL2 config on Model\r
+ mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
+ orr x0, x0, #(1 << 31) // Set EL1 to be 64bit\r
+\r
+ // Send all interrupts to their respective Exception levels for EL2\r
+ bic x0, x0, #(1 << 3) // Disable virtual FIQ\r
+ bic x0, x0, #(1 << 4) // Disable virtual IRQ\r
+ bic x0, x0, #(1 << 5) // Disable virtual SError and Abort\r
+ msr hcr_el2, x0 // Write back our settings\r
+\r
+ msr cptr_el2, xzr // Disable copro traps to EL2\r
+\r
+ msr sctlr_el2, xzr\r
+\r
+ // Enable architected timer access\r
+ mrs x0, cnthctl_el2\r
+ orr x0, x0, #3 // Enable EL1 access to timers\r
+ msr cnthctl_el2, x0\r
+\r
+ mrs x0, cntkctl_el1\r
+ orr x0, x0, #3 // EL0 access to counters\r
+ msr cntkctl_el1, x0\r
+\r
+ // Set ID regs\r
+ mrs x0, midr_el1\r
+ mrs x1, mpidr_el1\r
+ msr vpidr_el2, x0\r
+ msr vmpidr_el2, x1\r
+\r
+ ret\r
+\r
+\r
+// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7\r
+// we don't need a mode switch, just setup the Arguments and jump.\r
+// x0: Monitor World EntryPoint\r
+// x1: MpId\r
+// x2: SecBootMode\r
+// x3: Secure Monitor mode stack\r
+ASM_PFX(enter_monitor_mode):\r
+ mov x4, x0 // Swap EntryPoint and MpId registers\r
+ mov x0, x1\r
+ mov x1, x2\r
+ mov x2, x3\r
+ br x4\r
+\r
+// Put the address in correct ELR_ELx and do a eret.\r
+// We may need to do some config before we change to another Mode.\r
+ASM_PFX(return_from_exception):\r
+ msr elr_el3, x0\r
+\r
+ mrs x7, spsr_el3\r
+ ands w7, w7, #0xC\r
+ cmp w7, #0xC // EL3?\r
+ b.eq 3f\r
+ bl ASM_PFX(SetupExceptionLevel3)\r
+ cmp w7, #0x8 // EL2?\r
+ b.eq 2f\r
+ cmp w7, #0x4 // EL1?\r
+ b.eq 1f\r
+ b dead // We should never get here.\r
+\r
+1: bl ASM_PFX(SwitchToNSExceptionLevel1)\r
+2: // EL2: No more setup required.\r
+3: // EL3: Not sure why we would do this.\r
+ eret\r
+\r
+// For AArch64 we need to construct the spsr we want from individual bits and pieces.\r
+ASM_PFX(copy_cpsr_into_spsr):\r
+ mrs x0, CurrentEl // Get the current exception level we are running at.\r
+ mrs x1, SPSel // Which Stack are we using\r
+ orr x0, x0, x1\r
+ mrs x1, daif // Which interrupts are enabled\r
+ orr x0, x0, x1\r
+ msr spsr_el3, x0 // Write to spsr\r
+ ret\r
+\r
+// Get this from platform file.\r
+ASM_PFX(set_non_secure_mode):\r
+ msr spsr_el3, x0\r
+ ret\r
+\r
+dead:\r
+ b dead\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AutoGen.h>\r
+#include <AsmMacroIoLibV8.h>\r
+#include "SecInternal.h"\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
+GCC_ASM_IMPORT(ArmDisableInterrupts)\r
+GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
+GCC_ASM_IMPORT(ArmCallWFE)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
+\r
+StartupAddr: .dword ASM_PFX(CEntryPoint)\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+\r
+// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect\r
+// and configure the system accordingly. EL2 is default if possible.\r
+// If we started in EL3 we need to switch and run at EL2.\r
+// If we are running at EL2 stay in EL2\r
+// If we are starting at EL1 stay in EL1.\r
+\r
+// Sec only runs in EL3. Othewise we jump to PEI without changing anything.\r
+// If Sec runs we change to EL2 before switching to PEI.\r
+\r
+// Which EL are we running at? Every EL needs some level of setup...\r
+ EL1_OR_EL2_OR_EL3(x0)\r
+1:// If we are at EL1 or EL2 leave SEC for PEI.\r
+2:b ASM_PFX(JumpToPEI)\r
+ // If we are at EL3 we need to configure it and switch to EL2\r
+3:b ASM_PFX(MainEntryPoint)\r
+\r
+ASM_PFX(MainEntryPoint):\r
+ // First ensure all interrupts are disabled\r
+ bl ASM_PFX(ArmDisableInterrupts)\r
+\r
+ // Ensure that the MMU and caches are off\r
+ bl ASM_PFX(ArmDisableCachesAndMmu)\r
+\r
+ // By default, we are doing a cold boot\r
+ mov x10, #ARM_SEC_COLD_BOOT\r
+\r
+ // Jump to Platform Specific Boot Action function\r
+ bl ASM_PFX(ArmPlatformSecBootAction)\r
+\r
+_IdentifyCpu:\r
+ // Identify CPU ID\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ // Keep a copy of the MpId register value\r
+ mov x5, x0\r
+\r
+ // Is it the Primary Core ?\r
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
+ cmp x0, #1\r
+ // Only the primary core initialize the memory (SMC)\r
+ b.eq _InitMem\r
+\r
+_WaitInitMem:\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ // Otherwise we have to wait the Primary Core to finish the initialization\r
+ cmp x10, #ARM_SEC_COLD_BOOT\r
+ b.ne _SetupSecondaryCoreStack\r
+\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ASM_PFX(ArmCallWFE)\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
+ b _SetupSecondaryCoreStack\r
+\r
+_InitMem:\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ cmp x10, #ARM_SEC_COLD_BOOT\r
+ b.ne _SetupPrimaryCoreStack\r
+\r
+ // Initialize Init Boot Memory\r
+ bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
+\r
+_SetupPrimaryCoreStack:\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)\r
+ add x1, x1, x2\r
+\r
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), x2)\r
+\r
+ // The reserved space for global variable must be 8-bytes aligned for pushing\r
+ // 64-bit variable on the stack\r
+ SetPrimaryStack (x1, x2, x3, x4)\r
+ b _PrepareArguments\r
+\r
+_SetupSecondaryCoreStack:\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)\r
+ add x6, x1, x2\r
+\r
+ // Get the Core Position\r
+ mov x0, x5\r
+ bl ASM_PFX(ArmPlatformGetCorePosition)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add x0, x0, #1\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), x2)\r
+ mul x0, x0, x2\r
+ // SP = StackBase + StackOffset\r
+ add sp, x6, x0\r
+\r
+_PrepareArguments:\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr x3, StartupAddr\r
+\r
+ // Jump to SEC C code\r
+ // r0 = mp_id\r
+ // r1 = Boot Mode\r
+ mov x0, x5\r
+ mov x1, x10\r
+ blr x3\r
+\r
+ ret\r
+\r
+ASM_PFX(JumpToPEI):\r
+ LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), x0)\r
+ blr x0\r
+\r
+dead:\r
+ b dead\r
#/** @file\r
-# SEC - Reset vector code that jumps to C and loads DXE core\r
+# SEC - Reset vector code that jumps to C and starts the PEI phase\r
# \r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
Arm/SecEntryPoint.S | GCC\r
Arm/SecEntryPoint.asm | RVCT\r
\r
+[Sources.AARCH64]\r
+ AArch64/Helper.S | GCC\r
+ AArch64/SecEntryPoint.S | GCC\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r