This way avoids the control transfer on a shared port between EHCI and companion host\r
controller when UHCI gets attached earlier than EHCI and a USB 2.0 device inserts.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation\r
+Copyright (c) 2006 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Test whether the controller belongs to Ehci type\r
//\r
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) || (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB)\r
- || ((UsbClassCReg.PI != PCI_IF_EHCI) && (UsbClassCReg.PI !=PCI_IF_UHCI))) {\r
+ || ((UsbClassCReg.ProgInterface != PCI_IF_EHCI) && (UsbClassCReg.ProgInterface !=PCI_IF_UHCI))) {\r
\r
Status = EFI_UNSUPPORTED;\r
}\r
// companion usb ehci host controller and force EHCI driver get attached to it before\r
// UHCI driver attaches to UHCI host controller.\r
//\r
- if ((UsbClassCReg.PI == PCI_IF_UHCI) &&\r
+ if ((UsbClassCReg.ProgInterface == PCI_IF_UHCI) &&\r
(UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) && \r
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {\r
Status = PciIo->GetLocation (\r
goto CLOSE_PCIIO;\r
}\r
\r
- if ((UsbClassCReg.PI == PCI_IF_EHCI) &&\r
+ if ((UsbClassCReg.ProgInterface == PCI_IF_EHCI) &&\r
(UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) && \r
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {\r
Status = Instance->GetLocation (\r
\r
Provides some data struct used by EHCI controller driver.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation\r
+Copyright (c) 2006 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include "EhciDebug.h"\r
#include "ComponentName.h"\r
\r
-typedef enum {\r
- EHC_1_MICROSECOND = 1,\r
- EHC_1_MILLISECOND = 1000 * EHC_1_MICROSECOND,\r
- EHC_1_SECOND = 1000 * EHC_1_MILLISECOND,\r
+//\r
+// EHC timeout experience values\r
+//\r
\r
- //\r
- // EHCI register operation timeout, set by experience\r
- //\r
- EHC_RESET_TIMEOUT = 1 * EHC_1_SECOND,\r
- EHC_GENERIC_TIMEOUT = 10 * EHC_1_MILLISECOND,\r
+#define EHC_1_MICROSECOND 1\r
+#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)\r
+#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)\r
\r
- //\r
- // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r
- //\r
- EHC_ROOT_PORT_RECOVERY_STALL = 20 * EHC_1_MILLISECOND,\r
+//\r
+// EHCI register operation timeout, set by experience\r
+//\r
+#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)\r
+#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)\r
\r
- //\r
- // Sync and Async transfer polling interval, set by experience,\r
- // and the unit of Async is 100us, means 50ms as interval.\r
- //\r
- EHC_SYNC_POLL_INTERVAL = 1 * EHC_1_MILLISECOND,\r
- EHC_ASYNC_POLL_INTERVAL = 50 * 10000U\r
-} EHC_TIMEOUT_EXPERIENCE_VALUE;\r
+//\r
+// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r
+//\r
+#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r
\r
+//\r
+// Sync and Async transfer polling interval, set by experience,\r
+// and the unit of Async is 100us, means 50ms as interval.\r
+//\r
+#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)\r
+#define EHC_ASYNC_POLL_INTERVAL (50 * 10000U)\r
\r
//\r
// EHC raises TPL to TPL_NOTIFY to serialize all its operations\r
\r
This file provides the information dump support for EHCI when in debug mode.\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
DEBUG ((EFI_D_INFO, "Error Count : %d\n", QtdHw->ErrCnt));\r
DEBUG ((EFI_D_INFO, "Current Page : %d\n", QtdHw->CurPage));\r
- DEBUG ((EFI_D_INFO, "IOC : %d\n", QtdHw->IOC));\r
+ DEBUG ((EFI_D_INFO, "IOC : %d\n", QtdHw->Ioc));\r
DEBUG ((EFI_D_INFO, "Total Bytes : %d\n", QtdHw->TotalBytes));\r
DEBUG ((EFI_D_INFO, "Data Toggle : %d\n", QtdHw->DataToggle));\r
\r
\r
DEBUG ((EFI_D_INFO, "Error Count : %d\n", QhHw->ErrCnt));\r
DEBUG ((EFI_D_INFO, "Current Page : %d\n", QhHw->CurPage));\r
- DEBUG ((EFI_D_INFO, "IOC : %d\n", QhHw->IOC));\r
+ DEBUG ((EFI_D_INFO, "IOC : %d\n", QhHw->Ioc));\r
DEBUG ((EFI_D_INFO, "Total Bytes : %d\n", QhHw->TotalBytes));\r
DEBUG ((EFI_D_INFO, "Data Toggle : %d\n", QhHw->DataToggle));\r
\r
\r
This file contains the definination for host controller register operation routines.\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#ifndef _EFI_EHCI_REG_H_\r
#define _EFI_EHCI_REG_H_\r
\r
+//\r
+// EHCI register offset\r
+//\r
+\r
+\r
+//\r
+// Capability register offset\r
+//\r
+#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r
+#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r
+#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r
+\r
+//\r
+// Capability register bit definition\r
+//\r
+#define HCSP_NPORTS 0x0F // Number of root hub port\r
+#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
+\r
+//\r
+// Operational register offset\r
+//\r
+#define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r
+#define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r
+#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r
+#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r
+#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r
+#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r
+#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r
+#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r
+#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r
+\r
+#define EHC_FRAME_LEN 1024\r
\r
-typedef enum {\r
- //\r
- // Capability register offset\r
- //\r
- EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset\r
- EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h\r
- EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset\r
-\r
- //\r
- // Capability register bit definition\r
- //\r
- HCSP_NPORTS = 0x0F, // Number of root hub port\r
- HCCP_64BIT = 0x01, // 64-bit addressing capability\r
-\r
- //\r
- // Operational register offset\r
- //\r
- EHC_USBCMD_OFFSET = 0x0, // USB command register offset\r
- EHC_USBSTS_OFFSET = 0x04, // Statue register offset\r
- EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset\r
- EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset\r
- EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset\r
- EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset\r
- EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset\r
- EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset\r
- EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset\r
-\r
- EHC_FRAME_LEN = 1024,\r
-\r
- //\r
- // Register bit definition\r
- //\r
- CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC\r
-\r
- USBCMD_RUN = 0x01, // Run/stop\r
- USBCMD_RESET = 0x02, // Start the host controller reset\r
- USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule\r
- USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule\r
- USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell\r
-\r
- USBSTS_IAA = 0x20, // Interrupt on async advance\r
- USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status\r
- USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status\r
- USBSTS_HALT = 0x1000, // Host controller halted\r
- USBSTS_SYS_ERROR = 0x10, // Host system error\r
- USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC\r
- // (write clean) bits in USBSTS register\r
-\r
- PORTSC_CONN = 0x01, // Current Connect Status\r
- PORTSC_CONN_CHANGE = 0x02, // Connect Status Change\r
- PORTSC_ENABLED = 0x04, // Port Enable / Disable\r
- PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change\r
- PORTSC_OVERCUR = 0x10, // Over current Active\r
- PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change\r
- PORSTSC_RESUME = 0x40, // Force Port Resume\r
- PORTSC_SUSPEND = 0x80, // Port Suspend State\r
- PORTSC_RESET = 0x100, // Port Reset\r
- PORTSC_LINESTATE_K = 0x400, // Line Status K-state\r
- PORTSC_LINESTATE_J = 0x800, // Line Status J-state\r
- PORTSC_POWER = 0x1000, // Port Power\r
- PORTSC_OWNER = 0x2000, // Port Owner\r
- PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,\r
- // they are WC (write clean)\r
- //\r
- // PCI Configuration Registers\r
- //\r
- EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */\r
-}EHCI_REGISTER_OFFSET;\r
+//\r
+// Register bit definition\r
+//\r
+#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r
+\r
+#define USBCMD_RUN 0x01 // Run/stop\r
+#define USBCMD_RESET 0x02 // Start the host controller reset\r
+#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r
+#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r
+#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r
+\r
+#define USBSTS_IAA 0x20 // Interrupt on async advance\r
+#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r
+#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r
+#define USBSTS_HALT 0x1000 // Host controller halted\r
+#define USBSTS_SYS_ERROR 0x10 // Host system error\r
+#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r
+ // (write clean) bits in USBSTS register\r
+\r
+#define PORTSC_CONN 0x01 // Current Connect Status\r
+#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r
+#define PORTSC_ENABLED 0x04 // Port Enable / Disable\r
+#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r
+#define PORTSC_OVERCUR 0x10 // Over current Active\r
+#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r
+#define PORSTSC_RESUME 0x40 // Force Port Resume\r
+#define PORTSC_SUSPEND 0x80 // Port Suspend State\r
+#define PORTSC_RESET 0x100 // Port Reset\r
+#define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r
+#define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r
+#define PORTSC_POWER 0x1000 // Port Power\r
+#define PORTSC_OWNER 0x2000 // Port Owner\r
+#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r
+ // they are WC (write clean)\r
+//\r
+// PCI Configuration Registers\r
+//\r
+#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r
\r
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
\r
//\r
#pragma pack(1)\r
typedef struct {\r
- UINT8 PI;\r
+ UINT8 ProgInterface;\r
UINT8 SubClassCode;\r
UINT8 BaseCode;\r
} USB_CLASSC;\r
\r
EHCI transfer scheduling routines.\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
QhHw->Pid = 0;\r
QhHw->ErrCnt = 0;\r
QhHw->CurPage = 0;\r
- QhHw->IOC = 0;\r
+ QhHw->Ioc = 0;\r
QhHw->TotalBytes = 0;\r
\r
for (Index = 0; Index < 5; Index++) {\r
This file contains URB request, each request is warpped in a\r
URB (Usb Request Block).\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
QtdHw->Status = QTD_STAT_ACTIVE;\r
QtdHw->Pid = PktId;\r
QtdHw->ErrCnt = QTD_MAX_ERR;\r
- QtdHw->IOC = 0;\r
+ QtdHw->Ioc = 0;\r
QtdHw->TotalBytes = 0;\r
QtdHw->DataToggle = Toggle;\r
\r
This file contains URB request, each request is warpped in a\r
URB (Usb Request Block).\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
typedef struct _EHC_QH EHC_QH;\r
typedef struct _URB URB;\r
\r
-typedef enum {\r
- //\r
- // Transfer types, used in URB to identify the transfer type\r
- //\r
- EHC_CTRL_TRANSFER = 0x01,\r
- EHC_BULK_TRANSFER = 0x02,\r
- EHC_INT_TRANSFER_SYNC = 0x04,\r
- EHC_INT_TRANSFER_ASYNC = 0x08,\r
+//\r
+// Transfer types, used in URB to identify the transfer type\r
+//\r
+#define EHC_CTRL_TRANSFER 0x01\r
+#define EHC_BULK_TRANSFER 0x02\r
+#define EHC_INT_TRANSFER_SYNC 0x04\r
+#define EHC_INT_TRANSFER_ASYNC 0x08\r
\r
- EHC_QTD_SIG = SIGNATURE_32 ('U', 'S', 'B', 'T'),\r
- EHC_QH_SIG = SIGNATURE_32 ('U', 'S', 'B', 'H'),\r
- EHC_URB_SIG = SIGNATURE_32 ('U', 'S', 'B', 'R'),\r
+#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')\r
+#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')\r
+#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
\r
- //\r
- // Hardware related bit definitions\r
- //\r
- EHC_TYPE_ITD = 0x00,\r
- EHC_TYPE_QH = 0x02,\r
- EHC_TYPE_SITD = 0x04,\r
- EHC_TYPE_FSTN = 0x06,\r
-\r
- QH_NAK_RELOAD = 3,\r
- QH_HSHBW_MULTI = 1,\r
-\r
- QTD_MAX_ERR = 3,\r
- QTD_PID_OUTPUT = 0x00,\r
- QTD_PID_INPUT = 0x01,\r
- QTD_PID_SETUP = 0x02,\r
-\r
- QTD_STAT_DO_OUT = 0,\r
- QTD_STAT_DO_SS = 0,\r
- QTD_STAT_DO_PING = 0x01,\r
- QTD_STAT_DO_CS = 0x02,\r
- QTD_STAT_TRANS_ERR = 0x08,\r
- QTD_STAT_BABBLE_ERR = 0x10,\r
- QTD_STAT_BUFF_ERR = 0x20,\r
- QTD_STAT_HALTED = 0x40,\r
- QTD_STAT_ACTIVE = 0x80,\r
- QTD_STAT_ERR_MASK = QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR,\r
-\r
- QTD_MAX_BUFFER = 4,\r
- QTD_BUF_LEN = 4096,\r
- QTD_BUF_MASK = 0x0FFF,\r
-\r
- QH_MICROFRAME_0 = 0x01,\r
- QH_MICROFRAME_1 = 0x02,\r
- QH_MICROFRAME_2 = 0x04,\r
- QH_MICROFRAME_3 = 0x08,\r
- QH_MICROFRAME_4 = 0x10,\r
- QH_MICROFRAME_5 = 0x20,\r
- QH_MICROFRAME_6 = 0x40,\r
- QH_MICROFRAME_7 = 0x80,\r
-\r
- USB_ERR_SHORT_PACKET = 0x200\r
-}EHCI_URB_FLAG_VALUE;\r
+//\r
+// Hardware related bit definitions\r
+//\r
+#define EHC_TYPE_ITD 0x00\r
+#define EHC_TYPE_QH 0x02\r
+#define EHC_TYPE_SITD 0x04\r
+#define EHC_TYPE_FSTN 0x06\r
+\r
+#define QH_NAK_RELOAD 3\r
+#define QH_HSHBW_MULTI 1\r
+\r
+#define QTD_MAX_ERR 3\r
+#define QTD_PID_OUTPUT 0x00\r
+#define QTD_PID_INPUT 0x01\r
+#define QTD_PID_SETUP 0x02\r
+\r
+#define QTD_STAT_DO_OUT 0\r
+#define QTD_STAT_DO_SS 0\r
+#define QTD_STAT_DO_PING 0x01\r
+#define QTD_STAT_DO_CS 0x02\r
+#define QTD_STAT_TRANS_ERR 0x08\r
+#define QTD_STAT_BABBLE_ERR 0x10\r
+#define QTD_STAT_BUFF_ERR 0x20\r
+#define QTD_STAT_HALTED 0x40\r
+#define QTD_STAT_ACTIVE 0x80\r
+#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)\r
+\r
+#define QTD_MAX_BUFFER 4\r
+#define QTD_BUF_LEN 4096\r
+#define QTD_BUF_MASK 0x0FFF\r
+\r
+#define QH_MICROFRAME_0 0x01\r
+#define QH_MICROFRAME_1 0x02\r
+#define QH_MICROFRAME_2 0x04\r
+#define QH_MICROFRAME_3 0x08\r
+#define QH_MICROFRAME_4 0x10\r
+#define QH_MICROFRAME_5 0x20\r
+#define QH_MICROFRAME_6 0x40\r
+#define QH_MICROFRAME_7 0x80\r
+\r
+#define USB_ERR_SHORT_PACKET 0x200\r
\r
//\r
// Fill in the hardware link point: pass in a EHC_QH/QH_HW\r
UINT32 Pid : 2;\r
UINT32 ErrCnt : 2;\r
UINT32 CurPage : 3;\r
- UINT32 IOC : 1;\r
+ UINT32 Ioc : 1;\r
UINT32 TotalBytes : 15;\r
UINT32 DataToggle : 1;\r
\r
UINT32 Pid : 2;\r
UINT32 ErrCnt : 2;\r
UINT32 CurPage : 3;\r
- UINT32 IOC : 1;\r
+ UINT32 Ioc : 1;\r
UINT32 TotalBytes : 15;\r
UINT32 DataToggle : 1;\r
\r
\r
This file contains the definination for host controller memory management routines.\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define USB_HC_HIGH_32BIT(Addr64) \\r
((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
\r
-typedef struct _USBHC_MEM_BLOCK {\r
+typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;\r
+struct _USBHC_MEM_BLOCK {\r
UINT8 *Bits; // Bit array to record which unit is allocated\r
UINTN BitsLen;\r
UINT8 *Buf;\r
UINT8 *BufHost;\r
UINTN BufLen; // Memory size in bytes\r
VOID *Mapping;\r
- struct _USBHC_MEM_BLOCK *Next;\r
-} USBHC_MEM_BLOCK;\r
+ USBHC_MEM_BLOCK *Next;\r
+};\r
\r
//\r
// USBHC_MEM_POOL is used to manage the memory used by USB\r
USBHC_MEM_BLOCK *Head;\r
} USBHC_MEM_POOL;\r
\r
-typedef enum {\r
- USBHC_MEM_UNIT = 64, // Memory allocation unit, must be 2^n, n>4\r
+//\r
+// Memory allocation unit, must be 2^n, n>4\r
+//\r
+#define USBHC_MEM_UNIT 64\r
\r
- USBHC_MEM_UNIT_MASK = USBHC_MEM_UNIT - 1,\r
- USBHC_MEM_DEFAULT_PAGES = 16\r
-} USBHC_MEM_UNIT_DATA;\r
+#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)\r
+#define USBHC_MEM_DEFAULT_PAGES 16\r
\r
#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))\r
\r
/** @file\r
PCI emumeration support functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation\r
+Copyright (c) 2006 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
if ((PciIoDevice->SrIovCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {\r
UINT16 VFStride;\r
UINT16 FirstVFOffset;\r
- UINT32 PFRID;\r
+ UINT32 PFRid;\r
UINT32 LastVF;\r
\r
//\r
//\r
// Calculate LastVF\r
//\r
- PFRID = EFI_PCI_RID(Bus, Device, Func);\r
- LastVF = PFRID + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;\r
+ PFRid = EFI_PCI_RID(Bus, Device, Func);\r
+ LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;\r
\r
//\r
// Calculate ReservedBusNum for this PF\r
\r
The UHCI driver model and HC protocol routines.\r
\r
-Copyright (c) 2004 - 2009, Intel Corporation\r
+Copyright (c) 2004 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||\r
(UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||\r
- (UsbClassCReg.PI != PCI_IF_UHCI)\r
+ (UsbClassCReg.ProgInterface != PCI_IF_UHCI)\r
) {\r
\r
Status = EFI_UNSUPPORTED;\r
\r
The definition for UHCI driver model and HC protocol routines.\r
\r
-Copyright (c) 2004 - 2009, Intel Corporation\r
+Copyright (c) 2004 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include "UhciDebug.h"\r
#include "ComponentName.h"\r
\r
-typedef enum {\r
- UHC_1_MICROSECOND = 1,\r
- UHC_1_MILLISECOND = 1000 * UHC_1_MICROSECOND,\r
- UHC_1_SECOND = 1000 * UHC_1_MILLISECOND,\r
+//\r
+// UHC timeout experience values\r
+//\r
\r
- //\r
- // UHCI register operation timeout, set by experience\r
- //\r
- UHC_GENERIC_TIMEOUT = UHC_1_SECOND,\r
+#define UHC_1_MICROSECOND 1\r
+#define UHC_1_MILLISECOND (1000 * UHC_1_MICROSECOND)\r
+#define UHC_1_SECOND (1000 * UHC_1_MILLISECOND)\r
\r
- //\r
- // Wait for force global resume(FGR) complete, refers to\r
- // specification[UHCI11-2.1.1]\r
- //\r
- UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,\r
+//\r
+// UHCI register operation timeout, set by experience\r
+//\r
+#define UHC_GENERIC_TIMEOUT UHC_1_SECOND\r
\r
- //\r
- // Wait for roothub port reset and recovery, reset stall\r
- // is set by experience, and recovery stall refers to\r
- // specification[UHCI11-2.1.1]\r
- //\r
- UHC_ROOT_PORT_RESET_STALL = 50 * UHC_1_MILLISECOND,\r
- UHC_ROOT_PORT_RECOVERY_STALL = 10 * UHC_1_MILLISECOND,\r
+//\r
+// Wait for force global resume(FGR) complete, refers to\r
+// specification[UHCI11-2.1.1]\r
+//\r
+#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)\r
\r
- //\r
- // Sync and Async transfer polling interval, set by experience,\r
- // and the unit of Async is 100us.\r
- //\r
- UHC_SYNC_POLL_INTERVAL = 1 * UHC_1_MILLISECOND,\r
- UHC_ASYNC_POLL_INTERVAL = 50 * 10000UL\r
-}UHC_TIMEOUT_EXPERIENCE_VALUE;\r
+//\r
+// Wait for roothub port reset and recovery, reset stall\r
+// is set by experience, and recovery stall refers to\r
+// specification[UHCI11-2.1.1]\r
+//\r
+#define UHC_ROOT_PORT_RESET_STALL (50 * UHC_1_MILLISECOND)\r
+#define UHC_ROOT_PORT_RECOVERY_STALL (10 * UHC_1_MILLISECOND)\r
\r
+//\r
+// Sync and Async transfer polling interval, set by experience,\r
+// and the unit of Async is 100us.\r
+//\r
+#define UHC_SYNC_POLL_INTERVAL (1 * UHC_1_MILLISECOND)\r
+#define UHC_ASYNC_POLL_INTERVAL (50 * 10000UL)\r
\r
//\r
// UHC raises TPL to TPL_NOTIFY to serialize all its operations\r
\r
#pragma pack(1)\r
typedef struct {\r
- UINT8 PI;\r
+ UINT8 ProgInterface;\r
UINT8 SubClassCode;\r
UINT8 BaseCode;\r
} USB_CLASSC;\r
\r
The definition for UHCI register operation routines.\r
\r
-Copyright (c) 2007 - 2008, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#ifndef _EFI_UHCI_REG_H_\r
#define _EFI_UHCI_REG_H_\r
\r
-typedef enum {\r
- UHCI_FRAME_NUM = 1024,\r
-\r
- //\r
- // Register offset and PCI related staff\r
- //\r
- USB_BAR_INDEX = 4,\r
-\r
- USBCMD_OFFSET = 0,\r
- USBSTS_OFFSET = 2,\r
- USBINTR_OFFSET = 4,\r
- USBPORTSC_OFFSET = 0x10,\r
- USB_FRAME_NO_OFFSET = 6,\r
- USB_FRAME_BASE_OFFSET = 8,\r
- USB_EMULATION_OFFSET = 0xC0,\r
-\r
- //\r
- // Packet IDs\r
- //\r
- SETUP_PACKET_ID = 0x2D,\r
- INPUT_PACKET_ID = 0x69,\r
- OUTPUT_PACKET_ID = 0xE1,\r
- ERROR_PACKET_ID = 0x55,\r
-\r
- //\r
- // USB port status and control bit definition.\r
- //\r
- USBPORTSC_CCS = BIT0, // Current Connect Status\r
- USBPORTSC_CSC = BIT1, // Connect Status Change\r
- USBPORTSC_PED = BIT2, // Port Enable / Disable\r
- USBPORTSC_PEDC = BIT3, // Port Enable / Disable Change\r
- USBPORTSC_LSL = BIT4, // Line Status Low BIT\r
- USBPORTSC_LSH = BIT5, // Line Status High BIT\r
- USBPORTSC_RD = BIT6, // Resume Detect\r
- USBPORTSC_LSDA = BIT8, // Low Speed Device Attached\r
- USBPORTSC_PR = BIT9, // Port Reset\r
- USBPORTSC_SUSP = BIT12, // Suspend\r
-\r
- //\r
- // UHCI Spec said it must implement 2 ports each host at least,\r
- // and if more, check whether the bit7 of PORTSC is always 1.\r
- // So here assume the max of port number each host is 16.\r
- //\r
- USB_MAX_ROOTHUB_PORT = 0x0F,\r
- \r
- //\r
- // Command register bit definitions\r
- //\r
- USBCMD_RS = BIT0, // Run/Stop\r
- USBCMD_HCRESET = BIT1, // Host reset\r
- USBCMD_GRESET = BIT2, // Global reset\r
- USBCMD_EGSM = BIT3, // Global Suspend Mode\r
- USBCMD_FGR = BIT4, // Force Global Resume\r
- USBCMD_SWDBG = BIT5, // SW Debug mode\r
- USBCMD_CF = BIT6, // Config Flag (sw only)\r
- USBCMD_MAXP = BIT7, // Max Packet (0 = 32, 1 = 64)\r
-\r
- //\r
- // USB Status register bit definitions\r
- //\r
- USBSTS_USBINT = BIT0, // Interrupt due to IOC\r
- USBSTS_ERROR = BIT1, // Interrupt due to error\r
- USBSTS_RD = BIT2, // Resume Detect\r
- USBSTS_HSE = BIT3, // Host System Error\r
- USBSTS_HCPE = BIT4, // Host Controller Process Error\r
- USBSTS_HCH = BIT5, // HC Halted\r
-\r
- USBTD_ACTIVE = BIT7, // TD is still active\r
- USBTD_STALLED = BIT6, // TD is stalled\r
- USBTD_BUFFERR = BIT5, // Buffer underflow or overflow\r
- USBTD_BABBLE = BIT4, // Babble condition\r
- USBTD_NAK = BIT3, // NAK is received\r
- USBTD_CRC = BIT2, // CRC/Time out error\r
- USBTD_BITSTUFF = BIT1 // Bit stuff error\r
-}UHCI_REGISTER_OFFSET;\r
+//\r
+// UHCI register offset\r
+//\r
+\r
+#define UHCI_FRAME_NUM 1024\r
+\r
+//\r
+// Register offset and PCI related staff\r
+//\r
+#define USB_BAR_INDEX 4\r
+\r
+#define USBCMD_OFFSET 0\r
+#define USBSTS_OFFSET 2\r
+#define USBINTR_OFFSET 4\r
+#define USBPORTSC_OFFSET 0x10\r
+#define USB_FRAME_NO_OFFSET 6\r
+#define USB_FRAME_BASE_OFFSET 8\r
+#define USB_EMULATION_OFFSET 0xC0\r
+\r
+//\r
+// Packet IDs\r
+//\r
+#define SETUP_PACKET_ID 0x2D\r
+#define INPUT_PACKET_ID 0x69\r
+#define OUTPUT_PACKET_ID 0xE1\r
+#define ERROR_PACKET_ID 0x55\r
+\r
+//\r
+// USB port status and control bit definition.\r
+//\r
+#define USBPORTSC_CCS BIT0 // Current Connect Status\r
+#define USBPORTSC_CSC BIT1 // Connect Status Change\r
+#define USBPORTSC_PED BIT2 // Port Enable / Disable\r
+#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change\r
+#define USBPORTSC_LSL BIT4 // Line Status Low BIT\r
+#define USBPORTSC_LSH BIT5 // Line Status High BIT\r
+#define USBPORTSC_RD BIT6 // Resume Detect\r
+#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached\r
+#define USBPORTSC_PR BIT9 // Port Reset\r
+#define USBPORTSC_SUSP BIT12 // Suspend\r
+\r
+//\r
+// UHCI Spec said it must implement 2 ports each host at least,\r
+// and if more, check whether the bit7 of PORTSC is always 1.\r
+// So here assume the max of port number each host is 16.\r
+//\r
+#define USB_MAX_ROOTHUB_PORT 0x0F\r
+\r
+//\r
+// Command register bit definitions\r
+//\r
+#define USBCMD_RS BIT0 // Run/Stop\r
+#define USBCMD_HCRESET BIT1 // Host reset\r
+#define USBCMD_GRESET BIT2 // Global reset\r
+#define USBCMD_EGSM BIT3 // Global Suspend Mode\r
+#define USBCMD_FGR BIT4 // Force Global Resume\r
+#define USBCMD_SWDBG BIT5 // SW Debug mode\r
+#define USBCMD_CF BIT6 // Config Flag (sw only)\r
+#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)\r
+\r
+//\r
+// USB Status register bit definitions\r
+//\r
+#define USBSTS_USBINT BIT0 // Interrupt due to IOC\r
+#define USBSTS_ERROR BIT1 // Interrupt due to error\r
+#define USBSTS_RD BIT2 // Resume Detect\r
+#define USBSTS_HSE BIT3 // Host System Error\r
+#define USBSTS_HCPE BIT4 // Host Controller Process Error\r
+#define USBSTS_HCH BIT5 // HC Halted\r
+\r
+#define USBTD_ACTIVE BIT7 // TD is still active\r
+#define USBTD_STALLED BIT6 // TD is stalled\r
+#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow\r
+#define USBTD_BABBLE BIT4 // Babble condition\r
+#define USBTD_NAK BIT3 // NAK is received\r
+#define USBTD_CRC BIT2 // CRC/Time out error\r
+#define USBTD_BITSTUFF BIT1 // Bit stuff error\r
\r
\r
/**\r
\r
The definition for EHCI register operation routines.\r
\r
-Copyright (c) 2007, 2009, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define _EFI_UHCI_SCHED_H_\r
\r
\r
-typedef enum {\r
- UHCI_ASYNC_INT_SIGNATURE = SIGNATURE_32 ('u', 'h', 'c', 'a'),\r
-\r
- //\r
- // The failure mask for USB transfer return status. If any of\r
- // these bit is set, the transfer failed. EFI_USB_ERR_NOEXECUTE\r
- // and EFI_USB_ERR_NAK are not considered as error condition:\r
- // the transfer is still going on.\r
- //\r
- USB_ERR_FAIL_MASK = EFI_USB_ERR_STALL | EFI_USB_ERR_BUFFER |\r
- EFI_USB_ERR_BABBLE | EFI_USB_ERR_CRC |\r
- EFI_USB_ERR_TIMEOUT | EFI_USB_ERR_BITSTUFF |\r
- EFI_USB_ERR_SYSTEM\r
+#define UHCI_ASYNC_INT_SIGNATURE SIGNATURE_32 ('u', 'h', 'c', 'a')\r
+//\r
+// The failure mask for USB transfer return status. If any of\r
+// these bit is set, the transfer failed. EFI_USB_ERR_NOEXECUTE\r
+// and EFI_USB_ERR_NAK are not considered as error condition:\r
+// the transfer is still going on.\r
+//\r
+#define USB_ERR_FAIL_MASK (EFI_USB_ERR_STALL | EFI_USB_ERR_BUFFER | \\r
+ EFI_USB_ERR_BABBLE | EFI_USB_ERR_CRC | \\r
+ EFI_USB_ERR_TIMEOUT | EFI_USB_ERR_BITSTUFF | \\r
+ EFI_USB_ERR_SYSTEM)\r
\r
-}UHCI_ERR_FAIL_MASK;\r
\r
//\r
// Structure to return the result of UHCI QH execution.\r
\r
This file contains the definination for host controller memory management routines\r
\r
-Copyright (c) 2007, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
\r
\r
-typedef struct _USBHC_MEM_BLOCK {\r
+typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;\r
+struct _USBHC_MEM_BLOCK {\r
UINT8 *Bits; // Bit array to record which unit is allocated\r
UINTN BitsLen;\r
UINT8 *Buf;\r
UINT8 *BufHost;\r
UINTN BufLen; // Memory size in bytes\r
VOID *Mapping;\r
- struct _USBHC_MEM_BLOCK *Next;\r
-} USBHC_MEM_BLOCK;\r
+ USBHC_MEM_BLOCK *Next;\r
+};\r
\r
//\r
// USBHC_MEM_POOL is used to manage the memory used by USB\r
USBHC_MEM_BLOCK *Head;\r
} USBHC_MEM_POOL;\r
\r
-typedef enum {\r
- USBHC_MEM_UNIT = 64, // Memory allocation unit, must be 2^n, n>4\r
+//\r
+// Memory allocation unit, must be 2^n, n>4\r
+//\r
+#define USBHC_MEM_UNIT 64\r
\r
- USBHC_MEM_UNIT_MASK = USBHC_MEM_UNIT - 1,\r
- USBHC_MEM_DEFAULT_PAGES = 16\r
-}UHCI_MEM_UNIT_DATA;\r
+#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)\r
+#define USBHC_MEM_DEFAULT_PAGES 16\r
\r
#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))\r
\r
/** @file\r
Header file for SCSI Bus Driver.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#define SCSI_IO_DEV_SIGNATURE SIGNATURE_32 ('s', 'c', 'i', 'o')\r
\r
+typedef union {\r
+ UINT32 Scsi;\r
+ UINT8 ExtScsi[4]; \r
+} SCSI_ID;\r
+\r
typedef struct _SCSI_TARGET_ID {\r
- union {\r
- UINT32 Scsi;\r
- UINT8 ExtScsi[4]; \r
- } ScsiId;\r
+ SCSI_ID ScsiId;\r
UINT8 ExtScsiId[12];\r
}SCSI_TARGET_ID;\r
\r
\r
Usb Bus Driver Binding and Bus IO Protocol.\r
\r
-Copyright (c) 2004 - 2007, Intel Corporation\r
+Copyright (c) 2004 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include "UsbHub.h"\r
#include "UsbEnumer.h"\r
\r
-typedef enum {\r
- USB_MAX_LANG_ID = 16,\r
- USB_MAX_INTERFACE = 16,\r
- USB_MAX_DEVICES = 128,\r
+//\r
+// USB bus timeout experience values\r
+//\r
\r
- USB_BUS_1_MILLISECOND = 1000,\r
+#define USB_MAX_LANG_ID 16\r
+#define USB_MAX_INTERFACE 16\r
+#define USB_MAX_DEVICES 128\r
\r
- //\r
- // Roothub and hub's polling interval, set by experience,\r
- // The unit of roothub is 100us, means 1s as interval, and\r
- // the unit of hub is 1ms, means 64ms as interval.\r
- //\r
- USB_ROOTHUB_POLL_INTERVAL = 1000 * 10000U,\r
- USB_HUB_POLL_INTERVAL = 64,\r
+#define USB_BUS_1_MILLISECOND 1000\r
\r
- //\r
- // Wait for port stable to work, refers to specification\r
- // [USB20-9.1.2]\r
- //\r
- USB_WAIT_PORT_STABLE_STALL = 100 * USB_BUS_1_MILLISECOND,\r
+//\r
+// Roothub and hub's polling interval, set by experience,\r
+// The unit of roothub is 100us, means 1s as interval, and\r
+// the unit of hub is 1ms, means 64ms as interval.\r
+//\r
+#define USB_ROOTHUB_POLL_INTERVAL (1000 * 10000U)\r
+#define USB_HUB_POLL_INTERVAL 64\r
\r
- //\r
- // Wait for port statue reg change, set by experience\r
- //\r
- USB_WAIT_PORT_STS_CHANGE_STALL = 5 * USB_BUS_1_MILLISECOND,\r
+//\r
+// Wait for port stable to work, refers to specification\r
+// [USB20-9.1.2]\r
+//\r
+#define USB_WAIT_PORT_STABLE_STALL (100 * USB_BUS_1_MILLISECOND)\r
\r
- //\r
- // Wait for set device address, refers to specification\r
- // [USB20-9.2.6.3, it says 2ms]\r
- //\r
- USB_SET_DEVICE_ADDRESS_STALL = 20 * USB_BUS_1_MILLISECOND,\r
+//\r
+// Wait for port statue reg change, set by experience\r
+//\r
+#define USB_WAIT_PORT_STS_CHANGE_STALL (5 * USB_BUS_1_MILLISECOND)\r
\r
- //\r
- // Wait for retry max packet size, set by experience\r
- //\r
- USB_RETRY_MAX_PACK_SIZE_STALL = 100 * USB_BUS_1_MILLISECOND,\r
+//\r
+// Wait for set device address, refers to specification\r
+// [USB20-9.2.6.3, it says 2ms]\r
+//\r
+#define USB_SET_DEVICE_ADDRESS_STALL (20 * USB_BUS_1_MILLISECOND)\r
\r
- //\r
- // Wait for hub port power-on, refers to specification\r
- // [USB20-11.23.2]\r
- //\r
- USB_SET_PORT_POWER_STALL = 2 * USB_BUS_1_MILLISECOND,\r
+//\r
+// Wait for retry max packet size, set by experience\r
+//\r
+#define USB_RETRY_MAX_PACK_SIZE_STALL (100 * USB_BUS_1_MILLISECOND)\r
\r
- //\r
- // Wait for port reset, refers to specification\r
- // [USB20-7.1.7.5, it says 10ms for hub and 50ms for\r
- // root hub]\r
- //\r
- USB_SET_PORT_RESET_STALL = 20 * USB_BUS_1_MILLISECOND,\r
- USB_SET_ROOT_PORT_RESET_STALL = 50 * USB_BUS_1_MILLISECOND,\r
+//\r
+// Wait for hub port power-on, refers to specification\r
+// [USB20-11.23.2]\r
+//\r
+#define USB_SET_PORT_POWER_STALL (2 * USB_BUS_1_MILLISECOND)\r
\r
- //\r
- // Wait for clear roothub port reset, set by experience\r
- //\r
- USB_CLR_ROOT_PORT_RESET_STALL = 20 * USB_BUS_1_MILLISECOND,\r
+//\r
+// Wait for port reset, refers to specification\r
+// [USB20-7.1.7.5, it says 10ms for hub and 50ms for\r
+// root hub]\r
+//\r
+#define USB_SET_PORT_RESET_STALL (20 * USB_BUS_1_MILLISECOND)\r
+#define USB_SET_ROOT_PORT_RESET_STALL (50 * USB_BUS_1_MILLISECOND)\r
\r
- //\r
- // Wait for set roothub port enable, set by experience\r
- //\r
- USB_SET_ROOT_PORT_ENABLE_STALL = 20 * USB_BUS_1_MILLISECOND,\r
+//\r
+// Wait for clear roothub port reset, set by experience\r
+//\r
+#define USB_CLR_ROOT_PORT_RESET_STALL (20 * USB_BUS_1_MILLISECOND)\r
\r
- //\r
- // Send general device request timeout.\r
- // \r
- // The USB Specification 2.0, section 11.24.1 recommends a value of\r
- // 50 milliseconds. We use a value of 100 milliseconds to work\r
- // around slower hubs and devices.\r
- //\r
- USB_GENERAL_DEVICE_REQUEST_TIMEOUT = 100,\r
+//\r
+// Wait for set roothub port enable, set by experience\r
+//\r
+#define USB_SET_ROOT_PORT_ENABLE_STALL (20 * USB_BUS_1_MILLISECOND)\r
\r
- //\r
- // Send clear feature request timeout, set by experience\r
- //\r
- USB_CLEAR_FEATURE_REQUEST_TIMEOUT = 10\r
-}USB_BUS_TIMEOUT_EXPERIENCE_VALUE;\r
+//\r
+// Send general device request timeout.\r
+// \r
+// The USB Specification 2.0, section 11.24.1 recommends a value of\r
+// 50 milliseconds. We use a value of 100 milliseconds to work\r
+// around slower hubs and devices.\r
+//\r
+#define USB_GENERAL_DEVICE_REQUEST_TIMEOUT 100\r
+\r
+//\r
+// Send clear feature request timeout, set by experience\r
+//\r
+#define USB_CLEAR_FEATURE_REQUEST_TIMEOUT 10\r
\r
//\r
// Bus raises TPL to TPL_NOTIFY to serialize all its operations\r
\r
Manage Usb Descriptor List\r
\r
-Copyright (c) 2007, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#ifndef _USB_DESCRIPTOR_H_\r
#define _USB_DESCRIPTOR_H_\r
\r
-typedef enum {\r
- USB_MAX_INTERFACE_SETTING = 8\r
-}USB_INTERFACE_SETTING_MAX;\r
+#define USB_MAX_INTERFACE_SETTING 8\r
\r
//\r
// The RequestType in EFI_USB_DEVICE_REQUEST is composed of\r
\r
The definition for USB hub.\r
\r
-Copyright (c) 2007, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define USB_ENDPOINT_ADDR(EpAddr) ((EpAddr) & 0x7F)\r
#define USB_ENDPOINT_TYPE(Desc) ((Desc)->Attributes & USB_ENDPOINT_TYPE_MASK)\r
\r
-typedef enum {\r
- USB_DESC_TYPE_HUB = 0x29,\r
-\r
- //\r
- // Hub class control transfer target\r
- //\r
- USB_HUB_TARGET_HUB = 0,\r
- USB_HUB_TARGET_PORT = 3,\r
-\r
- //\r
- // HUB class specific contrl transfer request type\r
- //\r
- USB_HUB_REQ_GET_STATUS = 0,\r
- USB_HUB_REQ_CLEAR_FEATURE = 1,\r
- USB_HUB_REQ_SET_FEATURE = 3,\r
- USB_HUB_REQ_GET_DESC = 6,\r
- USB_HUB_REQ_SET_DESC = 7,\r
- USB_HUB_REQ_CLEAR_TT = 8,\r
- USB_HUB_REQ_RESET_TT = 9,\r
- USB_HUB_REQ_GET_TT_STATE = 10,\r
- USB_HUB_REQ_STOP_TT = 11,\r
-\r
-\r
- //\r
- // USB hub class feature selector\r
- //\r
- USB_HUB_C_HUB_LOCAL_POWER = 0,\r
- USB_HUB_C_HUB_OVER_CURRENT = 1,\r
- USB_HUB_PORT_CONNECTION = 0,\r
- USB_HUB_PORT_ENABLE = 1,\r
- USB_HUB_PORT_SUSPEND = 2,\r
- USB_HUB_PORT_OVER_CURRENT = 3,\r
- USB_HUB_PORT_RESET = 4,\r
- USB_HUB_PORT_POWER = 8,\r
- USB_HUB_PORT_LOW_SPEED = 9,\r
- USB_HUB_C_PORT_CONNECT = 16,\r
- USB_HUB_C_PORT_ENABLE = 17,\r
- USB_HUB_C_PORT_SUSPEND = 18,\r
- USB_HUB_C_PORT_OVER_CURRENT = 19,\r
- USB_HUB_C_PORT_RESET = 20,\r
- USB_HUB_PORT_TEST = 21,\r
- USB_HUB_PORT_INDICATOR = 22,\r
-\r
- //\r
- // USB hub power control method. In gang power control\r
- //\r
- USB_HUB_GANG_POWER_CTRL = 0,\r
- USB_HUB_PORT_POWER_CTRL = 0x01,\r
-\r
- //\r
- // USB hub status bits\r
- //\r
- USB_HUB_STAT_LOCAL_POWER = 0x01,\r
- USB_HUB_STAT_OVER_CURRENT = 0x02,\r
- USB_HUB_STAT_C_LOCAL_POWER = 0x01,\r
- USB_HUB_STAT_C_OVER_CURRENT = 0x02,\r
-\r
- USB_HUB_CLASS_CODE = 0x09,\r
- USB_HUB_SUBCLASS_CODE = 0x00,\r
-\r
- //\r
- // Host software return timeout if port status doesn't change \r
- // after 500ms(LOOP * STALL = 100 * 5ms), set by experience\r
- //\r
- USB_WAIT_PORT_STS_CHANGE_LOOP = 100\r
-}USB_HUB_FLAGS_VALUE;\r
+\r
+#define USB_DESC_TYPE_HUB 0x29\r
+//\r
+// Hub class control transfer target\r
+//\r
+#define USB_HUB_TARGET_HUB 0\r
+#define USB_HUB_TARGET_PORT 3\r
+//\r
+// HUB class specific contrl transfer request type\r
+//\r
+#define USB_HUB_REQ_GET_STATUS 0\r
+#define USB_HUB_REQ_CLEAR_FEATURE 1\r
+#define USB_HUB_REQ_SET_FEATURE 3\r
+#define USB_HUB_REQ_GET_DESC 6\r
+#define USB_HUB_REQ_SET_DESC 7\r
+#define USB_HUB_REQ_CLEAR_TT 8\r
+#define USB_HUB_REQ_RESET_TT 9\r
+#define USB_HUB_REQ_GET_TT_STATE 10\r
+#define USB_HUB_REQ_STOP_TT 11\r
+//\r
+// USB hub class feature selector\r
+//\r
+#define USB_HUB_C_HUB_LOCAL_POWER 0\r
+#define USB_HUB_C_HUB_OVER_CURRENT 1\r
+#define USB_HUB_PORT_CONNECTION 0\r
+#define USB_HUB_PORT_ENABLE 1\r
+#define USB_HUB_PORT_SUSPEND 2\r
+#define USB_HUB_PORT_OVER_CURRENT 3\r
+#define USB_HUB_PORT_RESET 4\r
+#define USB_HUB_PORT_POWER 8\r
+#define USB_HUB_PORT_LOW_SPEED 9\r
+#define USB_HUB_C_PORT_CONNECT 16\r
+#define USB_HUB_C_PORT_ENABLE 17\r
+#define USB_HUB_C_PORT_SUSPEND 18\r
+#define USB_HUB_C_PORT_OVER_CURRENT 19\r
+#define USB_HUB_C_PORT_RESET 20\r
+#define USB_HUB_PORT_TEST 21\r
+#define USB_HUB_PORT_INDICATOR 22\r
+//\r
+// USB hub power control method. In gang power control\r
+//\r
+#define USB_HUB_GANG_POWER_CTRL 0\r
+#define USB_HUB_PORT_POWER_CTRL 0x01\r
+//\r
+// USB hub status bits\r
+//\r
+#define USB_HUB_STAT_LOCAL_POWER 0x01\r
+#define USB_HUB_STAT_OVER_CURRENT 0x02\r
+#define USB_HUB_STAT_C_LOCAL_POWER 0x01\r
+#define USB_HUB_STAT_C_OVER_CURRENT 0x02\r
+\r
+#define USB_HUB_CLASS_CODE 0x09\r
+#define USB_HUB_SUBCLASS_CODE 0x00\r
+\r
+//\r
+// Host software return timeout if port status doesn't change \r
+// after 500ms(LOOP * STALL = 100 * 5ms), set by experience\r
+//\r
+#define USB_WAIT_PORT_STS_CHANGE_LOOP 100\r
\r
#pragma pack(1)\r
//\r
Definition of USB Mass Storage Class and its value, USB Mass Transport Protocol, \r
and other common definitions.\r
\r
-Copyright (c) 2007 - 2008, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define USB_IS_INTERRUPT_ENDPOINT(Attribute) (((Attribute) & (BIT0 | BIT1)) == USB_ENDPOINT_INTERRUPT)\r
#define USB_IS_ERROR(Result, Error) (((Result) & (Error)) != 0)\r
\r
-typedef enum {\r
- //\r
- // Usb mass storage class code\r
- //\r
- USB_MASS_STORE_CLASS = 0x08,\r
-\r
- //\r
- // Usb mass storage subclass code, specify the command set used.\r
- //\r
- USB_MASS_STORE_RBC = 0x01, ///< Reduced Block Commands\r
- USB_MASS_STORE_8020I = 0x02, ///< SFF-8020i, typically a CD/DVD device\r
- USB_MASS_STORE_QIC = 0x03, ///< Typically a tape device\r
- USB_MASS_STORE_UFI = 0x04, ///< Typically a floppy disk driver device\r
- USB_MASS_STORE_8070I = 0x05, ///< SFF-8070i, typically a floppy disk driver device.\r
- USB_MASS_STORE_SCSI = 0x06, ///< SCSI transparent command set\r
-\r
- //\r
- // Usb mass storage protocol code, specify the transport protocol\r
- //\r
- USB_MASS_STORE_CBI0 = 0x00, ///< CBI protocol with command completion interrupt\r
- USB_MASS_STORE_CBI1 = 0x01, ///< CBI protocol without command completion interrupt\r
- USB_MASS_STORE_BOT = 0x50, ///< Bulk-Only Transport\r
-\r
- USB_MASS_1_MILLISECOND = 1000,\r
- USB_MASS_1_SECOND = 1000 * USB_MASS_1_MILLISECOND,\r
-\r
- USB_MASS_CMD_SUCCESS = 0,\r
- USB_MASS_CMD_FAIL,\r
- USB_MASS_CMD_PERSISTENT\r
-} USB_MASS_DEV_CLASS_AND_VALUE;\r
+//\r
+// Usb mass storage class code\r
+//\r
+#define USB_MASS_STORE_CLASS 0x08\r
+\r
+//\r
+// Usb mass storage subclass code, specify the command set used.\r
+//\r
+#define USB_MASS_STORE_RBC 0x01 ///< Reduced Block Commands\r
+#define USB_MASS_STORE_8020I 0x02 ///< SFF-8020i, typically a CD/DVD device\r
+#define USB_MASS_STORE_QIC 0x03 ///< Typically a tape device\r
+#define USB_MASS_STORE_UFI 0x04 ///< Typically a floppy disk driver device\r
+#define USB_MASS_STORE_8070I 0x05 ///< SFF-8070i, typically a floppy disk driver device.\r
+#define USB_MASS_STORE_SCSI 0x06 ///< SCSI transparent command set\r
+\r
+//\r
+// Usb mass storage protocol code, specify the transport protocol\r
+//\r
+#define USB_MASS_STORE_CBI0 0x00 ///< CBI protocol with command completion interrupt\r
+#define USB_MASS_STORE_CBI1 0x01 ///< CBI protocol without command completion interrupt\r
+#define USB_MASS_STORE_BOT 0x50 ///< Bulk-Only Transport\r
+\r
+#define USB_MASS_1_MILLISECOND 1000\r
+#define USB_MASS_1_SECOND (1000 * USB_MASS_1_MILLISECOND)\r
+\r
+#define USB_MASS_CMD_SUCCESS 0\r
+#define USB_MASS_CMD_FAIL 1\r
+#define USB_MASS_CMD_PERSISTENT 2\r
\r
/**\r
Initializes USB transport protocol.\r
Implementation of the command set of USB Mass Storage Specification\r
for Bootability, Revision 1.0.\r
\r
-Copyright (c) 2007 - 2008, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
case USB_BOOT_SENSE_NOT_READY:\r
Status = EFI_DEVICE_ERROR;\r
- if (SenseData.ASC == USB_BOOT_ASC_NO_MEDIA) {\r
+ if (SenseData.Asc == USB_BOOT_ASC_NO_MEDIA) {\r
Media->MediaPresent = FALSE;\r
Status = EFI_NO_MEDIA;\r
- } else if (SenseData.ASC == USB_BOOT_ASC_NOT_READY) {\r
+ } else if (SenseData.Asc == USB_BOOT_ASC_NOT_READY) {\r
Status = EFI_NOT_READY;\r
}\r
break;\r
\r
case USB_BOOT_SENSE_UNIT_ATTENTION:\r
Status = EFI_DEVICE_ERROR;\r
- if (SenseData.ASC == USB_BOOT_ASC_MEDIA_CHANGE) {\r
+ if (SenseData.Asc == USB_BOOT_ASC_MEDIA_CHANGE) {\r
//\r
// If MediaChange, reset ReadOnly and new MediaId\r
//\r
DEBUG ((EFI_D_INFO, "UsbBootRequestSense: (%r) with sense key %x/%x/%x\n",\r
Status,\r
USB_BOOT_SENSE_KEY (SenseData.SenseKey),\r
- SenseData.ASC,\r
- SenseData.ASCQ\r
+ SenseData.Asc,\r
+ SenseData.Ascq\r
));\r
\r
return Status;\r
Definition of the command set of USB Mass Storage Specification\r
for Bootability, Revision 1.0.\r
\r
-Copyright (c) 2007 - 2008, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "UsbMass.h"\r
\r
-typedef enum {\r
- //\r
- // The opcodes of various USB boot commands:\r
- // INQUIRY/REQUEST_SENSE are "No Timeout Commands" as specified\r
- // by Multi-Media Commands (MMC) set.\r
- // Others are "Group 1 Timeout Commands". That is,\r
- // they should be retried if driver is ready. \r
- //\r
- USB_BOOT_INQUIRY_OPCODE = 0x12,\r
- USB_BOOT_REQUEST_SENSE_OPCODE = 0x03,\r
- USB_BOOT_MODE_SENSE10_OPCODE = 0x5A,\r
- USB_BOOT_READ_CAPACITY_OPCODE = 0x25,\r
- USB_BOOT_TEST_UNIT_READY_OPCODE = 0x00,\r
- USB_BOOT_READ10_OPCODE = 0x28,\r
- USB_BOOT_WRITE10_OPCODE = 0x2A,\r
-\r
- USB_SCSI_MODE_SENSE6_OPCODE = 0x1A,\r
- \r
- //\r
- // The Sense Key part of the sense data. Sense data has three levels:\r
- // Sense key, Additional Sense Code and Additional Sense Code Qualifier\r
- //\r
- USB_BOOT_SENSE_NO_SENSE = 0x00, ///< No sense key\r
- USB_BOOT_SENSE_RECOVERED = 0x01, ///< Last command succeed with recovery actions\r
- USB_BOOT_SENSE_NOT_READY = 0x02, ///< Device not ready\r
- USB_BOOT_SNESE_MEDIUM_ERROR = 0X03, ///< Failed probably because flaw in the media\r
- USB_BOOT_SENSE_HARDWARE_ERROR = 0X04, ///< Non-recoverable hardware failure\r
- USB_BOOT_SENSE_ILLEGAL_REQUEST = 0X05, ///< Illegal parameters in the request\r
- USB_BOOT_SENSE_UNIT_ATTENTION = 0X06, ///< Removable medium may have been changed\r
- USB_BOOT_SENSE_DATA_PROTECT = 0X07, ///< Write protected\r
- USB_BOOT_SENSE_BLANK_CHECK = 0X08, ///< Blank/non-blank medium while reading/writing\r
- USB_BOOT_SENSE_VENDOR = 0X09, ///< Vendor specific sense key\r
- USB_BOOT_SENSE_ABORTED = 0X0B, ///< Command aborted by the device\r
- USB_BOOT_SENSE_VOLUME_OVERFLOW = 0x0D, ///< Partition overflow\r
- USB_BOOT_SENSE_MISCOMPARE = 0x0E, ///< Source data mis-match while verfying.\r
-\r
- USB_BOOT_ASC_NOT_READY = 0x04,\r
- USB_BOOT_ASC_NO_MEDIA = 0x3A,\r
- USB_BOOT_ASC_MEDIA_CHANGE = 0x28,\r
-\r
- //\r
- // Supported PDT codes, or Peripheral Device Type\r
- //\r
- USB_PDT_DIRECT_ACCESS = 0x00, ///< Direct access device\r
- USB_PDT_CDROM = 0x05, ///< CDROM\r
- USB_PDT_OPTICAL = 0x07, ///< Non-CD optical disks\r
- USB_PDT_SIMPLE_DIRECT = 0x0E, ///< Simplified direct access device\r
- \r
- //\r
- // Other parameters, Max carried size is 512B * 128 = 64KB\r
- //\r
- USB_BOOT_IO_BLOCKS = 128,\r
-\r
- //\r
- // Retry mass command times, set by experience\r
- //\r
- USB_BOOT_COMMAND_RETRY = 5,\r
- USB_BOOT_INIT_MEDIA_RETRY = 5,\r
-\r
- //\r
- // Wait for unit ready command, set by experience\r
- //\r
- USB_BOOT_RETRY_UNIT_READY_STALL = 500 * USB_MASS_1_MILLISECOND,\r
-\r
- //\r
- // Mass command timeout, refers to specification[USB20-9.2.6.1]\r
- //\r
- // USB2.0 Spec define the up-limit timeout 5s for all command. USB floppy, \r
- // USB CD-Rom and iPod devices are much slower than USB key when reponse \r
- // most of commands, So we set 5s as timeout here.\r
- // \r
- USB_BOOT_GENERAL_CMD_TIMEOUT = 5 * USB_MASS_1_SECOND\r
-}USB_BOOT_OPTCODE;\r
+//\r
+// The opcodes of various USB boot commands:\r
+// INQUIRY/REQUEST_SENSE are "No Timeout Commands" as specified\r
+// by Multi-Media Commands (MMC) set.\r
+// Others are "Group 1 Timeout Commands". That is,\r
+// they should be retried if driver is ready. \r
+//\r
+#define USB_BOOT_INQUIRY_OPCODE 0x12\r
+#define USB_BOOT_REQUEST_SENSE_OPCODE 0x03\r
+#define USB_BOOT_MODE_SENSE10_OPCODE 0x5A\r
+#define USB_BOOT_READ_CAPACITY_OPCODE 0x25\r
+#define USB_BOOT_TEST_UNIT_READY_OPCODE 0x00\r
+#define USB_BOOT_READ10_OPCODE 0x28\r
+#define USB_BOOT_WRITE10_OPCODE 0x2A\r
+\r
+#define USB_SCSI_MODE_SENSE6_OPCODE 0x1A\r
+\r
+//\r
+// The Sense Key part of the sense data. Sense data has three levels:\r
+// Sense key, Additional Sense Code and Additional Sense Code Qualifier\r
+//\r
+#define USB_BOOT_SENSE_NO_SENSE 0x00 ///< No sense key\r
+#define USB_BOOT_SENSE_RECOVERED 0x01 ///< Last command succeed with recovery actions\r
+#define USB_BOOT_SENSE_NOT_READY 0x02 ///< Device not ready\r
+#define USB_BOOT_SNESE_MEDIUM_ERROR 0X03 ///< Failed probably because flaw in the media\r
+#define USB_BOOT_SENSE_HARDWARE_ERROR 0X04 ///< Non-recoverable hardware failure\r
+#define USB_BOOT_SENSE_ILLEGAL_REQUEST 0X05 ///< Illegal parameters in the request\r
+#define USB_BOOT_SENSE_UNIT_ATTENTION 0X06 ///< Removable medium may have been changed\r
+#define USB_BOOT_SENSE_DATA_PROTECT 0X07 ///< Write protected\r
+#define USB_BOOT_SENSE_BLANK_CHECK 0X08 ///< Blank/non-blank medium while reading/writing\r
+#define USB_BOOT_SENSE_VENDOR 0X09 ///< Vendor specific sense key\r
+#define USB_BOOT_SENSE_ABORTED 0X0B ///< Command aborted by the device\r
+#define USB_BOOT_SENSE_VOLUME_OVERFLOW 0x0D ///< Partition overflow\r
+#define USB_BOOT_SENSE_MISCOMPARE 0x0E ///< Source data mis-match while verfying.\r
+\r
+#define USB_BOOT_ASC_NOT_READY 0x04\r
+#define USB_BOOT_ASC_NO_MEDIA 0x3A\r
+#define USB_BOOT_ASC_MEDIA_CHANGE 0x28\r
+\r
+//\r
+// Supported PDT codes, or Peripheral Device Type\r
+//\r
+#define USB_PDT_DIRECT_ACCESS 0x00 ///< Direct access device\r
+#define USB_PDT_CDROM 0x05 ///< CDROM\r
+#define USB_PDT_OPTICAL 0x07 ///< Non-CD optical disks\r
+#define USB_PDT_SIMPLE_DIRECT 0x0E ///< Simplified direct access device\r
+\r
+//\r
+// Other parameters, Max carried size is 512B * 128 = 64KB\r
+//\r
+#define USB_BOOT_IO_BLOCKS 128\r
+\r
+//\r
+// Retry mass command times, set by experience\r
+//\r
+#define USB_BOOT_COMMAND_RETRY 5\r
+#define USB_BOOT_INIT_MEDIA_RETRY 5\r
+\r
+//\r
+// Wait for unit ready command, set by experience\r
+//\r
+#define USB_BOOT_RETRY_UNIT_READY_STALL (500 * USB_MASS_1_MILLISECOND)\r
+\r
+//\r
+// Mass command timeout, refers to specification[USB20-9.2.6.1]\r
+//\r
+// USB2.0 Spec define the up-limit timeout 5s for all command. USB floppy, \r
+// USB CD-Rom and iPod devices are much slower than USB key when reponse \r
+// most of commands, So we set 5s as timeout here.\r
+// \r
+#define USB_BOOT_GENERAL_CMD_TIMEOUT (5 * USB_MASS_1_SECOND)\r
\r
//\r
// The required commands are INQUIRY, READ CAPACITY, TEST UNIT READY,\r
UINT8 Infor[4];\r
UINT8 AddLen; ///< Additional Sense length, 10\r
UINT8 Reserved1[4];\r
- UINT8 ASC; ///< Additional Sense Code\r
- UINT8 ASCQ; ///< Additional Sense Code Qualifier\r
+ UINT8 Asc; ///< Additional Sense Code\r
+ UINT8 Ascq; ///< Additional Sense Code Qualifier\r
UINT8 Reserverd2[4];\r
} USB_BOOT_REQUEST_SENSE_DATA;\r
\r
based on the "Universal Serial Bus Mass Storage Class Bulk-Only\r
Transport" Revision 1.0, September 31, 1999.\r
\r
-Copyright (c) 2007 - 2008, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
extern USB_MASS_TRANSPORT mUsbBotTransport;\r
\r
-typedef enum {\r
- //\r
- // Usb Bulk-Only class specfic request\r
- //\r
- USB_BOT_RESET_REQUEST = 0xFF, ///< Bulk-Only Mass Storage Reset\r
- USB_BOT_GETLUN_REQUEST = 0xFE, ///< Get Max Lun\r
- USB_BOT_CBW_SIGNATURE = 0x43425355, ///< dCBWSignature, tag the packet as CBW\r
- USB_BOT_CSW_SIGNATURE = 0x53425355, ///< dCSWSignature, tag the packet as CSW\r
- USB_BOT_MAX_LUN = 0x0F, ///< Lun number is from 0 to 15\r
- USB_BOT_MAX_CMDLEN = 16, ///< Maxium number of command from command set\r
-\r
- //\r
- // Usb BOT command block status values\r
- //\r
- USB_BOT_COMMAND_OK = 0x00, ///< Command passed, good status\r
- USB_BOT_COMMAND_FAILED = 0x01, ///< Command failed\r
- USB_BOT_COMMAND_ERROR = 0x02, ///< Phase error, need to reset the device\r
-\r
- //\r
- // Usb Bot retry to get CSW, refers to specification[BOT10-5.3, it says 2 times]\r
- //\r
- USB_BOT_RECV_CSW_RETRY = 3,\r
-\r
- //\r
- // Usb Bot wait device reset complete, set by experience\r
- // \r
- USB_BOT_RESET_DEVICE_STALL = 100 * USB_MASS_1_MILLISECOND,\r
- \r
- //\r
- // Usb Bot transport timeout, set by experience\r
- //\r
- USB_BOT_SEND_CBW_TIMEOUT = 3 * USB_MASS_1_SECOND,\r
- USB_BOT_RECV_CSW_TIMEOUT = 3 * USB_MASS_1_SECOND,\r
- USB_BOT_RESET_DEVICE_TIMEOUT = 3 * USB_MASS_1_SECOND\r
-} USB_BOT_SUBCLASS;\r
+//\r
+// Usb Bulk-Only class specfic request\r
+//\r
+#define USB_BOT_RESET_REQUEST 0xFF ///< Bulk-Only Mass Storage Reset\r
+#define USB_BOT_GETLUN_REQUEST 0xFE ///< Get Max Lun\r
+#define USB_BOT_CBW_SIGNATURE 0x43425355 ///< dCBWSignature, tag the packet as CBW\r
+#define USB_BOT_CSW_SIGNATURE 0x53425355 ///< dCSWSignature, tag the packet as CSW\r
+#define USB_BOT_MAX_LUN 0x0F ///< Lun number is from 0 to 15\r
+#define USB_BOT_MAX_CMDLEN 16 ///< Maxium number of command from command set\r
+\r
+//\r
+// Usb BOT command block status values\r
+//\r
+#define USB_BOT_COMMAND_OK 0x00 ///< Command passed, good status\r
+#define USB_BOT_COMMAND_FAILED 0x01 ///< Command failed\r
+#define USB_BOT_COMMAND_ERROR 0x02 ///< Phase error, need to reset the device\r
+\r
+//\r
+// Usb Bot retry to get CSW, refers to specification[BOT10-5.3, it says 2 times]\r
+//\r
+#define USB_BOT_RECV_CSW_RETRY 3\r
+\r
+//\r
+// Usb Bot wait device reset complete, set by experience\r
+// \r
+#define USB_BOT_RESET_DEVICE_STALL (100 * USB_MASS_1_MILLISECOND)\r
+\r
+//\r
+// Usb Bot transport timeout, set by experience\r
+//\r
+#define USB_BOT_SEND_CBW_TIMEOUT (3 * USB_MASS_1_SECOND)\r
+#define USB_BOT_RECV_CSW_TIMEOUT (3 * USB_MASS_1_SECOND)\r
+#define USB_BOT_RESET_DEVICE_TIMEOUT (3 * USB_MASS_1_SECOND)\r
\r
#pragma pack(1)\r
///\r
Defination for the USB mass storage Control/Bulk/Interrupt (CBI) transport,\r
according to USB Mass Storage Class Control/Bulk/Interrupt (CBI) Transport, Revision 1.1.\r
\r
-Copyright (c) 2007 - 2008, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
extern USB_MASS_TRANSPORT mUsbCbi0Transport;\r
extern USB_MASS_TRANSPORT mUsbCbi1Transport;\r
\r
-typedef enum {\r
- USB_CBI_MAX_PACKET_NUM = 16,\r
- USB_CBI_RESET_CMD_LEN = 12,\r
-\r
- //\r
- // USB CBI retry C/B/I transport times, set by experience\r
- //\r
- USB_CBI_MAX_RETRY = 3,\r
-\r
- //\r
- // Time to wait for USB CBI reset to complete, set by experience\r
- // \r
- USB_CBI_RESET_DEVICE_STALL = 50 * USB_MASS_1_MILLISECOND,\r
-\r
- //\r
- // USB CBI transport timeout, set by experience\r
- //\r
- USB_CBI_RESET_DEVICE_TIMEOUT = 1 * USB_MASS_1_SECOND\r
-} USB_CBI_DATA;\r
+#define USB_CBI_MAX_PACKET_NUM 16\r
+#define USB_CBI_RESET_CMD_LEN 12\r
+//\r
+// USB CBI retry C/B/I transport times, set by experience\r
+//\r
+#define USB_CBI_MAX_RETRY 3\r
+//\r
+// Time to wait for USB CBI reset to complete, set by experience\r
+// \r
+#define USB_CBI_RESET_DEVICE_STALL (50 * USB_MASS_1_MILLISECOND)\r
+//\r
+// USB CBI transport timeout, set by experience\r
+//\r
+#define USB_CBI_RESET_DEVICE_TIMEOUT (1 * USB_MASS_1_SECOND)\r
\r
typedef struct {\r
//\r
/** @file\r
Helper routine and corresponding data struct used by USB Mouse Absolute Pointer Driver.\r
\r
-Copyright (c) 2004 - 2008, Intel Corporation\r
+Copyright (c) 2004 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
///\r
/// General HID Item structure\r
///\r
+\r
+typedef union {\r
+ UINT8 U8;\r
+ UINT16 U16;\r
+ UINT32 U32;\r
+ INT8 I8;\r
+ INT16 I16;\r
+ INT32 I32;\r
+ UINT8 *LongData;\r
+} HID_DATA;\r
+\r
typedef struct {\r
- UINT16 Format;\r
- UINT8 Size;\r
- UINT8 Type;\r
- UINT8 Tag;\r
- union {\r
- UINT8 U8;\r
- UINT16 U16;\r
- UINT32 U32;\r
- INT8 I8;\r
- INT16 I16;\r
- INT32 I32;\r
- UINT8 *LongData;\r
- } Data;\r
+ UINT16 Format;\r
+ UINT8 Size;\r
+ UINT8 Type;\r
+ UINT8 Tag;\r
+ HID_DATA Data;\r
} HID_ITEM;\r
\r
#define USB_MOUSE_ABSOLUTE_POINTER_DEV_FROM_MOUSE_PROTOCOL(a) \\r
/** @file\r
Helper routine and corresponding data struct used by USB Mouse Driver.\r
\r
-Copyright (c) 2004 - 2008, Intel Corporation\r
+Copyright (c) 2004 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
///\r
/// General HID Item structure\r
///\r
+\r
+typedef union {\r
+ UINT8 U8;\r
+ UINT16 U16;\r
+ UINT32 U32;\r
+ INT8 I8;\r
+ INT16 I16;\r
+ INT32 I32;\r
+ UINT8 *LongData;\r
+} HID_DATA;\r
+\r
typedef struct {\r
- UINT16 Format;\r
- UINT8 Size;\r
- UINT8 Type;\r
- UINT8 Tag;\r
- union {\r
- UINT8 U8;\r
- UINT16 U16;\r
- UINT32 U32;\r
- INT8 I8;\r
- INT16 I16;\r
- INT32 I32;\r
- UINT8 *LongData;\r
- } Data;\r
+ UINT16 Format;\r
+ UINT8 Size;\r
+ UINT8 Type;\r
+ UINT8 Tag;\r
+ HID_DATA Data;\r
} HID_ITEM;\r
\r
#define USB_MOUSE_DEV_FROM_MOUSE_PROTOCOL(a) \\r
/** @file\r
UEFI Event support functions and structure.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
// EFI_EVENT\r
//\r
+\r
+///\r
+/// Timer event information\r
+///\r
+typedef struct {\r
+ LIST_ENTRY Link;\r
+ UINT64 TriggerTime;\r
+ UINT64 Period;\r
+} TIMER_EVENT_INFO;\r
+\r
#define EVENT_SIGNATURE SIGNATURE_32('e','v','n','t')\r
typedef struct {\r
UINTN Signature;\r
///\r
/// A list of all runtime events\r
///\r
- EFI_RUNTIME_EVENT_ENTRY RuntimeData;\r
- ///\r
- /// Information by event type\r
- ///\r
- union {\r
- ///\r
- /// For timer events\r
- ///\r
- struct {\r
- LIST_ENTRY Link;\r
- UINT64 TriggerTime;\r
- UINT64 Period;\r
- } Timer;\r
- } u;\r
-\r
+ EFI_RUNTIME_EVENT_ENTRY RuntimeData;\r
+ TIMER_EVENT_INFO Timer;\r
} IEVENT;\r
\r
//\r
/** @file\r
Core Timer Services\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
// Get the timer's trigger time\r
//\r
- TriggerTime = Event->u.Timer.TriggerTime;\r
+ TriggerTime = Event->Timer.TriggerTime;\r
\r
//\r
// Insert the timer into the timer database in assending sorted order\r
//\r
for (Link = mEfiTimerList.ForwardLink; Link != &mEfiTimerList; Link = Link->ForwardLink) {\r
- Event2 = CR (Link, IEVENT, u.Timer.Link, EVENT_SIGNATURE);\r
+ Event2 = CR (Link, IEVENT, Timer.Link, EVENT_SIGNATURE);\r
\r
- if (Event2->u.Timer.TriggerTime > TriggerTime) {\r
+ if (Event2->Timer.TriggerTime > TriggerTime) {\r
break;\r
}\r
}\r
\r
- InsertTailList (Link, &Event->u.Timer.Link);\r
+ InsertTailList (Link, &Event->Timer.Link);\r
}\r
\r
/**\r
SystemTime = CoreCurrentSystemTime ();\r
\r
while (!IsListEmpty (&mEfiTimerList)) {\r
- Event = CR (mEfiTimerList.ForwardLink, IEVENT, u.Timer.Link, EVENT_SIGNATURE);\r
+ Event = CR (mEfiTimerList.ForwardLink, IEVENT, Timer.Link, EVENT_SIGNATURE);\r
\r
//\r
// If this timer is not expired, then we're done\r
//\r
- if (Event->u.Timer.TriggerTime > SystemTime) {\r
+ if (Event->Timer.TriggerTime > SystemTime) {\r
break;\r
}\r
\r
// Remove this timer from the timer queue\r
//\r
\r
- RemoveEntryList (&Event->u.Timer.Link);\r
- Event->u.Timer.Link.ForwardLink = NULL;\r
+ RemoveEntryList (&Event->Timer.Link);\r
+ Event->Timer.Link.ForwardLink = NULL;\r
\r
//\r
// Signal it\r
//\r
// If this is a periodic timer, set it\r
//\r
- if (Event->u.Timer.Period) {\r
+ if (Event->Timer.Period != 0) {\r
//\r
// Compute the timers new trigger time\r
//\r
- Event->u.Timer.TriggerTime = Event->u.Timer.TriggerTime + Event->u.Timer.Period;\r
+ Event->Timer.TriggerTime = Event->Timer.TriggerTime + Event->Timer.Period;\r
\r
//\r
// If that's before now, then reset the timer to start from now\r
//\r
- if (Event->u.Timer.TriggerTime <= SystemTime) {\r
- Event->u.Timer.TriggerTime = SystemTime;\r
+ if (Event->Timer.TriggerTime <= SystemTime) {\r
+ Event->Timer.TriggerTime = SystemTime;\r
CoreSignalEvent (mEfiCheckTimerEvent);\r
}\r
\r
// to process it\r
//\r
if (!IsListEmpty (&mEfiTimerList)) {\r
- Event = CR (mEfiTimerList.ForwardLink, IEVENT, u.Timer.Link, EVENT_SIGNATURE);\r
+ Event = CR (mEfiTimerList.ForwardLink, IEVENT, Timer.Link, EVENT_SIGNATURE);\r
\r
- if (Event->u.Timer.TriggerTime <= mEfiSystemTime) {\r
+ if (Event->Timer.TriggerTime <= mEfiSystemTime) {\r
CoreSignalEvent (mEfiCheckTimerEvent);\r
}\r
}\r
//\r
// If the timer is queued to the timer database, remove it\r
//\r
- if (Event->u.Timer.Link.ForwardLink != NULL) {\r
- RemoveEntryList (&Event->u.Timer.Link);\r
- Event->u.Timer.Link.ForwardLink = NULL;\r
+ if (Event->Timer.Link.ForwardLink != NULL) {\r
+ RemoveEntryList (&Event->Timer.Link);\r
+ Event->Timer.Link.ForwardLink = NULL;\r
}\r
\r
- Event->u.Timer.TriggerTime = 0;\r
- Event->u.Timer.Period = 0;\r
+ Event->Timer.TriggerTime = 0;\r
+ Event->Timer.Period = 0;\r
\r
if (Type != TimerCancel) {\r
\r
if (Type == TimerPeriodic) {\r
- Event->u.Timer.Period = TriggerTime;\r
+ Event->Timer.Period = TriggerTime;\r
}\r
\r
- Event->u.Timer.TriggerTime = CoreCurrentSystemTime () + TriggerTime;\r
+ Event->Timer.TriggerTime = CoreCurrentSystemTime () + TriggerTime;\r
CoreInsertEventTimer (Event);\r
\r
if (TriggerTime == 0) {\r
Console Platform DXE Driver, install Console Device Guids and update Console\r
Environment Variables.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
Status = ConPlatformUpdateDeviceVariable (\r
L"ConIn",\r
DevicePath,\r
- CHECK\r
+ Check\r
);\r
if (!EFI_ERROR (Status)) {\r
IsInConInVariable = TRUE;\r
ConPlatformUpdateDeviceVariable (\r
L"ConInDev",\r
DevicePath,\r
- APPEND\r
+ Append\r
);\r
}\r
} else {\r
ConPlatformUpdateDeviceVariable (\r
L"ConInDev",\r
DevicePath,\r
- APPEND\r
+ Append\r
);\r
\r
//\r
Status = ConPlatformUpdateDeviceVariable (\r
L"ConOut",\r
DevicePath,\r
- CHECK\r
+ Check\r
);\r
if (!EFI_ERROR (Status)) {\r
IsInConOutVariable = TRUE;\r
Status = ConPlatformUpdateDeviceVariable (\r
L"ErrOut",\r
DevicePath,\r
- CHECK\r
+ Check\r
);\r
if (!EFI_ERROR (Status)) {\r
IsInErrOutVariable = TRUE;\r
ConPlatformUpdateDeviceVariable (\r
L"ConOutDev",\r
DevicePath,\r
- APPEND\r
+ Append\r
);\r
}\r
//\r
ConPlatformUpdateDeviceVariable (\r
L"ErrOutDev",\r
DevicePath,\r
- APPEND\r
+ Append\r
);\r
}\r
} else {\r
ConPlatformUpdateDeviceVariable (\r
L"ConOutDev",\r
DevicePath,\r
- APPEND\r
+ Append\r
);\r
//\r
// Then append the device path to the ErrOutDev environment variable\r
ConPlatformUpdateDeviceVariable (\r
L"ErrOutDev",\r
DevicePath,\r
- APPEND\r
+ Append\r
);\r
\r
//\r
ConPlatformUpdateDeviceVariable (\r
L"ConInDev",\r
DevicePath,\r
- DELETE\r
+ Delete\r
);\r
}\r
\r
ConPlatformUpdateDeviceVariable (\r
L"ConOutDev",\r
DevicePath,\r
- DELETE\r
+ Delete\r
);\r
ConPlatformUpdateDeviceVariable (\r
L"ErrOutDev",\r
DevicePath,\r
- DELETE\r
+ Delete\r
);\r
}\r
\r
//\r
VariableDevicePath = ConPlatformGetVariable (VariableName);\r
\r
- if (Operation != DELETE) {\r
+ if (Operation != Delete) {\r
//\r
// Match specified DevicePath in Console Variable.\r
// \r
FALSE\r
);\r
\r
- if ((Operation == CHECK) || (!EFI_ERROR (Status))) {\r
+ if ((Operation == Check) || (!EFI_ERROR (Status))) {\r
//\r
// Branch here includes 2 cases:\r
// 1. Operation is CHECK, simply return Status.\r
/** @file\r
Header file for Console Platfrom DXE Driver.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
\r
typedef enum {\r
- CHECK,\r
- APPEND,\r
- DELETE\r
+ Check,\r
+ Append,\r
+ Delete\r
} CONPLATFORM_VAR_OPERATION;\r
\r
/**\r
/** @file\r
Generic debug support macros, typedefs and prototypes for IA32/x64.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
+Copyright (c) 2006 - 2010, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
VOID\r
);\r
\r
+typedef\r
+VOID\r
+(EFIAPI *CALLBACK_FUNC) (\r
+ );\r
+\r
typedef struct {\r
IA32_IDT_GATE_DESCRIPTOR OrigDesc;\r
DEBUG_PROC OrigVector;\r
IA32_IDT_GATE_DESCRIPTOR NewDesc;\r
DEBUG_PROC StubEntry;\r
- VOID (EFIAPI *RegisteredCallback) ();\r
+ CALLBACK_FUNC RegisteredCallback;\r
} IDT_ENTRY;\r
\r
extern UINT8 InterruptEntryStub[];\r
**/\r
EFI_STATUS\r
ManageIdtEntryTable (\r
- VOID (EFIAPI *NewCallback)(),\r
+ CALLBACK_FUNC NewCallback,\r
EFI_EXCEPTION_TYPE ExceptionType\r
);\r
\r
VOID\r
HookEntry (\r
IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN VOID (EFIAPI *NewCallback) ()\r
+ IN CALLBACK_FUNC NewCallback\r
);\r
\r
/**\r
/** @file\r
IA32/x64 generic functions to support Debug Support protocol.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation\r
+Copyright (c) 2006 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
VOID\r
HookEntry (\r
IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN VOID (EFIAPI *NewCallback) ()\r
+ IN CALLBACK_FUNC NewCallback\r
)\r
{\r
BOOLEAN OldIntFlagState;\r
/** @file\r
IA32 specific functions to support Debug Support protocol.\r
\r
-Copyright (c) 2008 - 2009, Intel Corporation\r
+Copyright (c) 2008 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
**/\r
EFI_STATUS\r
ManageIdtEntryTable (\r
- VOID (EFIAPI *NewCallback)(),\r
+ CALLBACK_FUNC NewCallback,\r
EFI_EXCEPTION_TYPE ExceptionType\r
)\r
{\r
/** @file\r
IPF specific functions to support Debug Support protocol.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation\r
+Copyright (c) 2006 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define NUM_IVT_ENTRIES 64\r
\r
typedef struct {\r
- BUNDLE OrigBundles[NUM_BUNDLES_IN_STUB];\r
- VOID (*RegisteredCallback) ();\r
+ BUNDLE OrigBundles[NUM_BUNDLES_IN_STUB];\r
+ CALLBACK_FUNC RegisteredCallback;\r
} IVT_ENTRY;\r
\r
IVT_ENTRY IvtEntryTable[NUM_IVT_ENTRIES];\r
ManageIvtEntryTable (\r
IN EFI_EXCEPTION_TYPE ExceptionType,\r
IN BUNDLE NewBundles[NUM_BUNDLES_IN_STUB],\r
- IN VOID (*NewCallback) ()\r
+ IN CALLBACK_FUNC NewCallback\r
)\r
{\r
BUNDLE *B0Ptr;\r
HookEntry (\r
IN EFI_EXCEPTION_TYPE ExceptionType,\r
IN BUNDLE NewBundles[4],\r
- IN VOID (*NewCallback) ()\r
+ IN CALLBACK_FUNC NewCallback\r
)\r
{\r
BUNDLE *FixupBundle;\r
// fixup IVT entry so it stores its index and whether or not to chain...\r
//\r
FixupBundle = B0Ptr + 2;\r
- FixupBundle->high |= ExceptionType << 36;\r
+ FixupBundle->High |= ExceptionType << 36;\r
\r
InstructionCacheFlush (B0Ptr, 5);\r
IvtEntryTable[ExceptionType].RegisteredCallback = NewCallback;\r
**/\r
VOID\r
ChainExternalInterrupt (\r
- IN VOID (*NewCallback) ()\r
+ IN CALLBACK_FUNC NewCallback\r
)\r
{\r
VOID *Start;\r
/** @file\r
IPF specific types, macros, and definitions for Debug Support Driver.\r
\r
-Copyright (c) 2004 - 2008, Intel Corporation\r
+Copyright (c) 2004 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define EFI_ISA IsaIpf\r
\r
typedef struct {\r
- UINT64 low;\r
- UINT64 high;\r
+ UINT64 Low;\r
+ UINT64 High;\r
} BUNDLE;\r
\r
+typedef\r
+VOID\r
+(*CALLBACK_FUNC) (\r
+ );\r
+\r
/**\r
IPF specific DebugSupport driver initialization.\r
\r
ManageIvtEntryTable (\r
IN EFI_EXCEPTION_TYPE ExceptionType,\r
IN BUNDLE NewBundles[4],\r
- IN VOID (*NewCallback) ()\r
+ IN CALLBACK_FUNC NewCallback\r
);\r
\r
/**\r
HookEntry (\r
IN EFI_EXCEPTION_TYPE ExceptionType,\r
IN BUNDLE NewBundles[4],\r
- IN VOID (*NewCallback) ()\r
+ IN CALLBACK_FUNC NewCallback\r
);\r
\r
/**\r
**/\r
VOID\r
ChainExternalInterrupt (\r
- IN VOID (*NewCallback) ()\r
+ IN CALLBACK_FUNC NewCallback\r
);\r
\r
/**\r
/** @file\r
X64 specific functions to support Debug Support protocol.\r
\r
-Copyright (c) 2008 - 2009, Intel Corporation\r
+Copyright (c) 2008 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
**/\r
EFI_STATUS\r
ManageIdtEntryTable (\r
- VOID (EFIAPI *NewCallback)(),\r
+ CALLBACK_FUNC NewCallback,\r
EFI_EXCEPTION_TYPE ExceptionType\r
)\r
{\r
/** @file\r
Definition for Device Path Utilities driver\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
IN CHAR16 *DeviceNodeStr\r
);\r
\r
+typedef\r
+VOID\r
+(*DEVICE_PATH_TO_TEXT_FUNC) (\r
+ IN OUT POOL_PRINT *Str,\r
+ IN VOID *DevPath,\r
+ IN BOOLEAN DisplayOnly,\r
+ IN BOOLEAN AllowShortcuts\r
+ );\r
+\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 SubType;\r
- VOID (*Function) (POOL_PRINT *, VOID *, BOOLEAN, BOOLEAN);\r
+ UINT8 Type;\r
+ UINT8 SubType;\r
+ DEVICE_PATH_TO_TEXT_FUNC Function;\r
} DEVICE_PATH_TO_TEXT_TABLE;\r
\r
typedef struct {\r
\r
typedef struct {\r
EFI_DEVICE_PATH_PROTOCOL Header;\r
- UINT32 HID;\r
- UINT32 UID;\r
- UINT32 CID;\r
+ UINT32 Hid;\r
+ UINT32 Uid;\r
+ UINT32 Cid;\r
CHAR8 HidUidCidStr[3];\r
} ACPI_EXTENDED_HID_DEVICE_PATH_WITH_STR;\r
\r
/** @file\r
Contains code that implements the virtual machine.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
StackCorrupted = 1;\r
}\r
\r
- VmPtr->FramePtr = (VOID *) ((UINT8 *) (UINTN) VmPtr->R[0] + 8);\r
+ VmPtr->FramePtr = (VOID *) ((UINT8 *) (UINTN) VmPtr->Gpr[0] + 8);\r
\r
//\r
// Try to get the debug support for EBC\r
EbcDebugSignalException (EXCEPT_EBC_STACK_FAULT, EXCEPTION_FLAG_FATAL, VmPtr);\r
StackCorrupted = 1;\r
}\r
- if ((StackCorrupted == 0) && ((UINT64)VmPtr->R[0] <= (UINT64)(UINTN) VmPtr->StackTop)) {\r
+ if ((StackCorrupted == 0) && ((UINT64)VmPtr->Gpr[0] <= (UINT64)(UINTN) VmPtr->StackTop)) {\r
EbcDebugSignalException (EXCEPT_EBC_STACK_FAULT, EXCEPTION_FLAG_FATAL, VmPtr);\r
StackCorrupted = 1;\r
}\r
//\r
// Indirect form @R2. Compute address of operand2\r
//\r
- Source = (UINTN) (VmPtr->R[OPERAND2_REGNUM (Operands)] + Index64Op2);\r
+ Source = (UINTN) (VmPtr->Gpr[OPERAND2_REGNUM (Operands)] + Index64Op2);\r
//\r
// Now get the data from the source. Always 0-extend and let the compiler\r
// sign-extend where required.\r
//\r
// Not indirect source: MOVxx {@}Rx, Ry [Index]\r
//\r
- Data64 = VmPtr->R[OPERAND2_REGNUM (Operands)] + Index64Op2;\r
+ Data64 = VmPtr->Gpr[OPERAND2_REGNUM (Operands)] + Index64Op2;\r
//\r
// Did Operand2 have an index? If so, treat as two signed values since\r
// indexes are signed values.\r
//\r
// Reuse the Source variable to now be dest.\r
//\r
- Source = (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Index64Op1);\r
+ Source = (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index64Op1);\r
//\r
// Do the write based on the size\r
//\r
// Direct storage in register. Clear unused bits and store back to\r
// register.\r
//\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = Data64 & DataMask;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = Data64 & DataMask;\r
}\r
//\r
// Advance the instruction pointer\r
// 16-8 = Major version\r
// 7-0 = Minor version\r
//\r
- VmPtr->R[7] = GetVmVersion ();\r
+ VmPtr->Gpr[7] = GetVmVersion ();\r
break;\r
\r
//\r
// After we're done, *(UINT64 *)R7 will be the address of the new thunk.\r
//\r
case 5:\r
- Offset = (INT32) VmReadMem32 (VmPtr, (UINTN) VmPtr->R[7]);\r
- U64EbcEntryPoint = (UINT64) (VmPtr->R[7] + Offset + 4);\r
+ Offset = (INT32) VmReadMem32 (VmPtr, (UINTN) VmPtr->Gpr[7]);\r
+ U64EbcEntryPoint = (UINT64) (VmPtr->Gpr[7] + Offset + 4);\r
EbcEntryPoint = (VOID *) (UINTN) U64EbcEntryPoint;\r
\r
//\r
//\r
// Finally replace the EBC entry point memory with the thunk address\r
//\r
- VmWriteMem64 (VmPtr, (UINTN) VmPtr->R[7], (UINT64) (UINTN) Thunk);\r
+ VmWriteMem64 (VmPtr, (UINTN) VmPtr->Gpr[7], (UINT64) (UINTN) Thunk);\r
break;\r
\r
//\r
// Compiler setting version per value in R7\r
//\r
case 6:\r
- VmPtr->CompilerVersion = (UINT32) VmPtr->R[7];\r
+ VmPtr->CompilerVersion = (UINT32) VmPtr->Gpr[7];\r
//\r
// Check compiler version against VM version?\r
//\r
Mask64 = (UINT64)~0;\r
}\r
\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = ImmData64 & Mask64;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = ImmData64 & Mask64;\r
} else {\r
//\r
// Get the address then write back based on size of the move\r
//\r
- Op1 = (UINT64) VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16;\r
+ Op1 = (UINT64) VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16;\r
if ((Operands & MOVI_M_MOVEWIDTH) == MOVI_MOVEWIDTH8) {\r
VmWriteMem8 (VmPtr, (UINTN) Op1, (UINT8) ImmData64);\r
} else if ((Operands & MOVI_M_MOVEWIDTH) == MOVI_MOVEWIDTH16) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = ImmedIndex64;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = ImmedIndex64;\r
} else {\r
//\r
// Get the address\r
//\r
- Op1 = (UINT64) VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16;\r
+ Op1 = (UINT64) VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16;\r
VmWriteMemN (VmPtr, (UINTN) Op1, (INTN) ImmedIndex64);\r
}\r
//\r
return EFI_UNSUPPORTED;\r
}\r
\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = (VM_REGISTER) Op2;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = (VM_REGISTER) Op2;\r
} else {\r
//\r
// Get the address = [Rx] + Index16\r
// Write back the result. Always a natural size write, since\r
// we're talking addresses here.\r
//\r
- Op1 = (UINT64) VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16;\r
+ Op1 = (UINT64) VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16;\r
VmWriteMemN (VmPtr, (UINTN) Op1, (UINTN) Op2);\r
}\r
//\r
//\r
// Get the data from the source.\r
//\r
- Op2 = (INT64) ((INTN) (VmPtr->R[OPERAND2_REGNUM (Operands)] + Op2Index));\r
+ Op2 = (INT64) ((INTN) (VmPtr->Gpr[OPERAND2_REGNUM (Operands)] + Op2Index));\r
if (OPERAND2_INDIRECT (Operands)) {\r
Op2 = (INT64) (INTN) VmReadMemN (VmPtr, (UINTN) Op2);\r
}\r
// Now write back the result.\r
//\r
if (!OPERAND1_INDIRECT (Operands)) {\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = Op2;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = Op2;\r
} else {\r
- VmWriteMemN (VmPtr, (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Op1Index), (UINTN) Op2);\r
+ VmWriteMemN (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Op1Index), (UINTN) Op2);\r
}\r
//\r
// Advance the instruction pointer\r
//\r
// Get the data from the source.\r
//\r
- Op2 = (INT64) ((INTN) (VmPtr->R[OPERAND2_REGNUM (Operands)] + Op2Index));\r
+ Op2 = (INT64) ((INTN) (VmPtr->Gpr[OPERAND2_REGNUM (Operands)] + Op2Index));\r
if (OPERAND2_INDIRECT (Operands)) {\r
Op2 = (INT64) (INTN) VmReadMemN (VmPtr, (UINTN) Op2);\r
}\r
// Now write back the result.\r
//\r
if (!OPERAND1_INDIRECT (Operands)) {\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = Op2;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = Op2;\r
} else {\r
- VmWriteMemN (VmPtr, (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Op1Index), (UINTN) Op2);\r
+ VmWriteMemN (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Op1Index), (UINTN) Op2);\r
}\r
//\r
// Advance the instruction pointer\r
// Get the data to push\r
//\r
if (OPERAND1_INDIRECT (Operands)) {\r
- DataN = VmReadMemN (VmPtr, (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16));\r
+ DataN = VmReadMemN (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16));\r
} else {\r
- DataN = (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16);\r
+ DataN = (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16);\r
}\r
//\r
// Adjust the stack down.\r
//\r
- VmPtr->R[0] -= sizeof (UINTN);\r
- VmWriteMemN (VmPtr, (UINTN) VmPtr->R[0], DataN);\r
+ VmPtr->Gpr[0] -= sizeof (UINTN);\r
+ VmWriteMemN (VmPtr, (UINTN) VmPtr->Gpr[0], DataN);\r
return EFI_SUCCESS;\r
}\r
\r
//\r
if ((Opcode & PUSHPOP_M_64) != 0) {\r
if (OPERAND1_INDIRECT (Operands)) {\r
- Data64 = VmReadMem64 (VmPtr, (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16));\r
+ Data64 = VmReadMem64 (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16));\r
} else {\r
- Data64 = (UINT64) VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16;\r
+ Data64 = (UINT64) VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16;\r
}\r
//\r
// Adjust the stack down, then write back the data\r
//\r
- VmPtr->R[0] -= sizeof (UINT64);\r
- VmWriteMem64 (VmPtr, (UINTN) VmPtr->R[0], Data64);\r
+ VmPtr->Gpr[0] -= sizeof (UINT64);\r
+ VmWriteMem64 (VmPtr, (UINTN) VmPtr->Gpr[0], Data64);\r
} else {\r
//\r
// 32-bit data\r
//\r
if (OPERAND1_INDIRECT (Operands)) {\r
- Data32 = VmReadMem32 (VmPtr, (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16));\r
+ Data32 = VmReadMem32 (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16));\r
} else {\r
- Data32 = (UINT32) VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16;\r
+ Data32 = (UINT32) VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16;\r
}\r
//\r
// Adjust the stack down and write the data\r
//\r
- VmPtr->R[0] -= sizeof (UINT32);\r
- VmWriteMem32 (VmPtr, (UINTN) VmPtr->R[0], Data32);\r
+ VmPtr->Gpr[0] -= sizeof (UINT32);\r
+ VmWriteMem32 (VmPtr, (UINTN) VmPtr->Gpr[0], Data32);\r
}\r
\r
return EFI_SUCCESS;\r
//\r
// Read the data off the stack, then adjust the stack pointer\r
//\r
- DataN = VmReadMemN (VmPtr, (UINTN) VmPtr->R[0]);\r
- VmPtr->R[0] += sizeof (UINTN);\r
+ DataN = VmReadMemN (VmPtr, (UINTN) VmPtr->Gpr[0]);\r
+ VmPtr->Gpr[0] += sizeof (UINTN);\r
//\r
// Do the write-back\r
//\r
if (OPERAND1_INDIRECT (Operands)) {\r
- VmWriteMemN (VmPtr, (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16), DataN);\r
+ VmWriteMemN (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16), DataN);\r
} else {\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = (INT64) (UINT64) ((UINTN) DataN + Index16);\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = (INT64) (UINT64) ((UINTN) DataN + Index16);\r
}\r
\r
return EFI_SUCCESS;\r
//\r
// Read the data off the stack, then adjust the stack pointer\r
//\r
- Data64 = VmReadMem64 (VmPtr, (UINTN) VmPtr->R[0]);\r
- VmPtr->R[0] += sizeof (UINT64);\r
+ Data64 = VmReadMem64 (VmPtr, (UINTN) VmPtr->Gpr[0]);\r
+ VmPtr->Gpr[0] += sizeof (UINT64);\r
//\r
// Do the write-back\r
//\r
if (OPERAND1_INDIRECT (Operands)) {\r
- VmWriteMem64 (VmPtr, (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16), Data64);\r
+ VmWriteMem64 (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16), Data64);\r
} else {\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = Data64 + Index16;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = Data64 + Index16;\r
}\r
} else {\r
//\r
// 32-bit pop. Read it off the stack and adjust the stack pointer\r
//\r
- Data32 = (INT32) VmReadMem32 (VmPtr, (UINTN) VmPtr->R[0]);\r
- VmPtr->R[0] += sizeof (UINT32);\r
+ Data32 = (INT32) VmReadMem32 (VmPtr, (UINTN) VmPtr->Gpr[0]);\r
+ VmPtr->Gpr[0] += sizeof (UINT32);\r
//\r
// Do the write-back\r
//\r
if (OPERAND1_INDIRECT (Operands)) {\r
- VmWriteMem32 (VmPtr, (UINTN) (VmPtr->R[OPERAND1_REGNUM (Operands)] + Index16), Data32);\r
+ VmWriteMem32 (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + Index16), Data32);\r
} else {\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = (INT64) Data32 + Index16;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = (INT64) Data32 + Index16;\r
}\r
}\r
\r
// put our return address and frame pointer on the VM stack.\r
//\r
if ((Operands & OPERAND_M_NATIVE_CALL) == 0) {\r
- VmPtr->R[0] -= 8;\r
- VmWriteMemN (VmPtr, (UINTN) VmPtr->R[0], (UINTN) FramePtr);\r
- VmPtr->FramePtr = (VOID *) (UINTN) VmPtr->R[0];\r
- VmPtr->R[0] -= 8;\r
- VmWriteMem64 (VmPtr, (UINTN) VmPtr->R[0], (UINT64) (UINTN) (VmPtr->Ip + Size));\r
+ VmPtr->Gpr[0] -= 8;\r
+ VmWriteMemN (VmPtr, (UINTN) VmPtr->Gpr[0], (UINTN) FramePtr);\r
+ VmPtr->FramePtr = (VOID *) (UINTN) VmPtr->Gpr[0];\r
+ VmPtr->Gpr[0] -= 8;\r
+ VmWriteMem64 (VmPtr, (UINTN) VmPtr->Gpr[0], (UINT64) (UINTN) (VmPtr->Ip + Size));\r
}\r
//\r
// If 64-bit data, then absolute jump only\r
//\r
// Call external function, get the return value, and advance the IP\r
//\r
- EbcLLCALLEX (VmPtr, (UINTN) Immed64, (UINTN) VmPtr->R[0], FramePtr, Size);\r
+ EbcLLCALLEX (VmPtr, (UINTN) Immed64, (UINTN) VmPtr->Gpr[0], FramePtr, Size);\r
}\r
} else {\r
//\r
// Compiler should take care of upper bits if 32-bit machine.\r
//\r
if (OPERAND1_REGNUM (Operands) != 0) {\r
- Immed64 = (UINT64) (UINTN) VmPtr->R[OPERAND1_REGNUM (Operands)];\r
+ Immed64 = (UINT64) (UINTN) VmPtr->Gpr[OPERAND1_REGNUM (Operands)];\r
}\r
//\r
// Get final address\r
// Native call. Relative or absolute?\r
//\r
if ((Operands & OPERAND_M_RELATIVE_ADDR) != 0) {\r
- EbcLLCALLEX (VmPtr, (UINTN) (Immed64 + VmPtr->Ip + Size), (UINTN) VmPtr->R[0], FramePtr, Size);\r
+ EbcLLCALLEX (VmPtr, (UINTN) (Immed64 + VmPtr->Ip + Size), (UINTN) VmPtr->Gpr[0], FramePtr, Size);\r
} else {\r
if ((VmPtr->StopFlags & STOPFLAG_BREAK_ON_CALLEX) != 0) {\r
CpuBreakpoint ();\r
}\r
\r
- EbcLLCALLEX (VmPtr, (UINTN) Immed64, (UINTN) VmPtr->R[0], FramePtr, Size);\r
+ EbcLLCALLEX (VmPtr, (UINTN) Immed64, (UINTN) VmPtr->Gpr[0], FramePtr, Size);\r
}\r
}\r
}\r
// If we're at the top of the stack, then simply set the done\r
// flag and return\r
//\r
- if (VmPtr->StackRetAddr == (UINT64) VmPtr->R[0]) {\r
+ if (VmPtr->StackRetAddr == (UINT64) VmPtr->Gpr[0]) {\r
VmPtr->StopFlags |= STOPFLAG_APP_DONE;\r
} else {\r
//\r
// Pull the return address off the VM app's stack and set the IP\r
// to it\r
//\r
- if (!IS_ALIGNED ((UINTN) VmPtr->R[0], sizeof (UINT16))) {\r
+ if (!IS_ALIGNED ((UINTN) VmPtr->Gpr[0], sizeof (UINT16))) {\r
EbcDebugSignalException (\r
EXCEPT_EBC_ALIGNMENT_CHECK,\r
EXCEPTION_FLAG_FATAL,\r
//\r
// Restore the IP and frame pointer from the stack\r
//\r
- VmPtr->Ip = (VMIP) (UINTN) VmReadMem64 (VmPtr, (UINTN) VmPtr->R[0]);\r
- VmPtr->R[0] += 8;\r
- VmPtr->FramePtr = (VOID *) VmReadMemN (VmPtr, (UINTN) VmPtr->R[0]);\r
- VmPtr->R[0] += 8;\r
+ VmPtr->Ip = (VMIP) (UINTN) VmReadMem64 (VmPtr, (UINTN) VmPtr->Gpr[0]);\r
+ VmPtr->Gpr[0] += 8;\r
+ VmPtr->FramePtr = (VOID *) VmReadMemN (VmPtr, (UINTN) VmPtr->Gpr[0]);\r
+ VmPtr->Gpr[0] += 8;\r
}\r
\r
return EFI_SUCCESS;\r
//\r
// Get the register data we're going to compare to\r
//\r
- Op1 = VmPtr->R[OPERAND1_REGNUM (Operands)];\r
+ Op1 = VmPtr->Gpr[OPERAND1_REGNUM (Operands)];\r
//\r
// Get immediate data\r
//\r
//\r
if (OPERAND2_INDIRECT (Operands)) {\r
if ((Opcode & OPCODE_M_64BIT) != 0) {\r
- Op2 = (INT64) VmReadMem64 (VmPtr, (UINTN) (VmPtr->R[OPERAND2_REGNUM (Operands)] + Index16));\r
+ Op2 = (INT64) VmReadMem64 (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND2_REGNUM (Operands)] + Index16));\r
} else {\r
//\r
// 32-bit operations. 0-extend the values for all cases.\r
//\r
- Op2 = (INT64) (UINT64) ((UINT32) VmReadMem32 (VmPtr, (UINTN) (VmPtr->R[OPERAND2_REGNUM (Operands)] + Index16)));\r
+ Op2 = (INT64) (UINT64) ((UINT32) VmReadMem32 (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND2_REGNUM (Operands)] + Index16)));\r
}\r
} else {\r
- Op2 = VmPtr->R[OPERAND2_REGNUM (Operands)] + Index16;\r
+ Op2 = VmPtr->Gpr[OPERAND2_REGNUM (Operands)] + Index16;\r
}\r
//\r
// Now do the compare\r
//\r
// Get operand1 data we're going to compare to\r
//\r
- Op1 = (INT64) VmPtr->R[OPERAND1_REGNUM (Operands)];\r
+ Op1 = (INT64) VmPtr->Gpr[OPERAND1_REGNUM (Operands)];\r
if (OPERAND1_INDIRECT (Operands)) {\r
//\r
// Indirect operand1. Fetch 32 or 64-bit value based on compare size.\r
//\r
// Now get operand2 (source). It's of format {@}R2 {Index16|Immed16}\r
//\r
- Op2 = (UINT64) VmPtr->R[OPERAND2_REGNUM (Operands)] + Index16;\r
+ Op2 = (UINT64) VmPtr->Gpr[OPERAND2_REGNUM (Operands)] + Index16;\r
if (OPERAND2_INDIRECT (Operands)) {\r
//\r
// Indirect form: @R2 Index16. Fetch as 32- or 64-bit data\r
// Get operand1 (destination and sometimes also an actual operand)\r
// of form {@}R1\r
//\r
- Op1 = VmPtr->R[OPERAND1_REGNUM (Operands)];\r
+ Op1 = VmPtr->Gpr[OPERAND1_REGNUM (Operands)];\r
if (OPERAND1_INDIRECT (Operands)) {\r
if ((Opcode & DATAMANIP_M_64) != 0) {\r
Op1 = VmReadMem64 (VmPtr, (UINTN) Op1);\r
// Write back the result.\r
//\r
if (OPERAND1_INDIRECT (Operands)) {\r
- Op1 = VmPtr->R[OPERAND1_REGNUM (Operands)];\r
+ Op1 = VmPtr->Gpr[OPERAND1_REGNUM (Operands)];\r
if ((Opcode & DATAMANIP_M_64) != 0) {\r
VmWriteMem64 (VmPtr, (UINTN) Op1, Op2);\r
} else {\r
// Storage back to a register. Write back, clearing upper bits (as per\r
// the specification) if 32-bit operation.\r
//\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = Op2;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = Op2;\r
if ((Opcode & DATAMANIP_M_64) == 0) {\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] &= 0xFFFFFFFF;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] &= 0xFFFFFFFF;\r
}\r
}\r
//\r
// Spec states that this instruction will not modify reserved bits in\r
// the flags register.\r
//\r
- VmPtr->Flags = (VmPtr->Flags &~VMFLAGS_ALL_VALID) | (VmPtr->R[OPERAND2_REGNUM (Operands)] & VMFLAGS_ALL_VALID);\r
+ VmPtr->Flags = (VmPtr->Flags &~VMFLAGS_ALL_VALID) | (VmPtr->Gpr[OPERAND2_REGNUM (Operands)] & VMFLAGS_ALL_VALID);\r
break;\r
\r
default:\r
//\r
// Retrieve the value in the flags register, then clear reserved bits\r
//\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = (UINT64) (VmPtr->Flags & VMFLAGS_ALL_VALID);\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = (UINT64) (VmPtr->Flags & VMFLAGS_ALL_VALID);\r
break;\r
\r
//\r
// Get IP -- address of following instruction\r
//\r
case 1:\r
- VmPtr->R[OPERAND1_REGNUM (Operands)] = (UINT64) (UINTN) VmPtr->Ip + 2;\r
+ VmPtr->Gpr[OPERAND1_REGNUM (Operands)] = (UINT64) (UINTN) VmPtr->Ip + 2;\r
break;\r
\r
default:\r
be of use to a disassembler for the most part. Also provides function\r
prototypes for VM functions.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define OPERAND1_CHAR(op) ('0' + OPERAND1_REGNUM (op))\r
#define OPERAND2_CHAR(op) ('0' + OPERAND2_REGNUM (op))\r
\r
-#define OPERAND1_REGDATA(pvm, op) pvm->R[OPERAND1_REGNUM (op)]\r
-#define OPERAND2_REGDATA(pvm, op) pvm->R[OPERAND2_REGNUM (op)]\r
+#define OPERAND1_REGDATA(pvm, op) pvm->Gpr[OPERAND1_REGNUM (op)]\r
+#define OPERAND2_REGDATA(pvm, op) pvm->Gpr[OPERAND2_REGNUM (op)]\r
\r
//\r
// Condition masks usually for byte 1 encodings of code\r
Provides auxiliary support routines for the VM. That is, routines\r
that are not particularly related to VM execution of EBC instructions.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// image handles, with each having a linked list of thunks allocated\r
// to that image handle.\r
//\r
-typedef struct _EBC_THUNK_LIST {\r
- VOID *ThunkBuffer;\r
- struct _EBC_THUNK_LIST *Next;\r
-} EBC_THUNK_LIST;\r
-\r
-typedef struct _EBC_IMAGE_LIST {\r
- struct _EBC_IMAGE_LIST *Next;\r
- EFI_HANDLE ImageHandle;\r
- EBC_THUNK_LIST *ThunkList;\r
-} EBC_IMAGE_LIST;\r
+typedef struct _EBC_THUNK_LIST EBC_THUNK_LIST;\r
+struct _EBC_THUNK_LIST {\r
+ VOID *ThunkBuffer;\r
+ EBC_THUNK_LIST *Next;\r
+};\r
+\r
+typedef struct _EBC_IMAGE_LIST EBC_IMAGE_LIST;\r
+struct _EBC_IMAGE_LIST {\r
+ EBC_IMAGE_LIST *Next;\r
+ EFI_HANDLE ImageHandle;\r
+ EBC_THUNK_LIST *ThunkList;\r
+};\r
\r
/**\r
This routine is called by the core when an image is being unloaded from\r
//\r
// Initialize the context structure\r
//\r
- EbcContext.R0 = VmPtr->R[0];\r
- EbcContext.R1 = VmPtr->R[1];\r
- EbcContext.R2 = VmPtr->R[2];\r
- EbcContext.R3 = VmPtr->R[3];\r
- EbcContext.R4 = VmPtr->R[4];\r
- EbcContext.R5 = VmPtr->R[5];\r
- EbcContext.R6 = VmPtr->R[6];\r
- EbcContext.R7 = VmPtr->R[7];\r
+ EbcContext.R0 = VmPtr->Gpr[0];\r
+ EbcContext.R1 = VmPtr->Gpr[1];\r
+ EbcContext.R2 = VmPtr->Gpr[2];\r
+ EbcContext.R3 = VmPtr->Gpr[3];\r
+ EbcContext.R4 = VmPtr->Gpr[4];\r
+ EbcContext.R5 = VmPtr->Gpr[5];\r
+ EbcContext.R6 = VmPtr->Gpr[6];\r
+ EbcContext.R7 = VmPtr->Gpr[7];\r
EbcContext.Ip = (UINT64)(UINTN)VmPtr->Ip;\r
EbcContext.Flags = VmPtr->Flags;\r
EbcContext.ControlFlags = 0;\r
//\r
// Restore the context structure and continue to execute\r
//\r
- VmPtr->R[0] = EbcContext.R0;\r
- VmPtr->R[1] = EbcContext.R1;\r
- VmPtr->R[2] = EbcContext.R2;\r
- VmPtr->R[3] = EbcContext.R3;\r
- VmPtr->R[4] = EbcContext.R4;\r
- VmPtr->R[5] = EbcContext.R5;\r
- VmPtr->R[6] = EbcContext.R6;\r
- VmPtr->R[7] = EbcContext.R7;\r
+ VmPtr->Gpr[0] = EbcContext.R0;\r
+ VmPtr->Gpr[1] = EbcContext.R1;\r
+ VmPtr->Gpr[2] = EbcContext.R2;\r
+ VmPtr->Gpr[3] = EbcContext.R3;\r
+ VmPtr->Gpr[4] = EbcContext.R4;\r
+ VmPtr->Gpr[5] = EbcContext.R5;\r
+ VmPtr->Gpr[6] = EbcContext.R6;\r
+ VmPtr->Gpr[7] = EbcContext.R7;\r
VmPtr->Ip = (VMIP)(UINTN)EbcContext.Ip;\r
VmPtr->Flags = EbcContext.Flags;\r
}\r
//\r
// Initialize the context structure\r
//\r
- EbcContext.R0 = VmPtr->R[0];\r
- EbcContext.R1 = VmPtr->R[1];\r
- EbcContext.R2 = VmPtr->R[2];\r
- EbcContext.R3 = VmPtr->R[3];\r
- EbcContext.R4 = VmPtr->R[4];\r
- EbcContext.R5 = VmPtr->R[5];\r
- EbcContext.R6 = VmPtr->R[6];\r
- EbcContext.R7 = VmPtr->R[7];\r
+ EbcContext.R0 = VmPtr->Gpr[0];\r
+ EbcContext.R1 = VmPtr->Gpr[1];\r
+ EbcContext.R2 = VmPtr->Gpr[2];\r
+ EbcContext.R3 = VmPtr->Gpr[3];\r
+ EbcContext.R4 = VmPtr->Gpr[4];\r
+ EbcContext.R5 = VmPtr->Gpr[5];\r
+ EbcContext.R6 = VmPtr->Gpr[6];\r
+ EbcContext.R7 = VmPtr->Gpr[7];\r
EbcContext.Ip = (UINT64)(UINTN)VmPtr->Ip;\r
EbcContext.Flags = VmPtr->Flags;\r
EbcContext.ControlFlags = 0;\r
//\r
// Restore the context structure and continue to execute\r
//\r
- VmPtr->R[0] = EbcContext.R0;\r
- VmPtr->R[1] = EbcContext.R1;\r
- VmPtr->R[2] = EbcContext.R2;\r
- VmPtr->R[3] = EbcContext.R3;\r
- VmPtr->R[4] = EbcContext.R4;\r
- VmPtr->R[5] = EbcContext.R5;\r
- VmPtr->R[6] = EbcContext.R6;\r
- VmPtr->R[7] = EbcContext.R7;\r
+ VmPtr->Gpr[0] = EbcContext.R0;\r
+ VmPtr->Gpr[1] = EbcContext.R1;\r
+ VmPtr->Gpr[2] = EbcContext.R2;\r
+ VmPtr->Gpr[3] = EbcContext.R3;\r
+ VmPtr->Gpr[4] = EbcContext.R4;\r
+ VmPtr->Gpr[5] = EbcContext.R5;\r
+ VmPtr->Gpr[6] = EbcContext.R6;\r
+ VmPtr->Gpr[7] = EbcContext.R7;\r
VmPtr->Ip = (VMIP)(UINTN)EbcContext.Ip;\r
VmPtr->Flags = EbcContext.Flags;\r
}\r
Main routines for the EBC interpreter. Includes the initialization and\r
main interpreter routines.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
typedef UINT32 EXCEPTION_FLAGS;\r
\r
typedef struct {\r
- VM_REGISTER R[8]; // General purpose registers.\r
+ VM_REGISTER Gpr[8]; // General purpose registers.\r
UINT64 Flags; // Flags register:\r
// 0 Set to 1 if the result of the last compare was true\r
// 1 Set to 1 if stepping\r
This module contains EBC support routines that are customized based on\r
the target processor.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// put our return address and frame pointer on the VM stack.\r
// Then set the VM's IP to new EBC code.\r
//\r
- VmPtr->R[0] -= 8;\r
- VmWriteMemN (VmPtr, (UINTN) VmPtr->R[0], (UINTN) FramePtr);\r
- VmPtr->FramePtr = (VOID *) (UINTN) VmPtr->R[0];\r
- VmPtr->R[0] -= 8;\r
- VmWriteMem64 (VmPtr, (UINTN) VmPtr->R[0], (UINT64) (UINTN) (VmPtr->Ip + Size));\r
+ VmPtr->Gpr[0] -= 8;\r
+ VmWriteMemN (VmPtr, (UINTN) VmPtr->Gpr[0], (UINTN) FramePtr);\r
+ VmPtr->FramePtr = (VOID *) (UINTN) VmPtr->Gpr[0];\r
+ VmPtr->Gpr[0] -= 8;\r
+ VmWriteMem64 (VmPtr, (UINTN) VmPtr->Gpr[0], (UINT64) (UINTN) (VmPtr->Ip + Size));\r
\r
VmPtr->Ip = (VMIP) (UINTN) TargetEbcAddr;\r
} else {\r
//\r
// Get return value and advance the IP.\r
//\r
- VmPtr->R[7] = EbcLLGetReturnValue ();\r
+ VmPtr->Gpr[7] = EbcLLGetReturnValue ();\r
VmPtr->Ip += Size;\r
}\r
}\r
return Status;\r
}\r
VmContext.StackTop = (UINT8*)VmContext.StackPool + (STACK_REMAIN_SIZE);\r
- VmContext.R[0] = (UINT64)(UINTN) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
- VmContext.HighStackBottom = (UINTN)VmContext.R[0];\r
- VmContext.R[0] &= ~(sizeof (UINTN) - 1);\r
- VmContext.R[0] -= sizeof (UINTN);\r
+ VmContext.Gpr[0] = (UINT64)(UINTN) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
+ VmContext.HighStackBottom = (UINTN)VmContext.Gpr[0];\r
+ VmContext.Gpr[0] &= ~(sizeof (UINTN) - 1);\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
\r
//\r
// Put a magic value in the stack gap, then adjust down again\r
//\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) VM_STACK_KEY_VALUE;\r
- VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.R[0];\r
- VmContext.LowStackTop = (UINTN) VmContext.R[0];\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) VM_STACK_KEY_VALUE;\r
+ VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.Gpr[0];\r
+ VmContext.LowStackTop = (UINTN) VmContext.Gpr[0];\r
\r
//\r
// For IA32, this is where we say our return address is\r
//\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg16;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg15;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg14;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg13;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg12;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg11;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg10;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg9;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg8;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg7;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg6;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg5;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg4;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg3;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg2;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) Arg1;\r
- VmContext.R[0] -= 16;\r
- VmContext.StackRetAddr = (UINT64) VmContext.R[0];\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg16;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg15;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg14;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg13;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg12;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg11;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg10;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg9;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg8;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg7;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg6;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg5;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg4;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg3;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg2;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg1;\r
+ VmContext.Gpr[0] -= 16;\r
+ VmContext.StackRetAddr = (UINT64) VmContext.Gpr[0];\r
\r
//\r
// We need to keep track of where the EBC stack starts. This way, if the EBC\r
// Return the value in R[7] unless there was an error\r
//\r
ReturnEBCStack(StackIndex);\r
- return (UINT64) VmContext.R[7];\r
+ return (UINT64) VmContext.Gpr[7];\r
}\r
\r
\r
return Status;\r
}\r
VmContext.StackTop = (UINT8*)VmContext.StackPool + (STACK_REMAIN_SIZE);\r
- VmContext.R[0] = (UINT64)(UINTN) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
- VmContext.HighStackBottom = (UINTN)VmContext.R[0];\r
- VmContext.R[0] -= sizeof (UINTN);\r
+ VmContext.Gpr[0] = (UINT64)(UINTN) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
+ VmContext.HighStackBottom = (UINTN)VmContext.Gpr[0];\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
\r
//\r
// Put a magic value in the stack gap, then adjust down again\r
//\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) VM_STACK_KEY_VALUE;\r
- VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.R[0];\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) VM_STACK_KEY_VALUE;\r
+ VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.Gpr[0];\r
\r
//\r
// Align the stack on a natural boundary\r
- // VmContext.R[0] &= ~(sizeof(UINTN) - 1);\r
+ // VmContext.Gpr[0] &= ~(sizeof(UINTN) - 1);\r
//\r
- VmContext.LowStackTop = (UINTN) VmContext.R[0];\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) SystemTable;\r
- VmContext.R[0] -= sizeof (UINTN);\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) ImageHandle;\r
+ VmContext.LowStackTop = (UINTN) VmContext.Gpr[0];\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) SystemTable;\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) ImageHandle;\r
\r
- VmContext.R[0] -= 16;\r
- VmContext.StackRetAddr = (UINT64) VmContext.R[0];\r
+ VmContext.Gpr[0] -= 16;\r
+ VmContext.StackRetAddr = (UINT64) VmContext.Gpr[0];\r
//\r
// VM pushes 16-bytes for return address. Simulate that here.\r
//\r
//\r
// Return the value in R[7] unless there was an error\r
//\r
- return (UINT64) VmContext.R[7];\r
+ return (UINT64) VmContext.Gpr[7];\r
}\r
\r
\r
This module contains EBC support routines that are customized based on\r
the target processor.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Advance the VM stack down, and then copy the argument to the stack.\r
// Hope it's aligned.\r
//\r
- VmPtr->R[0] -= sizeof (UINT64);\r
- *(UINT64 *) VmPtr->R[0] = Arg;\r
+ VmPtr->Gpr[0] -= sizeof (UINT64);\r
+ *(UINT64 *) VmPtr->Gpr[0] = Arg;\r
}\r
\r
/**\r
return Status;\r
}\r
VmContext.StackTop = (UINT8*)VmContext.StackPool + (STACK_REMAIN_SIZE);\r
- VmContext.R[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
- VmContext.HighStackBottom = (UINTN) VmContext.R[0];\r
- VmContext.R[0] -= sizeof (UINTN);\r
+ VmContext.Gpr[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
+ VmContext.HighStackBottom = (UINTN) VmContext.Gpr[0];\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
\r
\r
PushU64 (&VmContext, (UINT64) VM_STACK_KEY_VALUE);\r
- VmContext.StackMagicPtr = (UINTN *) VmContext.R[0];\r
- VmContext.LowStackTop = (UINTN) VmContext.R[0];\r
+ VmContext.StackMagicPtr = (UINTN *) VmContext.Gpr[0];\r
+ VmContext.LowStackTop = (UINTN) VmContext.Gpr[0];\r
//\r
// Push the EBC arguments on the stack. Does not matter that they may not\r
// all be valid.\r
//\r
PushU64 (&VmContext, 0);\r
PushU64 (&VmContext, 0xDEADBEEFDEADBEEF);\r
- VmContext.StackRetAddr = (UINT64) VmContext.R[0];\r
+ VmContext.StackRetAddr = (UINT64) VmContext.Gpr[0];\r
//\r
// Begin executing the EBC code\r
//\r
// Return the value in R[7] unless there was an error\r
//\r
ReturnEBCStack(StackIndex);\r
- return (UINT64) VmContext.R[7];\r
+ return (UINT64) VmContext.Gpr[7];\r
}\r
\r
\r
return Status;\r
}\r
VmContext.StackTop = (UINT8*)VmContext.StackPool + (STACK_REMAIN_SIZE);\r
- VmContext.R[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
- VmContext.HighStackBottom = (UINTN) VmContext.R[0];\r
- VmContext.R[0] -= sizeof (UINTN);\r
+ VmContext.Gpr[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
+ VmContext.HighStackBottom = (UINTN) VmContext.Gpr[0];\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
\r
\r
//\r
// at the bottom so we can detect stack corruption.\r
//\r
PushU64 (&VmContext, (UINT64) VM_STACK_KEY_VALUE);\r
- VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.R[0];\r
+ VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.Gpr[0];\r
\r
//\r
// When we thunk to external native code, we copy the last 8 qwords from\r
// Therefore, leave another gap below the magic value. Pick 10 qwords down,\r
// just as a starting point.\r
//\r
- VmContext.R[0] -= 10 * sizeof (UINT64);\r
+ VmContext.Gpr[0] -= 10 * sizeof (UINT64);\r
\r
//\r
// Align the stack pointer such that after pushing the system table,\r
// image handle, and return address on the stack, it's aligned on a 16-byte\r
// boundary as required for IPF.\r
//\r
- VmContext.R[0] &= (INT64)~0x0f;\r
- VmContext.LowStackTop = (UINTN) VmContext.R[0];\r
+ VmContext.Gpr[0] &= (INT64)~0x0f;\r
+ VmContext.LowStackTop = (UINTN) VmContext.Gpr[0];\r
//\r
// Simply copy the image handle and system table onto the EBC stack.\r
// Greatly simplifies things by not having to spill the args\r
//\r
PushU64 (&VmContext, (UINT64) 0);\r
PushU64 (&VmContext, (UINT64) 0x1234567887654321);\r
- VmContext.StackRetAddr = (UINT64) VmContext.R[0];\r
+ VmContext.StackRetAddr = (UINT64) VmContext.Gpr[0];\r
\r
//\r
// Begin executing the EBC code\r
// Return the value in R[7] unless there was an error\r
//\r
ReturnEBCStack(StackIndex);\r
- return (UINT64) VmContext.R[7];\r
+ return (UINT64) VmContext.Gpr[7];\r
}\r
\r
\r
// put our return address and frame pointer on the VM stack.\r
// Then set the VM's IP to new EBC code.\r
//\r
- VmPtr->R[0] -= 8;\r
- VmWriteMemN (VmPtr, (UINTN) VmPtr->R[0], (UINTN) FramePtr);\r
- VmPtr->FramePtr = (VOID *) (UINTN) VmPtr->R[0];\r
- VmPtr->R[0] -= 8;\r
- VmWriteMem64 (VmPtr, (UINTN) VmPtr->R[0], (UINT64) (VmPtr->Ip + Size));\r
+ VmPtr->Gpr[0] -= 8;\r
+ VmWriteMemN (VmPtr, (UINTN) VmPtr->Gpr[0], (UINTN) FramePtr);\r
+ VmPtr->FramePtr = (VOID *) (UINTN) VmPtr->Gpr[0];\r
+ VmPtr->Gpr[0] -= 8;\r
+ VmWriteMem64 (VmPtr, (UINTN) VmPtr->Gpr[0], (UINT64) (VmPtr->Ip + Size));\r
\r
VmPtr->Ip = (VMIP) (UINTN) TargetEbcAddr;\r
} else {\r
//\r
// Get return value and advance the IP.\r
//\r
- VmPtr->R[7] = EbcLLGetReturnValue ();\r
+ VmPtr->Gpr[7] = EbcLLGetReturnValue ();\r
VmPtr->Ip += Size;\r
}\r
}\r
This module contains EBC support routines that are customized based on\r
the target x64 processor.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Advance the VM stack down, and then copy the argument to the stack.\r
// Hope it's aligned.\r
//\r
- VmPtr->R[0] -= sizeof (UINT64);\r
- *(UINT64 *) VmPtr->R[0] = Arg;\r
+ VmPtr->Gpr[0] -= sizeof (UINT64);\r
+ *(UINT64 *) VmPtr->Gpr[0] = Arg;\r
return;\r
}\r
\r
return Status;\r
}\r
VmContext.StackTop = (UINT8*)VmContext.StackPool + (STACK_REMAIN_SIZE);\r
- VmContext.R[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
- VmContext.HighStackBottom = (UINTN) VmContext.R[0];\r
- VmContext.R[0] -= sizeof (UINTN);\r
+ VmContext.Gpr[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
+ VmContext.HighStackBottom = (UINTN) VmContext.Gpr[0];\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
\r
//\r
// Align the stack on a natural boundary.\r
//\r
- VmContext.R[0] &= ~(sizeof (UINTN) - 1);\r
+ VmContext.Gpr[0] &= ~(sizeof (UINTN) - 1);\r
\r
//\r
// Put a magic value in the stack gap, then adjust down again.\r
//\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) VM_STACK_KEY_VALUE;\r
- VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.R[0];\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) VM_STACK_KEY_VALUE;\r
+ VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.Gpr[0];\r
\r
//\r
// The stack upper to LowStackTop is belong to the VM.\r
//\r
- VmContext.LowStackTop = (UINTN) VmContext.R[0];\r
+ VmContext.LowStackTop = (UINTN) VmContext.Gpr[0];\r
\r
//\r
// For the worst case, assume there are 4 arguments passed in registers, store\r
//\r
// For x64, this is where we say our return address is\r
//\r
- VmContext.StackRetAddr = (UINT64) VmContext.R[0];\r
+ VmContext.StackRetAddr = (UINT64) VmContext.Gpr[0];\r
\r
//\r
// We need to keep track of where the EBC stack starts. This way, if the EBC\r
// Return the value in R[7] unless there was an error\r
//\r
ReturnEBCStack(StackIndex);\r
- return (UINT64) VmContext.R[7];\r
+ return (UINT64) VmContext.Gpr[7];\r
}\r
\r
\r
return Status;\r
}\r
VmContext.StackTop = (UINT8*)VmContext.StackPool + (STACK_REMAIN_SIZE);\r
- VmContext.R[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
- VmContext.HighStackBottom = (UINTN) VmContext.R[0];\r
- VmContext.R[0] -= sizeof (UINTN);\r
+ VmContext.Gpr[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);\r
+ VmContext.HighStackBottom = (UINTN) VmContext.Gpr[0];\r
+ VmContext.Gpr[0] -= sizeof (UINTN);\r
\r
\r
//\r
// Put a magic value in the stack gap, then adjust down again\r
//\r
- *(UINTN *) (UINTN) (VmContext.R[0]) = (UINTN) VM_STACK_KEY_VALUE;\r
- VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.R[0];\r
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) VM_STACK_KEY_VALUE;\r
+ VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.Gpr[0];\r
\r
//\r
// Align the stack on a natural boundary\r
- VmContext.R[0] &= ~(sizeof(UINTN) - 1);\r
+ VmContext.Gpr[0] &= ~(sizeof(UINTN) - 1);\r
//\r
- VmContext.LowStackTop = (UINTN) VmContext.R[0];\r
+ VmContext.LowStackTop = (UINTN) VmContext.Gpr[0];\r
\r
//\r
// Simply copy the image handle and system table onto the EBC stack.\r
//\r
// For x64, this is where we say our return address is\r
//\r
- VmContext.StackRetAddr = (UINT64) VmContext.R[0];\r
+ VmContext.StackRetAddr = (UINT64) VmContext.Gpr[0];\r
\r
//\r
// Entry function needn't access high stack context, simply\r
// Return the value in R[7] unless there was an error\r
//\r
ReturnEBCStack(StackIndex);\r
- return (UINT64) VmContext.R[7];\r
+ return (UINT64) VmContext.Gpr[7];\r
}\r
\r
\r
// put our return address and frame pointer on the VM stack.\r
// Then set the VM's IP to new EBC code.\r
//\r
- VmPtr->R[0] -= 8;\r
- VmWriteMemN (VmPtr, (UINTN) VmPtr->R[0], (UINTN) FramePtr);\r
- VmPtr->FramePtr = (VOID *) (UINTN) VmPtr->R[0];\r
- VmPtr->R[0] -= 8;\r
- VmWriteMem64 (VmPtr, (UINTN) VmPtr->R[0], (UINT64) (VmPtr->Ip + Size));\r
+ VmPtr->Gpr[0] -= 8;\r
+ VmWriteMemN (VmPtr, (UINTN) VmPtr->Gpr[0], (UINTN) FramePtr);\r
+ VmPtr->FramePtr = (VOID *) (UINTN) VmPtr->Gpr[0];\r
+ VmPtr->Gpr[0] -= 8;\r
+ VmWriteMem64 (VmPtr, (UINTN) VmPtr->Gpr[0], (UINT64) (VmPtr->Ip + Size));\r
\r
VmPtr->Ip = (VMIP) (UINTN) TargetEbcAddr;\r
} else {\r
//\r
// Get return value and advance the IP.\r
//\r
- VmPtr->R[7] = EbcLLGetReturnValue ();\r
+ VmPtr->Gpr[7] = EbcLLGetReturnValue ();\r
VmPtr->Ip += Size;\r
}\r
}\r
#define QUESTION_OPTION_FROM_LINK(a) CR (a, QUESTION_OPTION, Link, QUESTION_OPTION_SIGNATURE)\r
\r
#define FORM_BROWSER_STATEMENT_SIGNATURE SIGNATURE_32 ('F', 'S', 'T', 'A')\r
+\r
+typedef union {\r
+ EFI_STRING_ID VarName;\r
+ UINT16 VarOffset;\r
+} VAR_STORE_INFO;\r
+\r
typedef struct {\r
UINTN Signature;\r
LIST_ENTRY Link;\r
EFI_QUESTION_ID QuestionId; // The value of zero is reserved\r
EFI_VARSTORE_ID VarStoreId; // A value of zero indicates no variable storage\r
FORMSET_STORAGE *Storage;\r
- union {\r
- EFI_STRING_ID VarName;\r
- UINT16 VarOffset;\r
- } VarStoreInfo;\r
+ VAR_STORE_INFO VarStoreInfo;\r
UINT16 StorageWidth;\r
UINT8 QuestionFlags;\r
CHAR16 *VariableName; // Name/Value or EFI Variable name\r
/** @file\r
Private structure, MACRO and function definitions for User Interface related functionalities.\r
\r
-Copyright (c) 2004 - 2009, Intel Corporation\r
+Copyright (c) 2004 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#define UI_MENU_LIST_FROM_LINK(a) CR (a, UI_MENU_LIST, Link, UI_MENU_LIST_SIGNATURE)\r
\r
-typedef struct _MENU_REFRESH_ENTRY {\r
- struct _MENU_REFRESH_ENTRY *Next;\r
+typedef struct _MENU_REFRESH_ENTRY MENU_REFRESH_ENTRY;\r
+struct _MENU_REFRESH_ENTRY {\r
+ MENU_REFRESH_ENTRY *Next;\r
UI_MENU_OPTION *MenuOption; // Describes the entry needing an update\r
UI_MENU_SELECTION *Selection;\r
UINTN CurrentColumn;\r
UINTN CurrentRow;\r
UINTN CurrentAttribute;\r
-} MENU_REFRESH_ENTRY;\r
+};\r
\r
typedef struct {\r
UINT16 ScanCode;\r
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