Add ArmPlatformPkg from ARM Ltd. patch.
authorandrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524>
Tue, 1 Feb 2011 05:41:42 +0000 (05:41 +0000)
committerandrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524>
Tue, 1 Feb 2011 05:41:42 +0000 (05:41 +0000)
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11291 6f19259b-4bc3-4df7-8a09-765794883524

103 files changed:
ArmPlatformPkg/ArmPlatformPkg.dec [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/EBLoadSecSyms.inc [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/EfiFuncs.inc [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_boot_from_ram.inc [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_convert_symbols.sh [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_hw_setup.inc [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_load_symbols.inc [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_symbols_macros.inc [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_unload_symbols.inc [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.c [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.c [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEb.c [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.S [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.asm [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.c [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.inf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.c [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.inf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Pei/Arm/ModuleEntryPoint.S [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Pei/Arm/ModuleEntryPoint.asm [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Pei/Cache.c [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Pei/LzmaDecompress.h [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Pei/ModuleEntryPoint.S [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Pei/ModuleEntryPoint.asm [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Pei/Sec.c [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/Pei/Sec.inf [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/b.bat [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/ba.bat [new file with mode: 0644]
ArmPlatformPkg/ArmRealViewEbPkg/build.sh [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.c [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashBlockIoDxe.c [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashDxe.c [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashDxe.h [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashDxe.inf [new file with mode: 0644]
ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashFvbDxe.c [new file with mode: 0644]
ArmPlatformPkg/Bds/Bds.inf [new file with mode: 0644]
ArmPlatformPkg/Bds/BdsEntry.c [new file with mode: 0644]
ArmPlatformPkg/Documentation/ArmPlatformPkg.txt [new file with mode: 0644]
ArmPlatformPkg/Documentation/ArmRealViewRTSMInstructions.txt [new file with mode: 0644]
ArmPlatformPkg/Documentation/ArmVExpressInstructions.txt [new file with mode: 0644]
ArmPlatformPkg/Drivers/SP804TimerDxe/SP804Timer.c [new file with mode: 0644]
ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf [new file with mode: 0644]
ArmPlatformPkg/Include/Drivers/PL011Uart.h [new file with mode: 0644]
ArmPlatformPkg/Include/Drivers/SP804Timer.h [new file with mode: 0644]
ArmPlatformPkg/Include/Library/ArmPlatformLib.h [new file with mode: 0644]
ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.c [new file with mode: 0644]
ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf [new file with mode: 0644]
ArmPlatformPkg/Library/EblCmdLib/EblCmdMmu.c [new file with mode: 0644]
ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c [new file with mode: 0644]
ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf [new file with mode: 0644]
ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c [new file with mode: 0644]
ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf [new file with mode: 0644]
ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c [new file with mode: 0644]
ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf [new file with mode: 0644]
ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c [new file with mode: 0644]
ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf [new file with mode: 0644]
ArmPlatformPkg/MemoryInitPei/MemoryInit.c [new file with mode: 0644]
ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf [new file with mode: 0644]
ArmPlatformPkg/PlatformPei/PlatformPei.c [new file with mode: 0644]
ArmPlatformPkg/PlatformPei/PlatformPei.inf [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/Exception.S [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/Exception.asm [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/MainMPCore.c [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/MainUniCore.c [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/PrePeiCore.c [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/SwitchStack.S [new file with mode: 0644]
ArmPlatformPkg/PrePeiCore/SwitchStack.asm [new file with mode: 0644]
ArmPlatformPkg/Sec/Exception.S [new file with mode: 0644]
ArmPlatformPkg/Sec/Exception.asm [new file with mode: 0644]
ArmPlatformPkg/Sec/Helper.S [new file with mode: 0644]
ArmPlatformPkg/Sec/Helper.asm [new file with mode: 0644]
ArmPlatformPkg/Sec/Sec.c [new file with mode: 0644]
ArmPlatformPkg/Sec/Sec.inf [new file with mode: 0644]
ArmPlatformPkg/Sec/SecEntryPoint.S [new file with mode: 0644]
ArmPlatformPkg/Sec/SecEntryPoint.asm [new file with mode: 0644]

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
new file mode 100644 (file)
index 0000000..b9e7a7a
--- /dev/null
@@ -0,0 +1,57 @@
+#/** @file
+# Arm Versatile Express package.
+#
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = ArmPlatformPkg
+  PACKAGE_GUID                   = 3308e0a0-1d94-11e0-915c-0002a5d5c51b 
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
+
+[Guids.common]
+  gArmPlatformTokenSpaceGuid    =  { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
+
+[PcdsFeatureFlag.common]
+  gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE|BOOLEAN|0x00000001
+
+[PcdsFixedAtBuild.common]
+  # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
+  # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
+  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000002
+  
+  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0|UINT32|0x00000003
+  
+  # Stack for CPU Cores in Secure Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000004
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000005
+
+  # Stack for CPU Cores in Secure Monitor Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000006
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0|UINT32|0x00000007
+
+  # Stack for CPU Cores in Non Secure Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0|UINT32|0x00000008
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0|UINT32|0x00000009
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
new file mode 100644 (file)
index 0000000..4243c8e
--- /dev/null
@@ -0,0 +1,447 @@
+#\r
+#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+#  \r
+#  This program and the accompanying materials                          \r
+#  are licensed and made available under the terms and conditions of the BSD License         \r
+#  which accompanies this distribution.  The full text of the license may be found at        \r
+#  http://opensource.org/licenses/bsd-license.php                                            \r
+#\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+#\r
+#\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+  PLATFORM_NAME                  = ArmRealViewEbPkg\r
+  PLATFORM_GUID                  = F4C1AD3E-9D3E-4F61-8791-B3BB1C43D04C\r
+  PLATFORM_VERSION               = 0.1\r
+  DSC_SPECIFICATION              = 0x00010005\r
+  OUTPUT_DIRECTORY               = Build/ArmRealViewEb-RTSM-A8\r
+  SUPPORTED_ARCHITECTURES        = ARM\r
+  BUILD_TARGETS                  = DEBUG|RELEASE\r
+  SKUID_IDENTIFIER               = DEFAULT\r
+  FLASH_DEFINITION               = ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf\r
+\r
+[LibraryClasses.common]\r
+!if $(BUILD_TARGETS) == RELEASE\r
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf\r
+!else\r
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf\r
+#  UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf\r
+!endif\r
+\r
+  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+  ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf\r
+  \r
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+  BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf\r
+\r
+  EfiResetSystemLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.inf\r
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+  \r
+  EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf\r
+  EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf\r
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+  \r
+  #\r
+  # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window \r
+  # in the debugger will show load and unload commands for symbols. You can cut and paste this\r
+  # into the command window to load symbols. We should be able to use a script to do this, but\r
+  # the version of RVD I have does not support scripts accessing system memory.\r
+  #\r
+#  PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf\r
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf\r
+#  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+  \r
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf\r
+  DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf\r
+  \r
+  SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf\r
+  \r
+  RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf\r
+\r
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+  \r
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+  \r
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+\r
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf\r
+\r
+#\r
+# Assume everything is fixed at build\r
+#\r
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+\r
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+\r
+  EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf\r
+\r
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+\r
+  EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf\r
+  \r
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+  DebugAgentTimerLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf\r
+\r
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf\r
+  TimerLib|ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf  \r
+  GdbSerialLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.inf\r
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
+  \r
+  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf\r
+\r
+[LibraryClasses.common.SEC]\r
+  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+  ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf\r
+  \r
+  # 1/123 faster than Stm or Vstm version\r
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+\r
+  # Uncomment to turn on GDB stub in SEC. \r
+  #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf\r
+  \r
+  # L2 Cache Driver\r
+  L2X0CacheLib|ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf\r
+  # ARM PL390 General Interrupt Driver in Secure and Non-secure\r
+  PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf\r
+\r
+[LibraryClasses.common.PEI_CORE]\r
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+  # note: this won't actually work since globals in PEI are not writeable\r
+  # need to generate an ARM PEI services table pointer implementation\r
+  PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.PEIM]\r
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+  # note: this won't actually work since globals in PEI are not writeable\r
+  # need to generate an ARM PEI services table pointer implementation\r
+  PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+  PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf\r
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.DXE_CORE]\r
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+\r
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf\r
+  \r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+\r
+\r
+[LibraryClasses.common.UEFI_APPLICATION]\r
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+\r
+[LibraryClasses.common.UEFI_DRIVER]\r
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+\r
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+#  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+\r
+[LibraryClasses.ARM]\r
+  #\r
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.\r
+  # This library provides the instrinsic functions generate by a given compiler.\r
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.\r
+  #\r
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r
+\r
+[BuildOptions]\r
+  RVCT:*_*_ARM_ARCHCC_FLAGS  == --cpu Cortex-A8 --thumb --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+  RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+\r
+  GCC:*_*_ARM_ARCHCC_FLAGS    == -march=armv7-a -mthumb -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform \r
+  GCC:*_*_ARM_ARCHASM_FLAGS   == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+  GCC:RELEASE_*_*_CC_FLAGS    = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+\r
+  XCODE:*_*_ARM_ARCHCC_FLAGS     == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+  XCODE:*_*_ARM_ARCHASM_FLAGS    == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+  XCODE:*_*_ARM_ARCHDLINK_FLAGS  == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+  XCODE:RELEASE_*_*_CC_FLAGS     = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag.common]\r
+  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE\r
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE\r
+  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE\r
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE\r
+  \r
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE\r
+  \r
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress\r
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE\r
+  \r
+  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE\r
+\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE\r
+  \r
+  gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE\r
+\r
+!if $(EDK2_SKIP_PEICORE) == 1\r
+  gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE\r
+!endif\r
+\r
+[PcdsFixedAtBuild.common]\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmRealViewEb %a"\r
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32\r
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0\r
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000\r
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000\r
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000\r
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000\r
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF\r
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1\r
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0\r
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320\r
+\r
+# DEBUG_ASSERT_ENABLED       0x01\r
+# DEBUG_PRINT_ENABLED        0x02\r
+# DEBUG_CODE_ENABLED         0x04\r
+# CLEAR_MEMORY_ENABLED       0x08\r
+# ASSERT_BREAKPOINT_ENABLED  0x10\r
+# ASSERT_DEADLOOP_ENABLED    0x20\r
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f\r
+\r
+#  DEBUG_INIT      0x00000001  // Initialization\r
+#  DEBUG_WARN      0x00000002  // Warnings\r
+#  DEBUG_LOAD      0x00000004  // Load events\r
+#  DEBUG_FS        0x00000008  // EFI File system\r
+#  DEBUG_POOL      0x00000010  // Alloc & Free's\r
+#  DEBUG_PAGE      0x00000020  // Alloc & Free's\r
+#  DEBUG_INFO      0x00000040  // Verbose\r
+#  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers\r
+#  DEBUG_VARIABLE  0x00000100  // Variable\r
+#  DEBUG_BM        0x00000400  // Boot Manager\r
+#  DEBUG_BLKIO     0x00001000  // BlkIo Driver\r
+#  DEBUG_NET       0x00004000  // SNI Driver\r
+#  DEBUG_UNDI      0x00010000  // UNDI Driver\r
+#  DEBUG_LOADFILE  0x00020000  // UNDI Driver\r
+#  DEBUG_EVENT     0x00080000  // Event messages\r
+#  DEBUG_ERROR     0x80000000  // Error\r
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F\r
+\r
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
+\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000\r
+  \r
+#\r
+# Optional feature to help prevent EFI memory map fragments\r
+# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob\r
+# Values are in EFI Pages (4K). DXE Core will make sure that \r
+# at least this much of each type of memory can be allocated \r
+# from a single memory range. This way you only end up with\r
+# maximum of two fragements for each type in the memory map\r
+# (the memory used, and the free memory that was prereserved\r
+# but not used).\r
+#\r
+  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000\r
+  \r
+  # Stack for CPU Cores in Secure Mode\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000     # Top of SEC Stack for Secure World\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000          # Size of SEC Stack for Secure World\r
+\r
+  # Stack for CPU Cores in Secure Monitor Mode\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x4A000000  # Top of SEC Stack for Monitor World\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x2000       # Size of SEC Stack for Monitor World\r
+\r
+  # Stack for CPU Cores in Non Secure Mode\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000  # Top of SEC Stack for Normal World\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000     # Size of SEC Stack for Normal World\r
+  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004        # Pei Services Ptr just above stack\r
+\r
+  # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress|0x40050000       # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize|0x00100000              # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
+  \r
+  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000        # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms\r
+  \r
+  #\r
+  # ARM Pcds\r
+  #\r
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000\r
+  \r
+  #\r
+  # ARM EB PCDS\r
+  #\r
+  gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase|0x1000a000\r
+  \r
+  #\r
+  # ARM PL390 General Interrupt Controller\r
+  #\r
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x10041000\r
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x10040000\r
+\r
+  #\r
+  # ARM OS Loader\r
+  #\r
+  # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: \r
+  gArmTokenSpaceGuid.PcdArmMachineType|2272\r
+  gArmTokenSpaceGuid.PcdLinuxKernelDP|L"VenHw(02118005-9DA7-443a-92D5-781F022AEDBB)/MemoryMapped(0,0x46000000,0x46400000)"\r
+  gArmTokenSpaceGuid.PcdLinuxAtag|"rdinit=/bin/ash debug earlyprintk console=ttyAMA0,38400 mem=1G"\r
+  gArmTokenSpaceGuid.PcdFdtDP|L""\r
+  \r
+  #\r
+  # ARM L2x0 PCDs\r
+  #\r
+  gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1F002000\r
\r
+\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform\r
+#\r
+################################################################################\r
+[Components.common]\r
+  \r
+#\r
+# SEC\r
+#\r
+  ArmPlatformPkg/Sec/Sec.inf\r
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf\r
+  \r
+#\r
+# PEI Phase modules\r
+#\r
+  MdeModulePkg/Core/Pei/PeiMain.inf\r
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf  {\r
+    <LibraryClasses>\r
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+  }\r
+  ArmPlatformPkg/PlatformPei/PlatformPei.inf\r
+  ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf\r
+  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+  Nt32Pkg/BootModePei/BootModePei.inf\r
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
+    <LibraryClasses>\r
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+  }\r
+\r
+#\r
+# DXE\r
+#\r
+  MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+    <LibraryClasses>\r
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
+  }\r
+\r
+  #\r
+  # Architectural Protocols\r
+  #\r
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf  \r
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf  \r
+  \r
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+  \r
+  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf\r
+\r
+  ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf\r
+  ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf\r
+  ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
+\r
+  #\r
+  # Semi-hosting filesystem\r
+  #\r
+  ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+  \r
+  #\r
+  # FAT filesystem + GPT/MBR partitioning\r
+  #\r
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+  FatPkg/EnhancedFatDxe/Fat.inf\r
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+  \r
+  \r
+  #\r
+  # Application\r
+  #  \r
+  EmbeddedPkg/Ebl/Ebl.inf\r
+\r
+  #\r
+  # Bds\r
+  #\r
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+  ArmPlatformPkg/Bds/Bds.inf\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
new file mode 100644 (file)
index 0000000..2c70248
--- /dev/null
@@ -0,0 +1,458 @@
+#
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ArmRealViewEb-RTSM-A9x2
+  PLATFORM_GUID                  = f6c2f4a0-2027-11e0-a2a1-0002a5d5c51b
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/ArmRealViewEb-RTSM-A9x2
+  SUPPORTED_ARCHITECTURES        = ARM
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf
+
+[LibraryClasses.common]
+!if $(BUILD_TARGETS) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+#  UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+!endif
+
+  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
+  ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
+  ArmMPCoreMailBoxLib|ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBoxLib.inf
+  
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
+
+  EfiResetSystemLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  
+  EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf
+  EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  
+  #
+  # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window 
+  # in the debugger will show load and unload commands for symbols. You can cut and paste this
+  # into the command window to load symbols. We should be able to use a script to do this, but
+  # the version of RVD I have does not support scripts accessing system memory.
+  #
+#  PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+#  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  
+  SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+  
+  RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+
+#
+# Assume everything is fixed at build
+#
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+  EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
+
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+  EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+  
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DebugAgentTimerLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
+
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+  TimerLib|ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf  
+  GdbSerialLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.inf
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+  
+  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+
+[LibraryClasses.common.SEC]
+  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf
+  
+  # 1/123 faster than Stm or Vstm version
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+  # Uncomment to turn on GDB stub in SEC. 
+  #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+  
+  # L2 Cache Driver
+  L2X0CacheLib|ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
+  # ARM PL390 General Interrupt Driver in Secure and Non-secure
+  PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
+  PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+
+[LibraryClasses.common.PEI_CORE]
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  # note: this won't actually work since globals in PEI are not writeable
+  # need to generate an ARM PEI services table pointer implementation
+  PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.PEIM]
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  # note: this won't actually work since globals in PEI are not writeable
+  # need to generate an ARM PEI services table pointer implementation
+  PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+  
+
+[LibraryClasses.common.DXE_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+#  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+  #
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+  # This library provides the instrinsic functions generate by a given compiler.
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[BuildOptions]
+  RVCT:*_*_ARM_ARCHCC_FLAGS  == --cpu Cortex-A9 --thumb --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+  RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A9 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+
+  GCC:*_*_ARM_ARCHCC_FLAGS    == -march=armv7-a -mthumb -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform 
+  GCC:*_*_ARM_ARCHASM_FLAGS   == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+  GCC:RELEASE_*_*_CC_FLAGS    = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+
+  XCODE:*_*_ARM_ARCHCC_FLAGS     == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+  XCODE:*_*_ARM_ARCHASM_FLAGS    == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+  XCODE:*_*_ARM_ARCHDLINK_FLAGS  == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+  XCODE:RELEASE_*_*_CC_FLAGS     = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+  
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+  
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+  
+  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+  
+  gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+  gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE
+!endif
+
+[PcdsFixedAtBuild.common]
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmRealViewEb %a"
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+# DEBUG_ASSERT_ENABLED       0x01
+# DEBUG_PRINT_ENABLED        0x02
+# DEBUG_CODE_ENABLED         0x04
+# CLEAR_MEMORY_ENABLED       0x08
+# ASSERT_BREAKPOINT_ENABLED  0x10
+# ASSERT_DEADLOOP_ENABLED    0x20
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+
+#  DEBUG_INIT      0x00000001  // Initialization
+#  DEBUG_WARN      0x00000002  // Warnings
+#  DEBUG_LOAD      0x00000004  // Load events
+#  DEBUG_FS        0x00000008  // EFI File system
+#  DEBUG_POOL      0x00000010  // Alloc & Free's
+#  DEBUG_PAGE      0x00000020  // Alloc & Free's
+#  DEBUG_INFO      0x00000040  // Verbose
+#  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
+#  DEBUG_VARIABLE  0x00000100  // Variable
+#  DEBUG_BM        0x00000400  // Boot Manager
+#  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+#  DEBUG_NET       0x00004000  // SNI Driver
+#  DEBUG_UNDI      0x00010000  // UNDI Driver
+#  DEBUG_LOADFILE  0x00020000  // UNDI Driver
+#  DEBUG_EVENT     0x00080000  // Event messages
+#  DEBUG_ERROR     0x80000000  // Error
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+  
+#
+# Optional feature to help prevent EFI memory map fragments
+# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+# Values are in EFI Pages (4K). DXE Core will make sure that 
+# at least this much of each type of memory can be allocated 
+# from a single memory range. This way you only end up with
+# maximum of two fragements for each type in the memory map
+# (the memory used, and the free memory that was prereserved
+# but not used).
+#
+  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000
+  
+  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
+  
+  # Stacks for MPCores in Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000     # Top of SEC Stack for Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000                   # Stack for each of the 4 CPU cores
+
+  # Stacks for MPCores in Monitor Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x4A000000  # Top of SEC Stack for Monitor World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x2000              # Stack for each of the 4 CPU cores
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000     # Top of SEC Stack for Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000        # Stack for each of the 4 CPU cores
+  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004        # Pei Services Ptr just above stack
+
+  # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress|0x40050000       # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize|0x00100000              # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+  
+  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000        # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+  
+  #
+  # ARM Pcds
+  #
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+  
+  #
+  # ARM EB PCDS
+  #
+  gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase|0x1000a000
+  
+  #
+  # ARM PL390 General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x10041000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x10040000
+
+  #
+  # ARM OS Loader
+  #
+  # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: 
+  gArmTokenSpaceGuid.PcdArmMachineType|2272
+  gArmTokenSpaceGuid.PcdLinuxKernelDP|L"VenHw(02118005-9DA7-443a-92D5-781F022AEDBB)/MemoryMapped(0,0x46000000,0x46400000)"
+  gArmTokenSpaceGuid.PcdLinuxAtag|"rdinit=/bin/ash debug earlyprintk console=ttyAMA0,38400 mem=1G"
+  gArmTokenSpaceGuid.PcdFdtDP|L""
+  
+  #
+  # ARM L2x0 PCDs
+  #
+  gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1F002000
+  #
+  # ARM VE MP Core Mailbox
+  #
+  gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0x10000030
+  gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0x10000030
+  gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0x10000034
+  gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0xFFFFFFFF
+
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  
+#
+# SEC
+#
+  ArmPlatformPkg/Sec/Sec.inf
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  
+#
+# PEI Phase modules
+#
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf  {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  ArmPlatformPkg/PlatformPei/PlatformPei.inf
+  ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  Nt32Pkg/BootModePei/BootModePei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+
+#
+# DXE
+#
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf  
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf  
+  
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  
+  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf
+  ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf
+  ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+
+  #
+  # Semi-hosting filesystem
+  #
+  ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+  
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  
+  
+  #
+  # Application
+  #  
+  EmbeddedPkg/Ebl/Ebl.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  ArmPlatformPkg/Bds/Bds.inf
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf
new file mode 100644 (file)
index 0000000..6283dca
--- /dev/null
@@ -0,0 +1,313 @@
+# FLASH layout file for ARM VE.
+#
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+
+[FD.ArmRealViewEb_EFI]
+BaseAddress   = 0x40000000  # The base address of the FLASH Device.
+Size          = 0x00200000  # The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize     = 0x00010000
+NumBlocks     = 0x20
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00050000
+gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize
+FV = FVMAIN_SEC
+
+0x00050000|0x00100000
+gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+0x00150000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  #  { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x20000
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  #Signature: gEfiVariableGuid =
+  #  { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  #Size: 0xc000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xBFB8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xBF, 0x00, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf 
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services) 
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+   
+  INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+  
+  INF ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf
+  INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+
+  #
+  # Semi-hosting filesystem
+  #
+  INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+  
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader) 
+  #  
+  INF EmbeddedPkg/Ebl/Ebl.inf
+  
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF ArmPlatformPkg/Bds/Bds.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPei.inf
+  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+  
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   # 
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX Optional      |.depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    |.efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 8      |.efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE           |.efi
+    UI     STRING ="$(MODULE_NAME)" Optional         
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional        |.depex
+     TE       TE                         |.efi
+     UI       STRING="$(MODULE_NAME)" Optional         
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional         |.depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                     |.efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32           |.efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX Optional      |.depex
+    PE32         PE32                    |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX Optional      |.depex
+    PE32         PE32                    |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX Optional      |.depex
+    PE32         PE32                    |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)" Optional         
+    PE32   PE32                    |.efi
+  }
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf
new file mode 100644 (file)
index 0000000..04b3fb7
--- /dev/null
@@ -0,0 +1,313 @@
+# FLASH layout file for ARM RealView EB.\r
+#\r
+# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
+#\r
+#    This program and the accompanying materials\r
+#    are licensed and made available under the terms and conditions of the BSD License\r
+#    which accompanies this distribution. The full text of the license may be found at\r
+#    http://opensource.org/licenses/bsd-license.php\r
+#\r
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into  the Flash Device Image.  Each FD section\r
+# defines one flash "device" image.  A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash"  image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+\r
+\r
+[FD.ArmRealViewEb_EFI]\r
+BaseAddress   = 0x40000000  # The base address of the FLASH Device.\r
+Size          = 0x00200000  # The size in bytes of the FLASH Device\r
+ErasePolarity = 1\r
+BlockSize     = 0x00010000\r
+NumBlocks     = 0x20\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+\r
+0x00000000|0x00050000\r
+gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize\r
+FV = FVMAIN_SEC\r
+\r
+0x00050000|0x00100000\r
+gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
+FV = FVMAIN_COMPACT\r
+\r
+0x00150000|0x00010000\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+#NV_VARIABLE_STORE\r
+DATA = {\r
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER\r
+  # ZeroVector []\r
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =\r
+  #  { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}\r
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,\r
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,\r
+  # FvLength: 0x20000\r
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+  #Signature "_FVH"       #Attributes\r
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,\r
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision\r
+  0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,\r
+  #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block\r
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,\r
+  #Blockmap[1]: End\r
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+  ## This is the VARIABLE_STORE_HEADER\r
+  #Signature: gEfiVariableGuid =\r
+  #  { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}\r
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,\r
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,\r
+  #Size: 0xc000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xBFB8\r
+  # This can speed up the Variable Dispatch a bit.\r
+  0xB8, 0xBF, 0x00, 0x00,\r
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32\r
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
+}\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file.  This section also defines order the components and modules are positioned\r
+# within the image.  The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+\r
+[FV.FVMAIN_SEC]\r
+FvAlignment        = 8\r
+ERASE_POLARITY     = 1\r
+MEMORY_MAPPED      = TRUE\r
+STICKY_WRITE       = TRUE\r
+LOCK_CAP           = TRUE\r
+LOCK_STATUS        = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP  = TRUE\r
+WRITE_STATUS       = TRUE\r
+WRITE_LOCK_CAP     = TRUE\r
+WRITE_LOCK_STATUS  = TRUE\r
+READ_DISABLED_CAP  = TRUE\r
+READ_ENABLED_CAP   = TRUE\r
+READ_STATUS        = TRUE\r
+READ_LOCK_CAP      = TRUE\r
+READ_LOCK_STATUS   = TRUE\r
+\r
+  INF ArmPlatformPkg/Sec/Sec.inf\r
+\r
+\r
+[FV.FvMain]\r
+BlockSize          = 0x40\r
+NumBlocks          = 0         # This FV gets compressed so make it just big enough\r
+FvAlignment        = 8         # FV alignment and FV attributes setting.\r
+ERASE_POLARITY     = 1\r
+MEMORY_MAPPED      = TRUE\r
+STICKY_WRITE       = TRUE\r
+LOCK_CAP           = TRUE\r
+LOCK_STATUS        = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP  = TRUE\r
+WRITE_STATUS       = TRUE\r
+WRITE_LOCK_CAP     = TRUE\r
+WRITE_LOCK_STATUS  = TRUE\r
+READ_DISABLED_CAP  = TRUE\r
+READ_ENABLED_CAP   = TRUE\r
+READ_STATUS        = TRUE\r
+READ_LOCK_CAP      = TRUE\r
+READ_LOCK_STATUS   = TRUE\r
+\r
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf \r
+\r
+  #\r
+  # PI DXE Drivers producing Architectural Protocols (EFI Services) \r
+  #\r
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf\r
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+   \r
+  INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf\r
+  \r
+  INF ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf\r
+  INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
+\r
+  #\r
+  # Semi-hosting filesystem\r
+  #\r
+  INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+  \r
+  #\r
+  # FAT filesystem + GPT/MBR partitioning\r
+  #\r
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+  INF FatPkg/EnhancedFatDxe/Fat.inf\r
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+  #\r
+  # UEFI application (Shell Embedded Boot Loader) \r
+  #  \r
+  INF EmbeddedPkg/Ebl/Ebl.inf\r
+  \r
+\r
+  #\r
+  # Bds\r
+  #\r
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+  INF ArmPlatformPkg/Bds/Bds.inf\r
+\r
+\r
+[FV.FVMAIN_COMPACT]\r
+FvAlignment        = 8\r
+ERASE_POLARITY     = 1\r
+MEMORY_MAPPED      = TRUE\r
+STICKY_WRITE       = TRUE\r
+LOCK_CAP           = TRUE\r
+LOCK_STATUS        = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP  = TRUE\r
+WRITE_STATUS       = TRUE\r
+WRITE_LOCK_CAP     = TRUE\r
+WRITE_LOCK_STATUS  = TRUE\r
+READ_DISABLED_CAP  = TRUE\r
+READ_ENABLED_CAP   = TRUE\r
+READ_STATUS        = TRUE\r
+READ_LOCK_CAP      = TRUE\r
+READ_LOCK_STATUS   = TRUE\r
+\r
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf\r
+  INF MdeModulePkg/Core/Pei/PeiMain.inf\r
+  INF ArmPlatformPkg/PlatformPei/PlatformPei.inf\r
+  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf\r
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+  \r
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
+      SECTION FV_IMAGE = FVMAIN\r
+    }\r
+  }\r
+\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+\r
+############################################################################\r
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   # \r
+############################################################################\r
+#\r
+#[Rule.Common.DXE_DRIVER]\r
+#  FILE DRIVER = $(NAMED_GUID) {\r
+#    DXE_DEPEX    DXE_DEPEX Optional      |.depex\r
+#    COMPRESS PI_STD {\r
+#      GUIDED {\r
+#        PE32     PE32                    |.efi\r
+#        UI       STRING="$(MODULE_NAME)" Optional\r
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+#      }\r
+#    }\r
+#  }\r
+#\r
+############################################################################\r
+\r
+[Rule.Common.SEC]\r
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+    TE  TE    Align = 8      |.efi\r
+  }\r
+\r
+[Rule.Common.PEI_CORE]\r
+  FILE PEI_CORE = $(NAMED_GUID) {\r
+    TE     TE           |.efi\r
+    UI     STRING ="$(MODULE_NAME)" Optional         \r
+  }\r
+\r
+[Rule.Common.PEIM]\r
+  FILE PEIM = $(NAMED_GUID) {\r
+     PEI_DEPEX PEI_DEPEX Optional        |.depex\r
+     TE       TE                         |.efi\r
+     UI       STRING="$(MODULE_NAME)" Optional         \r
+  }\r
+\r
+[Rule.Common.PEIM.TIANOCOMPRESSED]\r
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
+    PEI_DEPEX PEI_DEPEX Optional         |.depex\r
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
+      PE32      PE32                     |.efi\r
+      UI        STRING="$(MODULE_NAME)" Optional\r
+    }\r
+  }\r
+\r
+[Rule.Common.DXE_CORE]\r
+  FILE DXE_CORE = $(NAMED_GUID) {\r
+    PE32     PE32           |.efi\r
+    UI       STRING="$(MODULE_NAME)" Optional\r
+  }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+  FILE DRIVER = $(NAMED_GUID) {\r
+    DXE_DEPEX    DXE_DEPEX Optional      |.depex\r
+    PE32         PE32                    |.efi\r
+    UI           STRING="$(MODULE_NAME)" Optional\r
+  }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+  FILE DRIVER = $(NAMED_GUID) {\r
+    DXE_DEPEX    DXE_DEPEX Optional      |.depex\r
+    PE32         PE32                    |.efi\r
+    UI           STRING="$(MODULE_NAME)" Optional\r
+  }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+  FILE DRIVER = $(NAMED_GUID) {\r
+    DXE_DEPEX    DXE_DEPEX Optional      |.depex\r
+    PE32         PE32                    |.efi\r
+    UI           STRING="$(MODULE_NAME)" Optional\r
+  }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+  FILE APPLICATION = $(NAMED_GUID) {\r
+    UI     STRING ="$(MODULE_NAME)" Optional         \r
+    PE32   PE32                    |.efi\r
+  }\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec
new file mode 100644 (file)
index 0000000..aabbc01
--- /dev/null
@@ -0,0 +1,40 @@
+#/** @file
+# Arm RealView EB package.
+#
+# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
+#
+#    This program and the accompanying materials are licensed and made available under
+#    the terms and conditions of the BSD License which accompanies this distribution.
+#    The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = ArmRealViewEbPkg
+  PACKAGE_GUID                   = 44577A0D-361A-45B2-B33D-BB9EE60D5A4F
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
+
+[Guids.common]
+  gArmRealViewEbPkgTokenSpaceGuid    =  { 0x44577A0D, 0x361A, 0x45B2, { 0xb3, 0x3d, 0xbb, 0x9e, 0xe6, 0x0d, 0x5a, 0x4f} } 
+
+[PcdsFeatureFlag.common]
+
+[PcdsFixedAtBuild.common]
+  gArmRealViewEbPkgTokenSpaceGuid.PcdPeiServicePtrAddr|0|UINT32|0x00000003
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/EBLoadSecSyms.inc b/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/EBLoadSecSyms.inc
new file mode 100644 (file)
index 0000000..8783036
--- /dev/null
@@ -0,0 +1,16 @@
+// returns the base address of the SEC FV in flash on the EB board\r
+// change this address for where your platform's SEC FV is located\r
+// (or make it more intelligent to search for it)\r
+define /r FindFv()\r
+{\r
+  return 0x40000000;\r
+}\r
+.\r
+\r
+include /s 'ZZZZZZ/EfiFuncs.inc'\r
+error=continue\r
+unload ,all\r
+error=abort\r
+LoadPeiSec()\r
+include C:\loadfiles.inc\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/EfiFuncs.inc b/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/EfiFuncs.inc
new file mode 100644 (file)
index 0000000..0bbe045
--- /dev/null
@@ -0,0 +1,463 @@
+error=abort\r
+\r
+// NOTE: THIS MAY NEED TO BE ADJUSTED\r
+// change to reflect the total amount of ram in your system\r
+define /r GetMaxMem()\r
+{\r
+  return 0x10000000; // 256 MB\r
+}\r
+.\r
+\r
+define /r GetWord(Addr)\r
+{\r
+  unsigned long data;\r
+  \r
+  if( (Addr & 0x2) == 0 )\r
+  {\r
+    data = dword(Addr);\r
+    data = data & 0xffff;\r
+    //$printf "getword data is %x\n", data$;\r
+    return data;\r
+  }\r
+  else\r
+  {\r
+    data = dword(Addr & 0xfffffffc);\r
+    //data = data >> 16;\r
+    data = data / 0x10000;\r
+    //$printf "getword data is %x (1)\n", data$;\r
+    return data;\r
+  }\r
+}\r
+.\r
+\r
+define /r ProcessPE32(imgstart)\r
+unsigned long imgstart;\r
+{\r
+  unsigned long filehdrstart;\r
+  unsigned long debugdirentryrva;\r
+       unsigned long debugtype;\r
+  unsigned long debugrva;\r
+       unsigned long dwarfsig;\r
+  unsigned long baseofcode;\r
+  unsigned long baseofdata;\r
+  unsigned long elfbase;\r
+  char *elfpath;\r
+\r
+       $printf "PE32 image found at %x",imgstart$;\r
+\r
+       //$printf "PE file hdr offset %x",dword(imgstart+0x3C)$;\r
+\r
+  // offset from dos hdr to PE file hdr\r
+  filehdrstart = imgstart + dword(imgstart+0x3C);\r
+\r
+  // offset to debug dir in PE hdrs\r
+       //$printf "debug dir is at %x",(filehdrstart+0xA8)$;\r
+       debugdirentryrva = dword(filehdrstart + 0xA8);\r
+  if(debugdirentryrva == 0)\r
+       {\r
+               $printf "no debug dir for image at %x",imgstart$;\r
+         return;\r
+       }\r
+\r
+       //$printf "debug dir entry rva is %x",debugdirentryrva$;\r
+\r
+       debugtype = dword(imgstart + debugdirentryrva + 0xc);\r
+  if( (debugtype != 0xdf) && (debugtype != 0x2) )\r
+       {\r
+               $printf "debug type is not dwarf for image at %x",imgstart$;\r
+               $printf "debug type is %x",debugtype$;\r
+               return;\r
+       }\r
+       \r
+       debugrva = dword(imgstart + debugdirentryrva + 0x14);\r
+       dwarfsig = dword(imgstart + debugrva);\r
+       if(dwarfsig != 0x66727764)\r
+       {\r
+               $printf "dwarf debug signature not found for image at %x",imgstart$;\r
+         return;\r
+       }\r
+\r
+  elfpath = (char *)(imgstart + debugrva + 0xc);\r
+\r
+  baseofcode = imgstart + dword(filehdrstart + 0x28);\r
+  baseofdata = imgstart + dword(filehdrstart + 0x2c);\r
\r
+  if( (baseofcode < baseofdata) && (baseofcode != 0) )\r
+  {\r
+               elfbase = baseofcode;\r
+  }\r
+  else\r
+  {\r
+    elfbase = baseofdata;\r
+  }\r
+\r
+       $printf "found path %s",elfpath$;\r
+       $fprintf 50, "load /ni /np /a %s &0x%x\n",elfpath,elfbase$;\r
+}\r
+.\r
+\r
+define /r ProcessTE(imgstart)\r
+unsigned long imgstart;\r
+{\r
+  unsigned long strippedsize;\r
+       unsigned long debugdirentryrva;\r
+       unsigned long debugtype;\r
+  unsigned long debugrva;\r
+       unsigned long dwarfsig;\r
+  unsigned long elfbase;\r
+  char *elfpath;\r
+\r
+       $printf "TE image found at %x",imgstart$;\r
+\r
+  // determine pe header bytes removed to account for in rva references\r
+  //strippedsize = word(imgstart + 0x6);\r
+  //strippedsize = (dword(imgstart + 0x4) & 0xffff0000) >> 16;\r
+  strippedsize = (dword(imgstart + 0x4) & 0xffff0000) / 0x10000;\r
+  strippedsize = strippedsize - 0x28;\r
+\r
+       debugdirentryrva = dword(imgstart + 0x20);\r
+  if(debugdirentryrva == 0)\r
+       {\r
+               $printf "no debug dir for image at %x",imgstart$;\r
+         return;\r
+       }\r
+  debugdirentryrva = debugdirentryrva - strippedsize;\r
+\r
+       //$printf "debug dir entry rva is %x",debugdirentryrva$;\r
+\r
+       debugtype = dword(imgstart + debugdirentryrva + 0xc);\r
+  if( (debugtype != 0xdf) && (debugtype != 0x2) )\r
+       {\r
+               $printf "debug type is not dwarf for image at %x",imgstart$;\r
+               $printf "debug type is %x",debugtype$;\r
+               return;\r
+       }\r
+       \r
+       debugrva = dword(imgstart + debugdirentryrva + 0x14);\r
+  debugrva = debugrva - strippedsize;\r
+       dwarfsig = dword(imgstart + debugrva);\r
+       if( (dwarfsig != 0x66727764) && (dwarfsig != 0x3031424e) )\r
+       {\r
+               $printf "dwarf debug signature not found for image at %x",imgstart$;\r
+               $printf "found %x", dwarfsig$;\r
+         return;\r
+       }\r
+       \r
+       if( dwarfsig == 0x66727764 )\r
+       {\r
+               elfpath = (char *)(imgstart + debugrva + 0xc);\r
+    $printf "looking for elf path at 0x%x", elfpath$; \r
+  }\r
+  else \r
+  {\r
+    elfpath = (char *)(imgstart + debugrva + 0x10);\r
+    $printf "looking for elf path at 0x%x", elfpath$; \r
+  }\r
+\r
+  // elf base is baseofcode (we hope that for TE images it's not baseofdata)\r
+  elfbase = imgstart + dword(imgstart + 0xc) - strippedsize;\r
+\r
+       $printf "found path %s",elfpath$;\r
+       $fprintf 50, "load /ni /np /a %s &0x%x\n",elfpath,elfbase$;\r
+}\r
+.\r
+\r
+define /r ProcessFvSection(secstart)\r
+unsigned long secstart;\r
+{\r
+  unsigned long sectionsize;\r
+  unsigned char sectiontype;\r
+\r
+       sectionsize = dword(secstart);\r
+  //sectiontype = (sectionsize & 0xff000000) >> 24;\r
+  sectiontype = (sectionsize & 0xff000000) / 0x1000000;\r
+  sectionsize = sectionsize & 0x00ffffff;\r
+\r
+       $printf "fv section at %x size %x type %x",secstart,sectionsize,sectiontype$;\r
+\r
+       if(sectiontype == 0x10) // PE32\r
+  {\r
+               ProcessPE32(secstart+0x4);\r
+       }\r
+       else if(sectiontype == 0x12) // TE\r
+       {\r
+               ProcessTE(secstart+0x4);        \r
+       }\r
+}\r
+.\r
+\r
+define /r ProcessFfsFile(ffsfilestart)\r
+unsigned long ffsfilestart;\r
+{\r
+  unsigned long ffsfilesize;\r
+  unsigned long ffsfiletype;\r
+  unsigned long secoffset;\r
+  unsigned long secsize;\r
+\r
+  //ffsfiletype = byte(ffsfilestart + 0x12);\r
+  ffsfilesize = dword(ffsfilestart + 0x14);\r
+  //ffsfiletype = (ffsfilesize & 0xff000000) >> 24;\r
+  ffsfiletype = (ffsfilesize & 0xff000000) / 0x1000000;\r
+  ffsfilesize = ffsfilesize & 0x00ffffff;\r
+\r
+  if(ffsfiletype == 0xff) return;\r
+\r
+       $printf "ffs file at %x size %x type %x",ffsfilestart,ffsfilesize,ffsfiletype$;\r
+\r
+  secoffset = ffsfilestart + 0x18;\r
+\r
+  // loop through sections in file\r
+  while(secoffset < (ffsfilestart + ffsfilesize))\r
+       {\r
+               // process fv section and increment section offset by size\r
+    secsize = dword(secoffset) & 0x00ffffff;\r
+    ProcessFvSection(secoffset);\r
+               secoffset = secoffset + secsize;\r
+\r
+         // align to next 4 byte boundary\r
+    if( (secoffset & 0x3) != 0 )\r
+               {\r
+                       secoffset = secoffset + (0x4 - (secoffset & 0x3));\r
+               }\r
+       } // end section loop\r
+}\r
+.\r
+\r
+define /r LoadPeiSec()\r
+{\r
+  unsigned long fvbase;\r
+  unsigned long fvlen;\r
+  unsigned long fvsig;\r
+       unsigned long ffsoffset;\r
+  unsigned long ffsfilesize;\r
+\r
+  fvbase = FindFv();\r
+       $printf "fvbase %x",fvbase$;\r
+\r
+  // get fv signature field\r
+  fvsig = dword(fvbase + 0x28);\r
+  if(fvsig != 0x4856465F)\r
+  {\r
+               $printf "FV does not have proper signature, exiting"$;\r
+    return 0;\r
+  }\r
+\r
+       $printf "FV signature found"$;\r
+\r
+  $fopen 50, 'C:\loadfiles.inc'$;\r
+\r
+  fvlen = dword(fvbase + 0x20);\r
+  \r
+  // first ffs file is after fv header, use headerlength field\r
+  //ffsoffset = (dword(fvbase + 0x30) & 0xffff0000) >> 16;\r
+  ffsoffset = (dword(fvbase + 0x30) & 0xffff0000) / 0x10000;\r
+  ffsoffset = fvbase + GetWord(fvbase + 0x30);\r
+\r
+  // loop through ffs files\r
+  while(ffsoffset < (fvbase+fvlen))\r
+       {\r
+               // process ffs file and increment by ffs file size field\r
+               ProcessFfsFile(ffsoffset);    \r
+               ffsfilesize = (dword(ffsoffset + 0x14) & 0x00ffffff);\r
+               if(ffsfilesize == 0)\r
+               {\r
+                 break;\r
+               }\r
+               ffsoffset = ffsoffset + ffsfilesize;\r
+               \r
+\r
+               // align to next 8 byte boundary\r
+    if( (ffsoffset & 0x7) != 0 )\r
+               {\r
+                       ffsoffset = ffsoffset + (0x8 - (ffsoffset & 0x7));\r
+               }\r
+         \r
+  } // end fv ffs loop\r
+\r
+       $vclose 50$;\r
+\r
+}\r
+.\r
+\r
+define /r FindSystemTable(TopOfRam)\r
+unsigned long TopOfRam;\r
+{\r
+  unsigned long offset;\r
+  \r
+  $printf "FindSystemTable"$;\r
+  $printf "top of mem is %x",TopOfRam$;\r
+  \r
+  offset = TopOfRam;\r
+  \r
+  // align to highest 4MB boundary\r
+  offset = offset & 0xFFC00000;\r
+  \r
+  // start at top and look on 4MB boundaries for system table ptr structure\r
+  while(offset > 0)\r
+  {\r
+    //$printf "checking %x",offset$;\r
+    //$printf "value is %x",dword(offset)$;\r
+    \r
+    // low signature match\r
+    if(dword(offset) == 0x20494249)\r
+    {\r
+      // high signature match\r
+      if(dword(offset+4) == 0x54535953)\r
+      {\r
+        // less than 4GB?\r
+        if(dword(offset+0x0c) == 0)\r
+        {\r
+          // less than top of ram?\r
+          if(dword(offset+8) < TopOfRam)\r
+          {\r
+            return(dword(offset+8));\r
+          }\r
+        }\r
+      }\r
+    \r
+    }\r
+   \r
+    if(offset < 0x400000) break;\r
+    offset = offset - 0x400000; \r
+  }\r
+  \r
+  return 0;\r
+}\r
+.\r
+\r
+define /r ProcessImage(ImageBase)\r
+unsigned long ImageBase;\r
+{\r
+  $printf "ProcessImage %x", ImageBase$;\r
+}\r
+.\r
+\r
+define /r FindDebugInfo(SystemTable)\r
+unsigned long SystemTable;\r
+{\r
+  unsigned long   CfgTableEntries;\r
+  unsigned long   ConfigTable;\r
+  unsigned long   i;\r
+  unsigned long   offset;\r
+  unsigned long   dbghdr;\r
+  unsigned long   dbgentries;\r
+  unsigned long   dbgptr;\r
+  unsigned long   dbginfo;\r
+  unsigned long   loadedimg;\r
+  \r
+  $printf "FindDebugInfo"$;\r
+  \r
+  dbgentries = 0;\r
+  CfgTableEntries = dword(SystemTable + 0x40);\r
+  ConfigTable = dword(SystemTable + 0x44);\r
+  \r
+  $printf "config table is at %x (%d entries)", ConfigTable, CfgTableEntries$;\r
+  \r
+  // now search for debug info entry with guid 49152E77-1ADA-4764-B7A2-7AFEFED95E8B\r
+  //   0x49152E77      0x47641ADA      0xFE7AA2B7      0x8B5ED9FE\r
+  for(i=0; i<CfgTableEntries; i++)\r
+  {\r
+    offset = ConfigTable + (i*0x14);\r
+    if(dword(offset) == 0x49152E77)\r
+    {\r
+      if(dword(offset+4) == 0x47641ADA)\r
+      {\r
+        if(dword(offset+8) == 0xFE7AA2B7)\r
+        {\r
+          if(dword(offset+0xc) == 0x8B5ED9FE)\r
+          {\r
+            dbghdr = dword(offset+0x10);\r
+            dbgentries = dword(dbghdr + 4);\r
+            dbgptr = dword(dbghdr + 8);\r
+          }\r
+        }\r
+      }\r
+    }\r
+  }\r
+  \r
+  if(dbgentries == 0)\r
+  {\r
+    $printf "no debug entries found"$;\r
+    return;\r
+  }\r
+  \r
+  $printf "debug table at %x (%d entries)", dbgptr, dbgentries$;\r
+  \r
+  for(i=0; i<dbgentries; i++)\r
+  {\r
+    dbginfo = dword(dbgptr + (i*4));\r
+    if(dbginfo != 0)\r
+    {\r
+      if(dword(dbginfo) == 1) // normal debug info type\r
+      {\r
+        loadedimg = dword(dbginfo + 4);\r
+        ProcessPE32(dword(loadedimg + 0x20));\r
+      }\r
+    }\r
+  }\r
+}\r
+.\r
+\r
+define /r LoadDxe()\r
+{\r
+  unsigned long     maxmem;\r
+  unsigned long     systbl;\r
+  \r
+  $printf "LoadDxe"$;\r
+  \r
+  $fopen 50, 'C:\loadfiles.inc'$;\r
+  \r
+  maxmem = GetMaxMem();\r
+  systbl = FindSystemTable(maxmem);\r
+  if(systbl != 0)\r
+  {\r
+    $printf "found system table at %x",systbl$;\r
+    FindDebugInfo(systbl);\r
+  }\r
+  \r
+  $vclose 50$;\r
+}\r
+.\r
+\r
+define /r LoadRuntimeDxe()\r
+\r
+{\r
+  unsigned long   maxmem;\r
+  unsigned long   SystemTable;\r
+  unsigned long   CfgTableEntries;\r
+  unsigned long   ConfigTable;\r
+  unsigned long   i;\r
+  unsigned long   offset;\r
+  unsigned long   numentries;\r
+  unsigned long   RuntimeDebugInfo;\r
+  unsigned long   DebugInfoOffset;\r
+  unsigned long   imgbase;\r
+  \r
+  $printf "LoadRuntimeDxe"$;\r
+  \r
+  $fopen 50, 'C:\loadfiles.inc'$;\r
+  \r
+  RuntimeDebugInfo = 0x80000010;\r
+  \r
+  if(RuntimeDebugInfo != 0)\r
+  {\r
+    numentries = dword(RuntimeDebugInfo);\r
+    \r
+    $printf "runtime debug info is at %x (%d entries)", RuntimeDebugInfo, numentries$;\r
+    \r
+    DebugInfoOffset = RuntimeDebugInfo + 0x4;\r
+    for(i=0; i<numentries; i++)\r
+    {\r
+      imgbase = dword(DebugInfoOffset);\r
+      if(imgbase != 0)\r
+      {\r
+        $printf "found image at %x",imgbase$;\r
+        ProcessPE32(imgbase);\r
+      }\r
+      DebugInfoOffset = DebugInfoOffset + 0x4;\r
+    }\r
+  }\r
+  \r
+  $vclose 50$;\r
+}\r
+.\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_boot_from_ram.inc b/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_boot_from_ram.inc
new file mode 100644 (file)
index 0000000..6299a84
--- /dev/null
@@ -0,0 +1,21 @@
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//  
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+error = continue
+unload
+error = abort
+
+setreg @CP15_CONTROL = 0x0005107E
+setreg @pc=0x80008208
+setreg @cpsr=0x000000D3
+dis/D
+readfile,raw,nowarn "ZZZZZZ/FV/BEAGLEBOARD_EFI.fd"=0x80008000
+
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_convert_symbols.sh b/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_convert_symbols.sh
new file mode 100644 (file)
index 0000000..67fdfe1
--- /dev/null
@@ -0,0 +1,23 @@
+#!/bin/sh\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+#  \r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution.  The full text of the license may be found at\r
+#  http:#opensource.org/licenses/bsd-license.php\r
+#\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+\r
+IN=`/usr/bin/cygpath -u $1`\r
+OUT=`/usr/bin/cygpath -u $2`\r
+\r
+/usr/bin/sed -e "s/\/cygdrive\/\(.\)/load\/a\/ni\/np \"\1:/g" \\r
+             -e 's:\\:/:g' \\r
+             -e "s/^/load\/a\/ni\/np \"/g" \\r
+             -e "s/dll /dll\" \&/g" \\r
+              $IN | /usr/bin/sort.exe --key=3 --output=$OUT\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_hw_setup.inc b/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_hw_setup.inc
new file mode 100644 (file)
index 0000000..ea5f8ec
--- /dev/null
@@ -0,0 +1,67 @@
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//  
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+
+error = continue
+unload
+error = abort
+
+setreg @CP15_CONTROL = 0x0005107E
+setreg @cpsr=0x000000D3
+
+; General clock settings.
+setmem /32 0x48307270=0x00000080
+setmem /32 0x48306D40=0x00000003
+setmem /32 0x48005140=0x03020A50
+
+;Clock configuration
+setmem /32 0x48004A40=0x0000030A
+setmem /32 0x48004C40=0x00000015
+
+;DPLL3 (Core) settings
+setmem /32 0x48004D00=0x00370037
+setmem /32 0x48004D30=0x00000000
+setmem /32 0x48004D40=0x094C0C00
+
+;DPLL4 (Peripheral) settings
+setmem /32 0x48004D00=0x00370037
+setmem /32 0x48004D30=0x00000000
+setmem /32 0x48004D44=0x0001B00C
+setmem /32 0x48004D48=0x00000009
+
+;DPLL1 (MPU) settings
+setmem /32 0x48004904=0x00000037
+setmem /32 0x48004934=0x00000000
+setmem /32 0x48004940=0x0011F40C
+setmem /32 0x48004944=0x00000001
+setmem /32 0x48004948=0x00000000
+
+;RAM setup.
+setmem /16 0x6D000010=0x0000
+setmem /16 0x6D000040=0x0001
+setmem /16 0x6D000044=0x0100
+setmem /16 0x6D000048=0x0000
+setmem /32 0x6D000060=0x0000000A
+setmem /32 0x6D000070=0x00000081
+setmem /16 0x6D000040=0x0003
+setmem /32 0x6D000080=0x02D04011
+setmem /16 0x6D000084=0x0032
+setmem /16 0x6D00008C=0x0000
+setmem /32 0x6D00009C=0xBA9DC4C6
+setmem /32 0x6D0000A0=0x00012522
+setmem /32 0x6D0000A4=0x0004E201
+setmem /16 0x6D000040=0x0003
+setmem /32 0x6D0000B0=0x02D04011
+setmem /16 0x6D0000B4=0x0032
+setmem /16 0x6D0000BC=0x0000
+setmem /32 0x6D0000C4=0xBA9DC4C6
+setmem /32 0x6D0000C8=0x00012522
+setmem /32 0x6D0000D4=0x0004E201
\ No newline at end of file
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_load_symbols.inc b/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_load_symbols.inc
new file mode 100644 (file)
index 0000000..e093ccb
--- /dev/null
@@ -0,0 +1,23 @@
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+//  \r
+//  This program and the accompanying materials\r
+//  are licensed and made available under the terms and conditions of the BSD License\r
+//  which accompanies this distribution.  The full text of the license may be found at\r
+//  http://opensource.org/licenses/bsd-license.php\r
+//\r
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+\r
+include 'ZZZZZZ/rvi_symbols_macros.inc'\r
+\r
+macro write_symbols_file("ZZZZZZ/rvi_symbols.tmp", 0x00000000, 0x10000000)\r
+\r
+host "bash -o igncr ZZZZZZ/rvi_convert_symbols.sh ZZZZZZ/rvi_symbols.tmp ZZZZZZ/rvi_symbols.inc"\r
+include 'ZZZZZZ/rvi_symbols.inc'\r
+load /NI /NP 'ZZZZZZ/rvi_dummy.axf' ;.constdata\r
+unload rvi_dummy.axf\r
+delfile rvi_dummy.axf\r
+\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_symbols_macros.inc b/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_symbols_macros.inc
new file mode 100644 (file)
index 0000000..97d465e
--- /dev/null
@@ -0,0 +1,194 @@
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+//  \r
+//  This program and the accompanying materials\r
+//  are licensed and made available under the terms and conditions of the BSD License\r
+//  which accompanies this distribution.  The full text of the license may be found at\r
+//  http://opensource.org/licenses/bsd-license.php\r
+//\r
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+\r
+define /R int compare_guid(guid1, guid2)\r
+    unsigned char *guid1;\r
+    unsigned char *guid2;\r
+{\r
+    return strncmp(guid1, guid2, 16);\r
+}\r
+.\r
+\r
+define /R unsigned char * find_system_table(mem_start, mem_size)\r
+    unsigned char *mem_start;\r
+    unsigned long mem_size;\r
+{\r
+    unsigned char *mem_ptr;\r
+     \r
+    mem_ptr = mem_start + mem_size;\r
+    \r
+    do\r
+    {\r
+        mem_ptr -= 0x400000; // 4 MB\r
+        \r
+        if (strncmp(mem_ptr, "IBI SYST", 8) == 0)\r
+        {\r
+            return *(unsigned long *)(mem_ptr + 8); // EfiSystemTableBase\r
+        }        \r
+        \r
+    } while (mem_ptr > mem_start);\r
+    \r
+    return 0;\r
+}\r
+.\r
+\r
+define /R unsigned char * find_debug_info_table_header(system_table)\r
+    unsigned char *system_table;\r
+{\r
+    unsigned long configuration_table_entries;\r
+    unsigned char *configuration_table;\r
+    unsigned long index;\r
+    unsigned char debug_table_guid[16];\r
+    \r
+    // Fill in the debug table's guid\r
+    debug_table_guid[ 0] = 0x77;\r
+    debug_table_guid[ 1] = 0x2E;\r
+    debug_table_guid[ 2] = 0x15;\r
+    debug_table_guid[ 3] = 0x49;\r
+    debug_table_guid[ 4] = 0xDA;\r
+    debug_table_guid[ 5] = 0x1A;\r
+    debug_table_guid[ 6] = 0x64;\r
+    debug_table_guid[ 7] = 0x47;\r
+    debug_table_guid[ 8] = 0xB7;\r
+    debug_table_guid[ 9] = 0xA2;\r
+    debug_table_guid[10] = 0x7A;\r
+    debug_table_guid[11] = 0xFE;\r
+    debug_table_guid[12] = 0xFE;\r
+    debug_table_guid[13] = 0xD9;\r
+    debug_table_guid[14] = 0x5E;\r
+    debug_table_guid[15] = 0x8B;\r
+    \r
+    configuration_table_entries = *(unsigned long *)(system_table + 64);\r
+    configuration_table         = *(unsigned long *)(system_table + 68);\r
+    \r
+    for (index = 0; index < configuration_table_entries; index++)\r
+    {\r
+        if (compare_guid(configuration_table, debug_table_guid) == 0)\r
+        {\r
+            return *(unsigned long *)(configuration_table + 16);\r
+        }\r
+        \r
+        configuration_table += 20;\r
+    }\r
+    \r
+    return 0;\r
+}\r
+.\r
+\r
+define /R int valid_pe_header(header)\r
+        unsigned char *header;\r
+{\r
+    if ((header[0x00] == 'M') &&\r
+        (header[0x01] == 'Z') &&\r
+        (header[0x80] == 'P') &&\r
+        (header[0x81] == 'E'))\r
+    {\r
+        return 1;\r
+    }\r
+    \r
+    return 0;\r
+}\r
+.\r
+\r
+define /R unsigned long pe_headersize(header)\r
+        unsigned char *header;\r
+{\r
+    unsigned long *size;\r
+    \r
+    size = header + 0x00AC;\r
+    \r
+    return *size;\r
+}\r
+.\r
+\r
+define /R unsigned char *pe_filename(header)\r
+        unsigned char *header;\r
+{\r
+    unsigned long *debugOffset;\r
+    unsigned char *stringOffset;\r
+   \r
+    if (valid_pe_header(header))\r
+    {\r
+        debugOffset  = header + 0x0128;\r
+        stringOffset = header + *debugOffset + 0x002C;\r
+       \r
+        return stringOffset;\r
+    }\r
+   \r
+    return 0;\r
+}\r
+.\r
+\r
+define /R int char_is_valid(c)\r
+        unsigned char c;\r
+{\r
+    if (c >= 32 && c < 127)\r
+       return 1;\r
+\r
+    return 0;\r
+}\r
+.\r
+\r
+define /R write_symbols_file(filename, mem_start, mem_size)\r
+    unsigned char *filename;\r
+    unsigned char *mem_start;\r
+    unsigned long mem_size;    \r
+{\r
+    unsigned char *system_table;\r
+    unsigned char *debug_info_table_header;\r
+    unsigned char *debug_info_table;\r
+    unsigned long debug_info_table_size;\r
+    unsigned long index;\r
+    unsigned char *debug_image_info;\r
+    unsigned char *loaded_image_protocol;\r
+    unsigned char *image_base;\r
+    unsigned char *debug_filename;\r
+    unsigned long header_size;\r
+    int           status;\r
+    \r
+    system_table = find_system_table(mem_start, mem_size);\r
+    if (system_table == 0)\r
+    {\r
+        return;\r
+    }\r
+    \r
+    status = fopen(88, filename, "w");\r
+    \r
+    debug_info_table_header = find_debug_info_table_header(system_table);\r
+    \r
+    debug_info_table      = *(unsigned long *)(debug_info_table_header + 8);\r
+    debug_info_table_size = *(unsigned long *)(debug_info_table_header + 4);\r
+    \r
+    for (index = 0; index < (debug_info_table_size * 4); index += 4)\r
+    {\r
+        debug_image_info = *(unsigned long *)(debug_info_table + index); \r
+        \r
+        if (debug_image_info == 0)\r
+        {\r
+            break;\r
+        }\r
+        \r
+        loaded_image_protocol = *(unsigned long *)(debug_image_info + 4);\r
+        \r
+        image_base = *(unsigned long *)(loaded_image_protocol + 32);\r
+        \r
+        debug_filename = pe_filename(image_base);\r
+        header_size    = pe_headersize(image_base);\r
+    \r
+        $fprintf 88, "%s 0x%08x\n", debug_filename, image_base + header_size$;\r
+    }\r
+    \r
+    \r
+    fclose(88);\r
+}\r
+.\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_unload_symbols.inc b/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts/rvi_unload_symbols.inc
new file mode 100644 (file)
index 0000000..f85f442
--- /dev/null
@@ -0,0 +1,118 @@
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+//  \r
+//  This program and the accompanying materials\r
+//  are licensed and made available under the terms and conditions of the BSD License\r
+//  which accompanies this distribution.  The full text of the license may be found at\r
+//  http://opensource.org/licenses/bsd-license.php\r
+//\r
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+\r
+error = continue\r
+\r
+unload\r
+\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+\r
+error = abort\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.c b/ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.c
new file mode 100644 (file)
index 0000000..38bd2ed
--- /dev/null
@@ -0,0 +1,417 @@
+/*++\r
+RealView EB FVB DXE Driver\r
+\r
+Copyright (c) 2010, Apple Inc. All rights reserved.<BR>                                                         \r
+This program and the accompanying materials                          \r
+are licensed and made available under the terms and conditions of the BSD License         \r
+which accompanies this distribution.  The full text of the license may be found at        \r
+http://opensource.org/licenses/bsd-license.php                                            \r
+                                                                                          \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.   \r
+\r
+\r
+--*/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+\r
+\r
+\r
+/**\r
+  The GetAttributes() function retrieves the attributes and\r
+  current settings of the block.\r
+\r
+  @param This       Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+\r
+  @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the\r
+                    attributes and current settings are\r
+                    returned. Type EFI_FVB_ATTRIBUTES_2 is defined\r
+                    in EFI_FIRMWARE_VOLUME_HEADER.\r
+\r
+  @retval EFI_SUCCESS The firmware volume attributes were\r
+                      returned.\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetAttributes (\r
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+  OUT       EFI_FVB_ATTRIBUTES_2                *Attributes\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+  The SetAttributes() function sets configurable firmware volume\r
+  attributes and returns the new settings of the firmware volume.\r
+  \r
+\r
+  @param This         Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+\r
+  @param Attributes   On input, Attributes is a pointer to\r
+                      EFI_FVB_ATTRIBUTES_2 that contains the\r
+                      desired firmware volume settings. On\r
+                      successful return, it contains the new\r
+                      settings of the firmware volume. Type\r
+                      EFI_FVB_ATTRIBUTES_2 is defined in\r
+                      EFI_FIRMWARE_VOLUME_HEADER.\r
+  \r
+  @retval EFI_SUCCESS           The firmware volume attributes were returned.\r
+\r
+  @retval EFI_INVALID_PARAMETER The attributes requested are in\r
+                                conflict with the capabilities\r
+                                as declared in the firmware\r
+                                volume header.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbSetAttributes (\r
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+  IN OUT    EFI_FVB_ATTRIBUTES_2                *Attributes\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+  The GetPhysicalAddress() function retrieves the base address of\r
+  a memory-mapped firmware volume. This function should be called\r
+  only for memory-mapped firmware volumes.\r
+\r
+  @param This     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+  \r
+  @param Address  Pointer to a caller-allocated\r
+                  EFI_PHYSICAL_ADDRESS that, on successful\r
+                  return from GetPhysicalAddress(), contains the\r
+                  base address of the firmware volume.\r
+  \r
+  @retval EFI_SUCCESS       The firmware volume base address was returned.\r
+  \r
+  @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetPhysicalAddress (\r
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+  OUT       EFI_PHYSICAL_ADDRESS                *Address\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+  The GetBlockSize() function retrieves the size of the requested\r
+  block. It also returns the number of additional blocks with\r
+  the identical size. The GetBlockSize() function is used to\r
+  retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).\r
+\r
+\r
+  @param This           Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+\r
+  @param Lba            Indicates the block for which to return the size.\r
+\r
+  @param BlockSize      Pointer to a caller-allocated UINTN in which\r
+                        the size of the block is returned.\r
+\r
+  @param NumberOfBlocks Pointer to a caller-allocated UINTN in\r
+                        which the number of consecutive blocks,\r
+                        starting with Lba, is returned. All\r
+                        blocks in this range have a size of\r
+                        BlockSize.\r
+\r
+  \r
+  @retval EFI_SUCCESS             The firmware volume base address was returned.\r
+  \r
+  @retval EFI_INVALID_PARAMETER   The requested LBA is out of range.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetBlockSize (\r
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+  IN        EFI_LBA                             Lba,\r
+  OUT       UINTN                               *BlockSize,\r
+  OUT       UINTN                               *NumberOfBlocks\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+\r
+/**\r
+  Reads the specified number of bytes into a buffer from the specified block.\r
+\r
+  The Read() function reads the requested number of bytes from the\r
+  requested block and stores them in the provided buffer.\r
+  Implementations should be mindful that the firmware volume\r
+  might be in the ReadDisabled state. If it is in this state,\r
+  the Read() function must return the status code\r
+  EFI_ACCESS_DENIED without modifying the contents of the\r
+  buffer. The Read() function must also prevent spanning block\r
+  boundaries. If a read is requested that would span a block\r
+  boundary, the read must read up to the boundary but not\r
+  beyond. The output parameter NumBytes must be set to correctly\r
+  indicate the number of bytes actually read. The caller must be\r
+  aware that a read may be partially completed.\r
+\r
+  @param This     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+  \r
+  @param Lba      The starting logical block index\r
+                  from which to read.\r
+\r
+  @param Offset   Offset into the block at which to begin reading.\r
+\r
+  @param NumBytes Pointer to a UINTN. At entry, *NumBytes\r
+                  contains the total size of the buffer. At\r
+                  exit, *NumBytes contains the total number of\r
+                  bytes read.\r
+\r
+  @param Buffer   Pointer to a caller-allocated buffer that will\r
+                  be used to hold the data that is read.\r
+\r
+  @retval EFI_SUCCESS         The firmware volume was read successfully,\r
+                              and contents are in Buffer.\r
+  \r
+  @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA\r
+                              boundary. On output, NumBytes\r
+                              contains the total number of bytes\r
+                              returned in Buffer.\r
+  \r
+  @retval EFI_ACCESS_DENIED   The firmware volume is in the\r
+                              ReadDisabled state.\r
+  \r
+  @retval EFI_DEVICE_ERROR    The block device is not\r
+                              functioning correctly and could\r
+                              not be read.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbRead (\r
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+  IN        EFI_LBA                             Lba,\r
+  IN        UINTN                               Offset,\r
+  IN OUT    UINTN                               *NumBytes,\r
+  IN OUT    UINT8                               *Buffer\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+  Writes the specified number of bytes from the input buffer to the block.\r
+\r
+  The Write() function writes the specified number of bytes from\r
+  the provided buffer to the specified block and offset. If the\r
+  firmware volume is sticky write, the caller must ensure that\r
+  all the bits of the specified range to write are in the\r
+  EFI_FVB_ERASE_POLARITY state before calling the Write()\r
+  function, or else the result will be unpredictable. This\r
+  unpredictability arises because, for a sticky-write firmware\r
+  volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY\r
+  state but cannot flip it back again.  Before calling the\r
+  Write() function,  it is recommended for the caller to first call \r
+  the EraseBlocks() function to erase the specified block to\r
+  write. A block erase cycle will transition bits from the\r
+  (NOT)EFI_FVB_ERASE_POLARITY state back to the\r
+  EFI_FVB_ERASE_POLARITY state. Implementations should be\r
+  mindful that the firmware volume might be in the WriteDisabled\r
+  state. If it is in this state, the Write() function must\r
+  return the status code EFI_ACCESS_DENIED without modifying the\r
+  contents of the firmware volume. The Write() function must\r
+  also prevent spanning block boundaries. If a write is\r
+  requested that spans a block boundary, the write must store up\r
+  to the boundary but not beyond. The output parameter NumBytes\r
+  must be set to correctly indicate the number of bytes actually\r
+  written. The caller must be aware that a write may be\r
+  partially completed. All writes, partial or otherwise, must be\r
+  fully flushed to the hardware before the Write() service\r
+  returns.\r
+\r
+  @param This     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+  \r
+  @param Lba      The starting logical block index to write to.\r
+  \r
+  @param Offset   Offset into the block at which to begin writing.\r
+  \r
+  @param NumBytes The pointer to a UINTN. At entry, *NumBytes\r
+                  contains the total size of the buffer. At\r
+                  exit, *NumBytes contains the total number of\r
+                  bytes actually written.\r
+  \r
+  @param Buffer   The pointer to a caller-allocated buffer that\r
+                  contains the source for the write.\r
+  \r
+  @retval EFI_SUCCESS         The firmware volume was written successfully.\r
+  \r
+  @retval EFI_BAD_BUFFER_SIZE The write was attempted across an\r
+                              LBA boundary. On output, NumBytes\r
+                              contains the total number of bytes\r
+                              actually written.\r
+  \r
+  @retval EFI_ACCESS_DENIED   The firmware volume is in the\r
+                              WriteDisabled state.\r
+  \r
+  @retval EFI_DEVICE_ERROR    The block device is malfunctioning\r
+                              and could not be written.\r
+\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbWrite (\r
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+  IN        EFI_LBA                             Lba,\r
+  IN        UINTN                               Offset,\r
+  IN OUT    UINTN                               *NumBytes,\r
+  IN        UINT8                               *Buffer\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+  Erases and initializes a firmware volume block.\r
+\r
+  The EraseBlocks() function erases one or more blocks as denoted\r
+  by the variable argument list. The entire parameter list of\r
+  blocks must be verified before erasing any blocks. If a block is\r
+  requested that does not exist within the associated firmware\r
+  volume (it has a larger index than the last block of the\r
+  firmware volume), the EraseBlocks() function must return the\r
+  status code EFI_INVALID_PARAMETER without modifying the contents\r
+  of the firmware volume. Implementations should be mindful that\r
+  the firmware volume might be in the WriteDisabled state. If it\r
+  is in this state, the EraseBlocks() function must return the\r
+  status code EFI_ACCESS_DENIED without modifying the contents of\r
+  the firmware volume. All calls to EraseBlocks() must be fully\r
+  flushed to the hardware before the EraseBlocks() service\r
+  returns.\r
+\r
+  @param This   Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL\r
+                instance.\r
+\r
+  @param ...    The variable argument list is a list of tuples.\r
+                Each tuple describes a range of LBAs to erase\r
+                and consists of the following:\r
+                - An EFI_LBA that indicates the starting LBA\r
+                - A UINTN that indicates the number of blocks to\r
+                  erase.\r
+\r
+                The list is terminated with an\r
+                EFI_LBA_LIST_TERMINATOR. For example, the\r
+                following indicates that two ranges of blocks\r
+                (5-7 and 10-11) are to be erased: EraseBlocks\r
+                (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);\r
+\r
+  @retval EFI_SUCCESS The erase request successfully\r
+                      completed.\r
+  \r
+  @retval EFI_ACCESS_DENIED   The firmware volume is in the\r
+                              WriteDisabled state.\r
+  @retval EFI_DEVICE_ERROR  The block device is not functioning\r
+                            correctly and could not be written.\r
+                            The firmware device may have been\r
+                            partially erased.\r
+  @retval EFI_INVALID_PARAMETER One or more of the LBAs listed\r
+                                in the variable argument list do\r
+                                not exist in the firmware volume.  \r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbEraseBlocks (\r
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+  ...\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+//\r
+// Making this global saves a few bytes in image size\r
+//\r
+EFI_HANDLE  gFvbHandle = NULL;\r
+\r
+\r
+///\r
+/// The Firmware Volume Block Protocol is the low-level interface\r
+/// to a firmware volume. File-level access to a firmware volume\r
+/// should not be done using the Firmware Volume Block Protocol.\r
+/// Normal access to a firmware volume must use the Firmware\r
+/// Volume Protocol. Typically, only the file system driver that\r
+/// produces the Firmware Volume Protocol will bind to the\r
+/// Firmware Volume Block Protocol.\r
+///\r
+EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL gFvbProtocol = {\r
+  FvbGetAttributes,\r
+  FvbSetAttributes,\r
+  FvbGetPhysicalAddress,\r
+  FvbGetBlockSize,\r
+  FvbRead,\r
+  FvbWrite,\r
+  FvbEraseBlocks,\r
+  ///\r
+  /// The handle of the parent firmware volume.\r
+  ///  \r
+  NULL\r
+};\r
+\r
+//     NvStorageVariableBase = (EFI_PHYSICAL_ADDRESS) FixedPcdGet32 (PcdFlashNvStorageVariableBase);\r
+\r
+\r
+/**\r
+  Initialize the state information for the CPU Architectural Protocol\r
+\r
+  @param  ImageHandle   of the loaded driver\r
+  @param  SystemTable   Pointer to the System Table\r
+\r
+  @retval EFI_SUCCESS           Protocol registered\r
+  @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure\r
+  @retval EFI_DEVICE_ERROR      Hardware problems\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbDxeInitialize (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  \r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                  &gFvbHandle,\r
+                  &gEfiFirmwareVolumeBlockProtocolGuid,   &gFvbProtocol,\r
+                  NULL\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+  \r
+  // SetVertAddressEvent ()\r
+  \r
+  // GCD Map NAND as RT\r
+  \r
+  return Status;\r
+}\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf b/ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf
new file mode 100644 (file)
index 0000000..b8e66fc
--- /dev/null
@@ -0,0 +1,53 @@
+#/** @file\r
+#  \r
+#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution.  The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  \r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#  \r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = FvbDxe\r
+  FILE_GUID                      = 43ECE281-D9E2-4DD0-B304-E6A5689256F4\r
+  MODULE_TYPE                    = DXE_RUNTIME_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+\r
+  ENTRY_POINT                    = FvbDxeInitialize\r
+\r
+\r
+[Sources.common]\r
+  FvbDxe.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  EmbeddedPkg/EmbeddedPkg.dec\r
+  ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  UefiLib\r
+  UefiBootServicesTableLib\r
+  DebugLib\r
+  PrintLib\r
+  UefiDriverEntryPoint\r
+  IoLib\r
+\r
+[Guids]\r
+  \r
+\r
+[Protocols]\r
+  gEfiFirmwareVolumeBlockProtocolGuid\r
+\r
+[FixedPcd.common]\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+\r
+[depex]\r
+  TRUE\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h b/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h
new file mode 100644 (file)
index 0000000..17f1983
--- /dev/null
@@ -0,0 +1,137 @@
+/** @file\r
+*  Header defining RealView EB constants (Base addresses, sizes, flags)\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  \r
+*  This program and the accompanying materials                          \r
+*  are licensed and made available under the terms and conditions of the BSD License         \r
+*  which accompanies this distribution.  The full text of the license may be found at        \r
+*  http://opensource.org/licenses/bsd-license.php                                            \r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*\r
+**/\r
+\r
+#ifndef __ARM_EB_H__\r
+#define __ARM_EB_H__\r
+\r
+/*******************************************\r
+// Platform Memory Map\r
+*******************************************/\r
+\r
+// Can be NOR, DOC, DRAM, SRAM\r
+#define ARM_EB_REMAP_BASE                       0x00000000\r
+#define ARM_EB_REMAP_SZ                         0x04000000\r
+\r
+// Motherboard Peripheral and On-chip peripheral\r
+#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE       0x10000000\r
+#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ         0x00100000\r
+#define ARM_EB_BOARD_PERIPH_BASE                0x10000000\r
+//#define ARM_EB_CHIP_PERIPH_BASE                 0x10020000\r
+\r
+// SMC\r
+#define ARM_EB_SMC_BASE                         0x40000000\r
+#define ARM_EB_SMC_SZ                           0x20000000\r
+\r
+// NOR Flash 1\r
+#define ARM_EB_SMB_NOR_BASE                     0x40000000\r
+#define ARM_EB_SMB_NOR_SZ                       0x04000000 /* 64 MB */\r
+// DOC Flash\r
+#define ARM_EB_SMB_DOC_BASE                     0x44000000\r
+#define ARM_EB_SMB_DOC_SZ                       0x04000000 /* 64 MB */\r
+// SRAM\r
+#define ARM_EB_SMB_SRAM_BASE                    0x48000000\r
+#define ARM_EB_SMB_SRAM_SZ                      0x02000000 /* 32 MB */\r
+// USB, Ethernet, VRAM\r
+#define ARM_EB_SMB_PERIPH_BASE                  0x4E000000\r
+//#define ARM_EB_SMB_PERIPH_VRAM                  0x4C000000\r
+#define ARM_EB_SMB_PERIPH_SZ                    0x02000000 /* 32 MB */\r
+\r
+// DRAM\r
+#define ARM_EB_DRAM_BASE                        0x70000000\r
+#define ARM_EB_DRAM_SZ                          0x10000000\r
+\r
+// Logic Tile\r
+#define ARM_EB_LOGIC_TILE_BASE                     0xC0000000\r
+#define ARM_EB_LOGIC_TILE_SZ                       0x40000000\r
+\r
+/*******************************************\r
+// Motherboard peripherals\r
+*******************************************/\r
+\r
+// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r
+#define ARM_EB_SYS_FLAGS_REG                    (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_EB_SYS_FLAGS_SET_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_EB_SYS_FLAGS_CLR_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
+#define ARM_EB_SYS_FLAGS_NV_REG                 (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_EB_SYS_FLAGS_NV_SET_REG             (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_EB_SYS_FLAGS_NV_CLR_REG             (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
+#define ARM_EB_SYS_PROCID0_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
+#define ARM_EB_SYS_PROCID1_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
+#define ARM_EB_SYS_CFGDATA_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
+#define ARM_EB_SYS_CFGCTRL_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
+#define ARM_EB_SYS_CFGSTAT_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
+\r
+// SP810 Controller\r
+#define SP810_CTRL_BASE                      (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
+\r
+// SYSTRCL Register\r
+#define ARM_EB_SYSCTRL                                                                                 0x10001000\r
+\r
+// Uart0\r
+#define PL011_CONSOLE_UART_BASE                (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
+#define PL011_CONSOLE_UART_SPEED            115200\r
+\r
+// SP804 Timer Bases\r
+#define SP804_TIMER0_BASE                    (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
+#define SP804_TIMER1_BASE                    (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
+#define SP804_TIMER2_BASE                    (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
+#define SP804_TIMER3_BASE                    (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
+\r
+// Dynamic Memory Controller Base\r
+#define ARM_EB_DMC_BASE                     0x10018000\r
+\r
+// Static Memory Controller Base\r
+#define ARM_EB_SMC_CTRL_BASE                    0x10080000\r
+\r
+/*// System Configuration Controller register Base addresses\r
+//#define ARM_EB_SYS_CFG_CTRL_BASE                0x100E2000\r
+#define ARM_EB_SYS_CFGRW0_REG                   0x100E2000\r
+#define ARM_EB_SYS_CFGRW1_REG                   0x100E2004\r
+#define ARM_EB_SYS_CFGRW2_REG                   0x100E2008\r
+\r
+#define ARM_EB_CFGRW1_REMAP_NOR0                0\r
+#define ARM_EB_CFGRW1_REMAP_NOR1                (1 << 28)\r
+#define ARM_EB_CFGRW1_REMAP_EXT_AXI             (1 << 29)\r
+#define ARM_EB_CFGRW1_REMAP_DRAM                (1 << 30)\r
+\r
+// PL301 Fast AXI Base Address\r
+#define ARM_EB_FAXI_BASE                        0x100E9000\r
+\r
+// L2x0 Cache Controller Base Address\r
+//#define ARM_EB_L2x0_CTLR_BASE                   0x1E00A000*/\r
+\r
+\r
+/*******************************************\r
+// Interrupt Map\r
+*******************************************/\r
+\r
+// Timer Interrupts\r
+#define TIMER01_INTERRUPT_NUM                34\r
+#define TIMER23_INTERRUPT_NUM                35\r
+\r
+\r
+/*******************************************\r
+// EFI Memory Map in Permanent Memory (DRAM)\r
+*******************************************/\r
+\r
+// This region is allocated at the bottom of the DRAM. It will be used\r
+// for fixed address allocations such as Vector Table\r
+#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ        SIZE_8MB\r
+\r
+// This region is the memory declared to PEI as permanent memory for PEI\r
+// and DXE. EFI stacks and heaps will be declared in this region.\r
+#define ARM_EB_EFI_MEMORY_REGION_SZ             0x1000000\r
+\r
+#endif \r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.c b/ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.c
new file mode 100644 (file)
index 0000000..b9e8256
--- /dev/null
@@ -0,0 +1,484 @@
+/*++\r
+\r
+Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>                                                         \r
+This program and the accompanying materials                          \r
+are licensed and made available under the terms and conditions of the BSD License         \r
+which accompanies this distribution.  The full text of the license may be found at        \r
+http://opensource.org/licenses/bsd-license.php                                            \r
+                                                                                          \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.   \r
+\r
+Module Name:\r
+\r
+  Gic.c\r
+\r
+Abstract:\r
+\r
+  Driver implementing the GIC interrupt controller protocol\r
+\r
+--*/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+\r
+#include <Protocol/Cpu.h>\r
+#include <Protocol/HardwareInterrupt.h>\r
+\r
+\r
+//\r
+// EB board definitions\r
+//\r
+#define EB_GIC1_CPU_INTF_BASE   0x10040000\r
+#define EB_GIC1_DIST_BASE       0x10041000\r
+#define EB_GIC2_CPU_INTF_BASE   0x10050000\r
+#define EB_GIC2_DIST_BASE       0x10051000\r
+#define EB_GIC3_CPU_INTF_BASE   0x10060000\r
+#define EB_GIC3_DIST_BASE       0x10061000\r
+#define EB_GIC4_CPU_INTF_BASE   0x10070000\r
+#define EB_GIC5_DIST_BASE       0x10071000\r
+\r
+// number of interrupts sources supported by each GIC on the EB\r
+#define EB_NUM_GIC_INTERRUPTS   96  \r
+\r
+// number of 32-bit registers needed to represent those interrupts as a bit\r
+// (used for enable set, enable clear, pending set, pending clear, and active regs)\r
+#define EB_NUM_GIC_REG_PER_INT_BITS   (EB_NUM_GIC_INTERRUPTS / 32)\r
+\r
+// number of 32-bit registers needed to represent those interrupts as two bits\r
+// (used for configuration reg)\r
+#define EB_NUM_GIC_REG_PER_INT_CFG    (EB_NUM_GIC_INTERRUPTS / 16)\r
+\r
+// number of 32-bit registers needed to represent interrupts as 8-bit priority field\r
+// (used for priority regs)\r
+#define EB_NUM_GIC_REG_PER_INT_BYTES  (EB_NUM_GIC_INTERRUPTS / 4)\r
+\r
+#define GIC_DEFAULT_PRIORITY  0x80\r
+\r
+//\r
+// GIC definitions\r
+//\r
+\r
+// Distributor\r
+#define GIC_ICDDCR          0x000 // Distributor Control Register\r
+#define GIC_ICDICTR         0x004 // Interrupt Controller Type Register\r
+#define GIC_ICDIIDR         0x008 // Implementer Identification Register\r
+\r
+// each reg base below repeats for EB_NUM_GIC_REG_PER_INT_BITS (see GIC spec)\r
+#define GIC_ICDISR          0x080 // Interrupt Security Registers\r
+#define GIC_ICDISER         0x100 // Interrupt Set-Enable Registers\r
+#define GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers\r
+#define GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers\r
+#define GIC_ICDCPR          0x280 // Interrupt Clear-Pending Registers\r
+#define GIC_ICDABR          0x300 // Active Bit Registers\r
+\r
+// each reg base below repeats for EB_NUM_GIC_REG_PER_INT_BYTES\r
+#define GIC_ICDIPR          0x400 // Interrupt Priority Registers\r
+\r
+// each reg base below repeats for EB_NUM_GIC_INTERRUPTS\r
+#define GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers\r
+#define GIC_ICDICFR         0xC00 // Interrupt Configuration Registers\r
+\r
+// just one of these\r
+#define GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register\r
+\r
+\r
+// Cpu interface\r
+#define GIC_ICCICR          0x00  // CPU Interface Controler Register\r
+#define GIC_ICCPMR          0x04  // Interrupt Priority Mask Register\r
+#define GIC_ICCBPR          0x08  // Binary Point Register\r
+#define GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register\r
+#define GIC_ICCEIOR         0x10  // End Of Interrupt Register\r
+#define GIC_ICCRPR          0x14  // Running Priority Register\r
+#define GIC_ICCPIR          0x18  // Highest Pending Interrupt Register\r
+#define GIC_ICCABPR         0x1C  // Aliased Binary Point Register\r
+#define GIC_ICCIDR          0xFC  // Identification Register\r
+\r
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;\r
+\r
+//\r
+// Notifications\r
+//\r
+VOID      *CpuProtocolNotificationToken = NULL;\r
+EFI_EVENT CpuProtocolNotificationEvent  = (EFI_EVENT)NULL;\r
+EFI_EVENT EfiExitBootServicesEvent      = (EFI_EVENT)NULL;\r
+\r
+\r
+HARDWARE_INTERRUPT_HANDLER  gRegisteredInterruptHandlers[EB_NUM_GIC_INTERRUPTS];\r
+\r
+/**\r
+  Register Handler for the specified interrupt source.\r
+\r
+  @param This     Instance pointer for this protocol\r
+  @param Source   Hardware source of the interrupt\r
+  @param Handler  Callback for interrupt. NULL to unregister\r
+\r
+  @retval EFI_SUCCESS Source was updated to support Handler.\r
+  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RegisterInterruptSource (\r
+  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
+  IN HARDWARE_INTERRUPT_SOURCE          Source,\r
+  IN HARDWARE_INTERRUPT_HANDLER         Handler\r
+  )\r
+{\r
+  if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+    ASSERT(FALSE);\r
+    return EFI_UNSUPPORTED;\r
+  } \r
+  \r
+  if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {\r
+    return EFI_ALREADY_STARTED;\r
+  }\r
+\r
+  gRegisteredInterruptHandlers[Source] = Handler;\r
+  return This->EnableInterruptSource(This, Source);\r
+}\r
+\r
+\r
+/**\r
+  Enable interrupt source Source.\r
+\r
+  @param This     Instance pointer for this protocol\r
+  @param Source   Hardware source of the interrupt\r
+\r
+  @retval EFI_SUCCESS       Source interrupt enabled.\r
+  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EnableInterruptSource (\r
+  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
+  IN HARDWARE_INTERRUPT_SOURCE          Source\r
+  )\r
+{\r
+  UINT32    RegOffset;\r
+  UINTN     RegShift;\r
+  \r
+  if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+    ASSERT(FALSE);\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  \r
+  // calculate enable register offset and bit position\r
+  RegOffset = Source / 32;\r
+  RegShift = Source % 32;\r
+\r
+  // write set-enable register\r
+  MmioWrite32 (EB_GIC1_DIST_BASE+GIC_ICDISER+(4*RegOffset), 1 << RegShift);\r
+  \r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Disable interrupt source Source.\r
+\r
+  @param This     Instance pointer for this protocol\r
+  @param Source   Hardware source of the interrupt\r
+\r
+  @retval EFI_SUCCESS       Source interrupt disabled.\r
+  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+DisableInterruptSource (\r
+  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
+  IN HARDWARE_INTERRUPT_SOURCE          Source\r
+  )\r
+{\r
+  UINT32    RegOffset;\r
+  UINTN     RegShift;\r
+  \r
+  if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+    ASSERT(FALSE);\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  \r
+  // calculate enable register offset and bit position\r
+  RegOffset = Source / 32;\r
+  RegShift = Source % 32;\r
+\r
+  // write set-enable register\r
+  MmioWrite32 (EB_GIC1_DIST_BASE+GIC_ICDICER+(4*RegOffset), 1 << RegShift);\r
+  \r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+\r
+/**\r
+  Return current state of interrupt source Source.\r
+\r
+  @param This     Instance pointer for this protocol\r
+  @param Source   Hardware source of the interrupt\r
+  @param InterruptState  TRUE: source enabled, FALSE: source disabled.\r
+\r
+  @retval EFI_SUCCESS       InterruptState is valid\r
+  @retval EFI_DEVICE_ERROR  InterruptState is not valid\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetInterruptSourceState (\r
+  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
+  IN HARDWARE_INTERRUPT_SOURCE          Source,\r
+  IN BOOLEAN                            *InterruptState\r
+  )\r
+{\r
+  UINT32    RegOffset;\r
+  UINTN     RegShift;\r
+  \r
+  if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+    ASSERT(FALSE);\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  \r
+  // calculate enable register offset and bit position\r
+  RegOffset = Source / 32;\r
+  RegShift = Source % 32;\r
+    \r
+  if ((MmioRead32 (EB_GIC1_DIST_BASE+GIC_ICDISER+(4*RegOffset)) & (1<<RegShift)) == 0) {\r
+    *InterruptState = FALSE;\r
+  } else {\r
+    *InterruptState = TRUE;\r
+  }\r
+  \r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Signal to the hardware that the End Of Intrrupt state \r
+  has been reached.\r
+\r
+  @param This     Instance pointer for this protocol\r
+  @param Source   Hardware source of the interrupt\r
+\r
+  @retval EFI_SUCCESS       Source interrupt EOI'ed.\r
+  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EndOfInterrupt (\r
+  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
+  IN HARDWARE_INTERRUPT_SOURCE          Source\r
+  )\r
+{\r
+  if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+    ASSERT(FALSE);\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  MmioWrite32 (EB_GIC1_CPU_INTF_BASE+GIC_ICCEIOR, Source);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
+\r
+  @param  InterruptType    Defines the type of interrupt or exception that\r
+                           occurred on the processor.This parameter is processor architecture specific.\r
+  @param  SystemContext    A pointer to the processor context when\r
+                           the interrupt occurred on the processor.\r
+\r
+  @return None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IrqInterruptHandler (\r
+  IN EFI_EXCEPTION_TYPE           InterruptType,\r
+  IN EFI_SYSTEM_CONTEXT           SystemContext\r
+  )\r
+{\r
+  UINT32                      GicInterrupt;\r
+  HARDWARE_INTERRUPT_HANDLER  InterruptHandler;\r
+\r
+  GicInterrupt = MmioRead32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCIAR);\r
+  if (GicInterrupt >= EB_NUM_GIC_INTERRUPTS) {\r
+    MmioWrite32 (EB_GIC1_CPU_INTF_BASE+GIC_ICCEIOR, GicInterrupt);\r
+  }\r
+  \r
+  InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r
+  if (InterruptHandler != NULL) {\r
+    // Call the registered interrupt handler.\r
+    InterruptHandler (GicInterrupt, SystemContext);\r
+  } else {\r
+    DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: %x\n", GicInterrupt));\r
+  }\r
+\r
+  EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);\r
+}\r
+\r
+\r
+//\r
+// Making this global saves a few bytes in image size\r
+//\r
+EFI_HANDLE  gHardwareInterruptHandle = NULL;\r
+\r
+//\r
+// The protocol instance produced by this driver\r
+//\r
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {\r
+  RegisterInterruptSource,\r
+  EnableInterruptSource,\r
+  DisableInterruptSource,\r
+  GetInterruptSourceState,\r
+  EndOfInterrupt\r
+};\r
+\r
+\r
+/**\r
+  Shutdown our hardware\r
+  \r
+  DXE Core will disable interrupts and turn off the timer and disable interrupts\r
+  after all the event handlers have run.\r
+\r
+  @param[in]  Event   The Event that is being processed\r
+  @param[in]  Context Event Context\r
+**/\r
+VOID\r
+EFIAPI\r
+ExitBootServicesEvent (\r
+  IN EFI_EVENT  Event,\r
+  IN VOID       *Context\r
+  )\r
+{\r
+  UINTN    i;\r
+  \r
+  for (i = 0; i < EB_NUM_GIC_INTERRUPTS; i++) {\r
+    DisableInterruptSource (&gHardwareInterruptProtocol, i);\r
+  }\r
+}\r
+\r
+\r
+//\r
+// Notification routines\r
+//\r
+VOID\r
+CpuProtocolInstalledNotification (\r
+  IN EFI_EVENT   Event,\r
+  IN VOID        *Context\r
+  )\r
+{\r
+  EFI_STATUS              Status;\r
+  EFI_CPU_ARCH_PROTOCOL   *Cpu;\r
+  \r
+  //\r
+  // Get the cpu protocol that this driver requires.\r
+  //\r
+  Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Unregister the default exception handler.\r
+  //\r
+  Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Register to receive interrupts\r
+  //\r
+  Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);\r
+  ASSERT_EFI_ERROR(Status);\r
+}\r
+\r
+/**\r
+  Initialize the state information for the CPU Architectural Protocol\r
+\r
+  @param  ImageHandle   of the loaded driver\r
+  @param  SystemTable   Pointer to the System Table\r
+\r
+  @retval EFI_SUCCESS           Protocol registered\r
+  @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure\r
+  @retval EFI_DEVICE_ERROR      Hardware problems\r
+\r
+**/\r
+EFI_STATUS\r
+InterruptDxeInitialize (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINTN      i;\r
+  UINT32      RegOffset;\r
+  UINTN       RegShift;\r
+\r
+  \r
+  // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
+  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
+\r
+  for (i = 0; i < EB_NUM_GIC_INTERRUPTS; i++) {\r
+    DisableInterruptSource (&gHardwareInterruptProtocol, i);\r
+    \r
+    // Set Priority \r
+    RegOffset = i / 4;\r
+    RegShift = (i % 4) * 8;\r
+    MmioAndThenOr32 (\r
+      EB_GIC1_DIST_BASE+GIC_ICDIPR+(4*RegOffset), \r
+      ~(0xff << RegShift), \r
+      GIC_DEFAULT_PRIORITY << RegShift\r
+      );\r
+  }\r
+\r
+  // configure interrupts for cpu 0\r
+  for (i = 0; i < EB_NUM_GIC_REG_PER_INT_BYTES; i++) {\r
+    MmioWrite32 (EB_GIC1_DIST_BASE + GIC_ICDIPTR + (i*4), 0x01010101);\r
+  }\r
+\r
+  // set binary point reg to 0x7 (no preemption)\r
+  MmioWrite32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCBPR, 0x7);\r
+\r
+  // set priority mask reg to 0xff to allow all priorities through\r
+  MmioWrite32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCPMR, 0xff);\r
+  \r
+  // enable gic cpu interface\r
+  MmioWrite32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCICR, 0x1);\r
+\r
+  // enable gic distributor\r
+  MmioWrite32 (EB_GIC1_DIST_BASE + GIC_ICCICR, 0x1);\r
+\r
+  \r
+  ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));\r
+  \r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                  &gHardwareInterruptHandle,\r
+                  &gHardwareInterruptProtocolGuid,   &gHardwareInterruptProtocol,\r
+                  NULL\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+  \r
+  // Set up to be notified when the Cpu protocol is installed.\r
+  Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK, CpuProtocolInstalledNotification, NULL, &CpuProtocolNotificationEvent);    \r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = gBS->RegisterProtocolNotify (&gEfiCpuArchProtocolGuid, CpuProtocolNotificationEvent, (VOID *)&CpuProtocolNotificationToken);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  // Register for an ExitBootServicesEvent\r
+  Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf b/ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf
new file mode 100644 (file)
index 0000000..17bfd4f
--- /dev/null
@@ -0,0 +1,53 @@
+#/** @file\r
+#  \r
+#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution.  The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  \r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#  \r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = GicInterruptDxe\r
+  FILE_GUID                      = A7496828-946E-43BF-97D6-AA0272001899\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+\r
+  ENTRY_POINT                    = InterruptDxeInitialize\r
+\r
+\r
+[Sources.common]\r
+  InterruptDxe.c\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  EmbeddedPkg/EmbeddedPkg.dec\r
+  ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  UefiLib\r
+  UefiBootServicesTableLib\r
+  DebugLib\r
+  PrintLib\r
+  UefiDriverEntryPoint\r
+  IoLib\r
+\r
+[Guids]\r
+  \r
+\r
+[Protocols]\r
+  gHardwareInterruptProtocolGuid\r
+  gEfiCpuArchProtocolGuid\r
+  \r
+[FixedPcd.common]\r
+  gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress\r
+\r
+[depex]\r
+  TRUE\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEb.c b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEb.c
new file mode 100644 (file)
index 0000000..2bbca87
--- /dev/null
@@ -0,0 +1,68 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  
+*  This program and the accompanying materials                          
+*  are licensed and made available under the terms and conditions of the BSD License         
+*  which accompanies this distribution.  The full text of the license may be found at        
+*  http://opensource.org/licenses/bsd-license.php                                            
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Drivers/PL341Dmc.h>
+
+/**
+  Return if Trustzone is supported by your platform
+
+  A non-zero value must be returned if you want to support a Secure World on your platform.
+  ArmPlatformTrustzoneInit() will later set up the secure regions.
+  This function can return 0 even if Trustzone is supported by your processor. In this case,
+  the platform will continue to run in Secure World.
+
+  @return   A non-zero value if Trustzone supported.
+
+**/
+UINTN ArmPlatformTrustzoneSupported(VOID) {
+  // There is no Trustzone controllers (TZPC & TZASC) and no Secure Memory on RTSM
+       return FALSE;
+}
+
+/**
+  Initialize the Secure peripherals and memory regions
+
+  If Trustzone is supported by your platform then this function makes the required initialization
+  of the secure peripherals and memory regions.
+
+**/
+VOID ArmPlatformTrustzoneInit(VOID) {
+       ASSERT(FALSE);
+}
+
+/**
+  Remap the memory at 0x0
+
+  Some platform requires or gives the ability to remap the memory at the address 0x0.
+  This function can do nothing if this feature is not relevant to your platform.
+
+**/
+VOID ArmPlatformBootRemapping(VOID) {
+  // Disable memory remapping and return to normal mapping
+       MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID ArmPlatformInitializeSystemMemory(VOID) {
+    // We do not need to initialize the System Memory on RTSM
+}
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.S b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.S
new file mode 100644 (file)
index 0000000..79675ae
--- /dev/null
@@ -0,0 +1,62 @@
+//\r
+//  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//  \r
+//  This program and the accompanying materials                          \r
+//  are licensed and made available under the terms and conditions of the BSD License         \r
+//  which accompanies this distribution.  The full text of the license may be found at        \r
+//  http://opensource.org/licenses/bsd-license.php                                            \r
+//\r
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+#Start of Code section\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)\r
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)\r
+\r
+/**
+  Called at the early stage of the Boot phase to know if the memory has already been initialized
+
+  Running the code from the reset vector does not mean we start from cold boot. In some case, we
+  can go through this code with the memory already initialized.
+  Because this function is called at the early stage, the implementation must not use the stack.
+  Its implementation must probably done in assembly to ensure this requirement.
+
+  @return   Return the condition value into the 'Z' flag
+
+**/
+ASM_PFX(ArmPlatformIsMemoryInitialized):\r
+  // Check if the memory has been already mapped, if so skipped the memory initialization
+  LoadConstantToReg (ARM_EB_SYSCTRL, r0)
+  ldr   r0, [r0, #0]
+  
+  // 0x200 (BIT9): This read-only bit returns the remap status.
+  and   r0, r0, #0x200
+  tst   r0, #0x200
+  bx   lr\r
+    \r
+/**
+  Initialize the memory where the initial stacks will reside
+
+  This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+  In some platform, this region is already initialized and the implementation of this function can
+  do nothing. This memory can also represent the Secure RAM.
+  This function is called before the satck has been set up. Its implementation must ensure the stack
+  pointer is not used (probably required to use assembly language)
+
+**/
+ASM_PFX(ArmPlatformInitializeBootMemory):\r
+  // The SMC does not need to be initialized for RTSM\r
+  bx    lr\r
+\r
+.end\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.asm b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.asm
new file mode 100644 (file)
index 0000000..c0b4263
--- /dev/null
@@ -0,0 +1,63 @@
+//\r
+//  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//  \r
+//  This program and the accompanying materials                          \r
+//  are licensed and made available under the terms and conditions of the BSD License         \r
+//  which accompanies this distribution.  The full text of the license may be found at        \r
+//  http://opensource.org/licenses/bsd-license.php                                            \r
+//\r
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+  INCLUDE AsmMacroIoLib.inc\r
+  \r
+  EXPORT  ArmPlatformIsMemoryInitialized\r
+  EXPORT  ArmPlatformInitializeBootMemory\r
+  \r
+  PRESERVE8\r
+  AREA    ArmRealViewEbHelper, CODE, READONLY\r
+\r
+/**\r
+  Called at the early stage of the Boot phase to know if the memory has already been initialized\r
+\r
+  Running the code from the reset vector does not mean we start from cold boot. In some case, we\r
+  can go through this code with the memory already initialized.\r
+  Because this function is called at the early stage, the implementation must not use the stack.\r
+  Its implementation must probably done in assembly to ensure this requirement.\r
+\r
+  @return   Return the condition value into the 'Z' flag\r
+\r
+**/\r
+ArmPlatformIsMemoryInitialized\r
+  // Check if the memory has been already mapped, if so skipped the memory initialization\r
+  LoadConstantToReg (ARM_EB_SYSCTRL, r0)\r
+  ldr   r0, [r0, #0]\r
+  \r
+  // 0x200 (BIT9): This read-only bit returns the remap status.\r
+  and   r0, r0, #0x200\r
+  tst   r0, #0x200\r
+  bx   lr\r
+    \r
+/**\r
+  Initialize the memory where the initial stacks will reside\r
+\r
+  This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+  In some platform, this region is already initialized and the implementation of this function can\r
+  do nothing. This memory can also represent the Secure RAM.\r
+  This function is called before the satck has been set up. Its implementation must ensure the stack\r
+  pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ArmPlatformInitializeBootMemory\r
+  // The SMC does not need to be initialized for RTSM\r
+  bx    lr\r
+  \r
+  END\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
new file mode 100644 (file)
index 0000000..37a21d8
--- /dev/null
@@ -0,0 +1,46 @@
+#/* @file
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmRealViewEbLib
+  FILE_GUID                      = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  MemoryAllocationLib
+
+[Sources.common]
+  ArmRealViewEb.c
+  ArmRealViewEbMem.c
+
+[Protocols]
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdStandalone
+
+[FixedPcd]
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c
new file mode 100644 (file)
index 0000000..759de3a
--- /dev/null
@@ -0,0 +1,202 @@
+/** @file\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  \r
+*  This program and the accompanying materials                          \r
+*  are licensed and made available under the terms and conditions of the BSD License         \r
+*  which accompanies this distribution.  The full text of the license may be found at        \r
+*  http://opensource.org/licenses/bsd-license.php                                            \r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*\r
+**/\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+#define DDR_ATTRIBUTES_SECURE_CACHED    ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_SECURE_UNCACHED  ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED\r
+\r
+/**\r
+  Return the information about the memory region in permanent memory used by PEI\r
+\r
+  One of the PEI Module must install the permament memory used by PEI. This function returns the\r
+  information about this region for your platform to this PEIM module.\r
+\r
+  @param[out]   PeiMemoryBase       Base of the memory region used by PEI core and modules\r
+  @param[out]   PeiMemorySize       Size of the memory region used by PEI core and modules\r
+\r
+**/\r
+VOID ArmPlatformGetPeiMemory (\r
+    OUT UINTN*                                   PeiMemoryBase,\r
+    OUT UINTN*                                   PeiMemorySize\r
+    ) {\r
+    ASSERT((PeiMemoryBase != NULL) && (PeiMemorySize != NULL));\r
+    \r
+    *PeiMemoryBase = ARM_EB_DRAM_BASE + ARM_EB_EFI_FIX_ADDRESS_REGION_SZ;\r
+    *PeiMemorySize = ARM_EB_EFI_MEMORY_REGION_SZ;\r
+}\r
+\r
+/**\r
+  Return the Virtual Memory Map of your platform\r
+\r
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
+\r
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
+                                    Virtual Memory mapping. This array must be ended by a zero-filled\r
+                                    entry\r
+\r
+**/\r
+VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {\r
+    UINT32                        val32;\r
+    UINT32                        CacheAttributes;\r
+    BOOLEAN                       bTrustzoneSupport = FALSE;\r
+    UINTN                         Index = 0;\r
+    ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;\r
+\r
+    ASSERT(VirtualMemoryMap != NULL);\r
+\r
+    VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9);\r
+    if (VirtualMemoryTable == NULL) {\r
+        return;\r
+    }\r
+\r
+    if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+        CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);\r
+    } else {\r
+        CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);\r
+    }\r
+\r
+    // ReMap (Either NOR Flash or DRAM)\r
+    VirtualMemoryTable[Index].PhysicalBase = ARM_EB_REMAP_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_EB_REMAP_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_EB_REMAP_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+    // DDR\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_DRAM_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_EB_DRAM_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_EB_DRAM_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+    // SMC CS7\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+    // SMB CS0-CS1 - NOR Flash 1 & 2\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_NOR_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_EB_SMB_NOR_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_EB_SMB_NOR_SZ + ARM_EB_SMB_DOC_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+    // SMB CS2 - SRAM\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_SRAM_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_EB_SMB_SRAM_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_EB_SMB_SRAM_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+    // SMB CS3-CS6 - Motherboard Peripherals\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_PERIPH_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_EB_SMB_PERIPH_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_EB_SMB_PERIPH_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+    // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
+    if (MmioRead32(ARM_EB_SYS_PROCID1_REG) != 0) {\r
+        VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_LOGIC_TILE_BASE;\r
+        VirtualMemoryTable[Index].VirtualBase  = ARM_EB_LOGIC_TILE_BASE;\r
+        VirtualMemoryTable[Index].Length       = ARM_EB_LOGIC_TILE_SZ;\r
+        VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+    }\r
+\r
+    // End of Table\r
+    VirtualMemoryTable[++Index].PhysicalBase = 0;\r
+    VirtualMemoryTable[Index].VirtualBase  = 0;\r
+    VirtualMemoryTable[Index].Length       = 0;\r
+    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
+    *VirtualMemoryMap = VirtualMemoryTable;\r
+}\r
+\r
+/**\r
+  Return the EFI Memory Map of your platform\r
+\r
+  This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource\r
+  Descriptor HOBs used by DXE core.\r
+\r
+  @param[out]   EfiMemoryMap        Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an\r
+                                    EFI Memory region. This array must be ended by a zero-filled entry\r
+\r
+**/\r
+VOID ArmPlatformGetEfiMemoryMap (\r
+    OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
+) {\r
+    EFI_RESOURCE_ATTRIBUTE_TYPE     Attributes;\r
+    UINT64                          MemoryBase;\r
+    UINTN                           Index = 0;\r
+    ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR  *EfiMemoryTable;\r
+\r
+    ASSERT(EfiMemoryMap != NULL);\r
+\r
+    EfiMemoryTable = (ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR) * 6);\r
+\r
+    Attributes =\r
+    (\r
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_TESTED\r
+    );\r
+    MemoryBase = ARM_EB_DRAM_BASE;\r
+  \r
+    // Memory Reserved for fixed address allocations (such as Exception Vector Table)\r
+    EfiMemoryTable[Index].ResourceAttribute = Attributes;\r
+    EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+    EfiMemoryTable[Index].NumberOfBytes = ARM_EB_EFI_FIX_ADDRESS_REGION_SZ;\r
+    \r
+    MemoryBase += ARM_EB_EFI_FIX_ADDRESS_REGION_SZ;\r
+\r
+    // Memory declared to PEI as permanent memory for PEI and DXE\r
+    EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
+    EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+    EfiMemoryTable[Index].NumberOfBytes = ARM_EB_EFI_MEMORY_REGION_SZ;\r
+\r
+    MemoryBase += ARM_EB_EFI_MEMORY_REGION_SZ;\r
+\r
+    // We must reserve the memory used by the Firmware Volume copied in DRAM at 0x80000000\r
+    if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
+        // Chunk between the EFI Memory region and the firmware\r
+        EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
+        EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+        EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdBaseAddress) - MemoryBase;\r
+\r
+        // Chunk reserved by the firmware in DRAM\r
+        EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_PRESENT);\r
+        EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdEmbeddedFdBaseAddress);\r
+        EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdSize);\r
+\r
+        MemoryBase = PcdGet32(PcdEmbeddedFdBaseAddress) + PcdGet32(PcdEmbeddedFdSize);\r
+    }\r
+      \r
+    // We allocate all the remain memory as untested system memory\r
+    EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_TESTED);\r
+    EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+    EfiMemoryTable[Index].NumberOfBytes = ARM_EB_DRAM_SZ - (MemoryBase-ARM_EB_DRAM_BASE);\r
+\r
+    EfiMemoryTable[++Index].ResourceAttribute = 0;\r
+    EfiMemoryTable[Index].PhysicalStart = 0;\r
+    EfiMemoryTable[Index].NumberOfBytes = 0;\r
+\r
+    *EfiMemoryMap = EfiMemoryTable;\r
+}\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf
new file mode 100644 (file)
index 0000000..dbfc37b
--- /dev/null
@@ -0,0 +1,46 @@
+#/* @file\r
+#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+#  \r
+#  This program and the accompanying materials                          \r
+#  are licensed and made available under the terms and conditions of the BSD License         \r
+#  which accompanies this distribution.  The full text of the license may be found at        \r
+#  http://opensource.org/licenses/bsd-license.php                                            \r
+#\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+#\r
+#*/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ArmRealViewEbLib\r
+  FILE_GUID                      = 6e02ebe0-1d96-11e0-b9cb-0002a5d5c51b\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmPlatformLib\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  EmbeddedPkg/EmbeddedPkg.dec\r
+  ArmPkg/ArmPkg.dec\r
+  ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  IoLib\r
+  ArmLib\r
+\r
+[Sources.common]\r
+  ArmRealViewEb.c\r
+  ArmRealViewEbHelper.asm   | RVCT\r
+  ArmRealViewEbHelper.S     | GCC\r
+\r
+[Protocols]\r
+\r
+[FeaturePcd]\r
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+  gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
+[FixedPcd]\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c b/ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c
new file mode 100644 (file)
index 0000000..e623842
--- /dev/null
@@ -0,0 +1,80 @@
+/** @file\r
+  Template for ArmEb DebugAgentLib. \r
+\r
+  For ARM we reserve FIQ for the Debug Agent Timer. We don't care about \r
+  laytency as we only really need the timer to run a few times a second \r
+  (how fast can some one type a ctrl-c?), but it works much better if\r
+  the interrupt we are using to break into the debugger is not being\r
+  used, and masked, by the system. \r
+\r
+  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+  \r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+\r
+#include <Library/DebugAgentTimerLib.h>\r
+\r
+#include <ArmEb/ArmEb.h>\r
+\r
+\r
+/**\r
+  Setup all the hardware needed for the debug agents timer.\r
+\r
+  This function is used to set up debug enviroment. \r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DebugAgentTimerIntialize (\r
+  VOID\r
+  )\r
+{\r
+  // Map Timer to FIQ\r
+}\r
+  \r
+  \r
+/**\r
+  Set the period for the debug agent timer. Zero means disable the timer.\r
+\r
+  @param[in] TimerPeriodMilliseconds    Frequency of the debug agent timer.\r
+\r
+**/  \r
+VOID\r
+EFIAPI\r
+DebugAgentTimerSetPeriod (\r
+  IN  UINT32  TimerPeriodMilliseconds\r
+  )\r
+{\r
+  if (TimerPeriodMilliseconds == 0) {\r
+    // Disable timer and Disable FIQ\r
+    return;\r
+  } \r
+\r
+  // Set timer period and unmask FIQ\r
+}\r
+  \r
+\r
+/**\r
+  Perform End Of Interrupt for the debug agent timer. This is called in the \r
+  interrupt handler after the interrupt has been processed. \r
+\r
+**/  \r
+VOID\r
+EFIAPI\r
+DebugAgentTimerEndOfInterrupt (\r
+  VOID\r
+  )\r
+{\r
+  // EOI Timer interrupt for FIQ\r
+}\r
+  \r
+  
\ No newline at end of file
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
new file mode 100644 (file)
index 0000000..38642fd
--- /dev/null
@@ -0,0 +1,38 @@
+#/** @file\r
+# Component description file for Base PCI Cf8 Library.\r
+#\r
+# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.\r
+#  Layers on top of an I/O Library instance.\r
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>\r
+#\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ArmEbDebugAgentTimerLib\r
+  FILE_GUID                      = 80949BBB-68EE-4a4c-B434-D5DB5A232F0C\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = DebugAgentTimerLib|SEC BASE DXE_CORE\r
+\r
+\r
+[Sources.common]\r
+  DebugAgentTimerLib.c\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  EmbeddedPkg/EmbeddedPkg.dec\r
+  ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec\r
+\r
+[LibraryClasses]\r
+  IoLib\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.c b/ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.c
new file mode 100644 (file)
index 0000000..1ad0e17
--- /dev/null
@@ -0,0 +1,118 @@
+/** @file
+  Basic serial IO abstaction for GDB
+
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/GdbSerialLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Drivers/PL011Uart.h>
+
+RETURN_STATUS
+EFIAPI
+GdbSerialLibConstructor (
+  VOID
+  )
+{
+  return GdbSerialInit (115200, 0, 8, 1);
+}
+
+RETURN_STATUS
+EFIAPI
+GdbSerialInit (
+  IN UINT64     BaudRate, 
+  IN UINT8      Parity, 
+  IN UINT8      DataBits, 
+  IN UINT8      StopBits 
+  )
+{
+  if ((Parity != 0) || (DataBits != 8) || (StopBits != 1)) {
+    return RETURN_UNSUPPORTED;
+  }
+
+  if (BaudRate != 115200) {
+    // Could add support for different Baud rates....
+    return RETURN_UNSUPPORTED;
+  }
+      
+  UINT32  Base = PcdGet32 (PcdGdbUartBase);\r
+  \r
+  // initialize baud rate generator to 115200 based on EB clock REFCLK24MHZ\r
+  MmioWrite32 (Base + UARTIBRD, UART_115200_IDIV);\r
+  MmioWrite32 (Base + UARTFBRD, UART_115200_FDIV);\r
+\r
+  // no parity, 1 stop, no fifo, 8 data bits\r
+  MmioWrite32 (Base + UARTLCR_H, 0x60);\r
+\r
+  // clear any pending errors\r
+  MmioWrite32 (Base + UARTECR, 0);\r
+\r
+  // enable tx, rx, and uart overall\r
+  MmioWrite32 (Base + UARTCR, 0x301);\r
+\r
+  return RETURN_SUCCESS;\r
+}
+
+BOOLEAN
+EFIAPI
+GdbIsCharAvailable (
+  VOID
+  )  
+{
+  UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;\r
+\r
+  if ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0) {\r
+    return TRUE;\r
+  } else {\r
+    return FALSE;\r
+  }\r
+}
+
+CHAR8
+EFIAPI
+GdbGetChar (
+  VOID
+  )
+{
+  UINT32  FR = PcdGet32 (PcdGdbUartBase) + UARTFR;\r
+  UINT32  DR = PcdGet32 (PcdGdbUartBase) + UARTDR;\r
+    \r
+  while ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0);\r
+  return MmioRead8 (DR);\r
+}
+
+VOID
+EFIAPI
+GdbPutChar (
+  IN  CHAR8   Char
+  )
+{
+  UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;\r
+  UINT32 DR = PcdGet32 (PcdGdbUartBase) + UARTDR;\r
+\r
+  while ((MmioRead32 (FR) & UART_TX_EMPTY_FLAG_MASK) != 0);\r
+  MmioWrite8 (DR, Char);\r
+  return;
+}
+
+VOID
+GdbPutString (
+  IN CHAR8  *String
+  )
+{
+  while (*String != '\0') {
+    GdbPutChar (*String);
+    String++;
+  }
+}
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.inf
new file mode 100644 (file)
index 0000000..3a609c7
--- /dev/null
@@ -0,0 +1,40 @@
+#/** @file
+#  
+#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#  
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = GdbSerialLib
+  FILE_GUID                      = E8EA1309-2F14-428f-ABE3-7016CE4B4305
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = GdbSerialLib
+
+  CONSTRUCTOR                    = GdbSerialLibConstructor
+
+
+[Sources.common]
+  GdbSerialLib.c
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec
+
+[LibraryClasses]
+  DebugLib
+  IoLib   
+
+[FixedPcd]
+
+  gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase
\ No newline at end of file
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.c b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.c
new file mode 100644 (file)
index 0000000..0c11956
--- /dev/null
@@ -0,0 +1,87 @@
+/** @file\r
+  Template library implementation to support ResetSystem Runtime call.\r
+  \r
+  Fill in the templates with what ever makes you system reset.\r
+\r
+\r
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+  \r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/EfiResetSystemLib.h>\r
+#include <Drivers/PL011Uart.h>\r
+\r
+/**\r
+  Resets the entire platform.\r
+\r
+  @param  ResetType             The type of reset to perform.\r
+  @param  ResetStatus           The status code for the reset.\r
+  @param  DataSize              The size, in bytes, of WatchdogData.\r
+  @param  ResetData             For a ResetType of EfiResetCold, EfiResetWarm, or\r
+                                EfiResetShutdown the data buffer starts with a Null-terminated\r
+                                Unicode string, optionally followed by additional binary data.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibResetSystem (\r
+  IN EFI_RESET_TYPE   ResetType,\r
+  IN EFI_STATUS       ResetStatus,\r
+  IN UINTN            DataSize,\r
+  IN CHAR16           *ResetData OPTIONAL\r
+  )\r
+{\r
+  if (ResetData != NULL) {\r
+    DEBUG ((EFI_D_ERROR, "%s", ResetData));\r
+  }\r
+\r
+  switch (ResetType) {\r
+  case EfiResetWarm:\r
+    // Map a warm reset into a cold reset\r
+  case EfiResetCold:\r
+  case EfiResetShutdown:\r
+  default:\r
+    CpuDeadLoop ();\r
+    break;\r
+  }\r
+\r
+  // If the reset didn't work, return an error.\r
+  ASSERT (FALSE);\r
+  return EFI_DEVICE_ERROR;\r
+}\r
+  \r
+\r
+\r
+/**\r
+  Initialize any infrastructure required for LibResetSystem () to function.\r
+\r
+  @param  ImageHandle   The firmware allocated handle for the EFI image.\r
+  @param  SystemTable   A pointer to the EFI System Table.\r
+  \r
+  @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibInitializeResetSystem (\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+  return EFI_SUCCESS;\r
+}\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.inf
new file mode 100644 (file)
index 0000000..18a1203
--- /dev/null
@@ -0,0 +1,35 @@
+#/** @file\r
+# Reset System lib to make it easy to port new platforms\r
+#\r
+# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>\r
+#\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ArmEbResetSystemLib\r
+  FILE_GUID                      = CEFFA65C-B568-453e-9E11-B81AE683D035\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = EfiResetSystemLib\r
+\r
+\r
+[Sources.common]\r
+  ResetSystemLib.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  EmbeddedPkg/EmbeddedPkg.dec\r
+  ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  DebugLib\r
+  BaseLib\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Arm/ModuleEntryPoint.S b/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Arm/ModuleEntryPoint.S
new file mode 100644 (file)
index 0000000..2b5ee8f
--- /dev/null
@@ -0,0 +1,68 @@
+#------------------------------------------------------------------------------ \r
+#\r
+# ARM EB Entry point. Reset vector in FV header will brach to\r
+# _ModuleEntryPoint. \r
+#\r
+# We use crazy macros, like LoadConstantToReg, since Xcode assembler \r
+# does not support = assembly syntax for ldr.\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmEb/ArmEb.h>\r
+\r
+.text\r
+.align 3\r
+\r
+.globl ASM_PFX(CEntryPoint)\r
+.globl ASM_PFX(_ModuleEntryPoint)\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
\r
+  // Turn off remapping NOR to 0. We can now use DRAM in low memory\r
+  // CAN'T DO THIS HERE -- BRANCH FROM RESET VECTOR IS RELATIVE AND REMAINS IN REMAPPED NOR\r
+  //MmioOr32 (EB_SP810_CTRL_BASE ,BIT8) \r
+\r
+  // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+  mrc     p15, 0, r0, c1, c0, 2\r
+  orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)\r
+  mcr     p15, 0, r0, c1, c0, 2\r
+  mov     r0, #0x40000000       // Set EN bit in FPEXC\r
+  mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly\r
+   \r
+  // Set CPU vectors to 0 (which is currently flash)\r
+  LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r
+  mcr     p15, 0, r0, c12, c0, 0\r
+  isb                               // Sync changes to control registers\r
+\r
+  //\r
+  // Set stack based on PCD values. Need to do it this way to make C code work \r
+  // when it runs from FLASH. \r
+  //  \r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2)    // stack base arg2  \r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3)    // stack size arg3  \r
+  add     r4, r2, r3\r
+  mov     r13, r4\r
+\r
+  // Call C entry point\r
+  LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1)    // memory size arg1      \r
+  LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0)    // memory size arg0       \r
+  blx      ASM_PFX(CEntryPoint) \r
+\r
+ShouldNeverGetHere:\r
+  // _CEntryPoint should never return \r
+  b       ShouldNeverGetHere\r
+\r
\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Arm/ModuleEntryPoint.asm b/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Arm/ModuleEntryPoint.asm
new file mode 100644 (file)
index 0000000..aa0b98f
--- /dev/null
@@ -0,0 +1,80 @@
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution.  The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmEb/ArmEb.h>\r
+#include <AutoGen.h>\r
+\r
+  INCLUDE AsmMacroIoLib.inc\r
+  \r
+  IMPORT  CEntryPoint\r
+  EXPORT  _ModuleEntryPoint\r
+        \r
+  PRESERVE8\r
+  AREA    ModuleEntryPoint, CODE, READONLY\r
+  \r
+\r
+StartupAddr        DCD      CEntryPoint\r
+\r
+_ModuleEntryPoint\r
\r
+  // Turn off remapping NOR to 0. We can now use DRAM in low memory\r
+  // CAN'T DO THIS HERE -- BRANCH FROM RESET VECTOR IS RELATIVE AND REMAINS IN REMAPPED NOR\r
+  //MmioOr32 (0x10001000 ,BIT8) //EB_SP810_CTRL_BASE\r
+\r
+  // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+  mrc     p15, 0, r0, c1, c0, 2\r
+  orr     r0, r0, #0x00f00000   // Enable VFP access (V* instructions)\r
+  mcr     p15, 0, r0, c1, c0, 2\r
+  mov     r0, #0x40000000       // Set EN bit in FPEXC\r
+  mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly\r
+   \r
+  // Set CPU vectors to 0 (which is currently flash)\r
+  LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r
+  mcr     p15, 0, r0, c12, c0, 0\r
+  isb                               // Sync changes to control registers\r
+\r
+  //\r
+  // Set stack based on PCD values. Need to do it this way to make C code work \r
+  // when it runs from FLASH. \r
+  //  \r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2)    // stack base arg2  \r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3)    // stack size arg3  \r
+  add     r4, r2, r3\r
+  mov     r13, r4\r
+  \r
+  LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1)    // memory size arg1      \r
+  LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0)    // memory size arg0 \r
+\r
+  // move sec startup address into a data register\r
+  // ensure we're jumping to FV version of the code (not boot remapped alias)\r
+  ldr   r4, StartupAddr\r
+\r
+  // jump to SEC C code\r
+  blx   r4\r
+  \r
+  // Call C entry point\r
+  // THIS DOESN'T WORK, WE NEED A LONG JUMP\r
+      \r
+  // blx     CEntryPoint \r
+\r
+ShouldNeverGetHere\r
+  // _CEntryPoint should never return \r
+  b       ShouldNeverGetHere\r
+  \r
+  END\r
+\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Cache.c b/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Cache.c
new file mode 100644 (file)
index 0000000..a0e3abb
--- /dev/null
@@ -0,0 +1,79 @@
+/** @file\r
+\r
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+  \r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/PrePiLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+\r
+// SoC registers. L3 interconnects\r
+#define SOC_REGISTERS_L3_PHYSICAL_BASE       0x68000000\r
+#define SOC_REGISTERS_L3_PHYSICAL_LENGTH     0x08000000\r
+#define SOC_REGISTERS_L3_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
+\r
+// SoC registers. L4 interconnects\r
+#define SOC_REGISTERS_L4_PHYSICAL_BASE       0x48000000\r
+#define SOC_REGISTERS_L4_PHYSICAL_LENGTH     0x08000000\r
+#define SOC_REGISTERS_L4_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
+\r
+VOID\r
+InitCache (\r
+  IN  UINT32  MemoryBase,\r
+  IN  UINT32  MemoryLength\r
+  )\r
+{\r
+  UINT32                        CacheAttributes;\r
+  ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[5];\r
+  VOID                          *TranslationTableBase;\r
+  UINTN                         TranslationTableSize;\r
+\r
+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+    CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
+  } else {\r
+    CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
+  }\r
+\r
+  // DDR\r
+  MemoryTable[0].PhysicalBase = MemoryBase;\r
+  MemoryTable[0].VirtualBase  = MemoryBase;\r
+  MemoryTable[0].Length       = MemoryLength;\r
+  MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+  // SOC Registers. L3 interconnects\r
+  MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
+  MemoryTable[1].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;\r
+  \r
+  // SOC Registers. L4 interconnects\r
+  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
+  MemoryTable[2].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;\r
+\r
+  // End of Table\r
+  MemoryTable[3].PhysicalBase = 0;\r
+  MemoryTable[3].VirtualBase  = 0;\r
+  MemoryTable[3].Length       = 0;\r
+  MemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+  \r
+  ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
+  \r
+  BuildMemoryAllocationHob ((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r
+}\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Pei/LzmaDecompress.h b/ArmPlatformPkg/ArmRealViewEbPkg/Pei/LzmaDecompress.h
new file mode 100644 (file)
index 0000000..e4483b6
--- /dev/null
@@ -0,0 +1,103 @@
+/** @file\r
+  LZMA Decompress Library header file\r
+\r
+  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __LZMA_DECOMPRESS_H___\r
+#define __LZMA_DECOMPRESS_H___\r
+\r
+/**\r
+  Examines a GUIDed section and returns the size of the decoded buffer and the\r
+  size of an scratch buffer required to actually decode the data in a GUIDed section.\r
+\r
+  Examines a GUIDed section specified by InputSection.  \r
+  If GUID for InputSection does not match the GUID that this handler supports,\r
+  then RETURN_UNSUPPORTED is returned.  \r
+  If the required information can not be retrieved from InputSection,\r
+  then RETURN_INVALID_PARAMETER is returned.\r
+  If the GUID of InputSection does match the GUID that this handler supports,\r
+  then the size required to hold the decoded buffer is returned in OututBufferSize,\r
+  the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field\r
+  from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute.\r
+  \r
+  If InputSection is NULL, then ASSERT().\r
+  If OutputBufferSize is NULL, then ASSERT().\r
+  If ScratchBufferSize is NULL, then ASSERT().\r
+  If SectionAttribute is NULL, then ASSERT().\r
+\r
+\r
+  @param[in]  InputSection       A pointer to a GUIDed section of an FFS formatted file.\r
+  @param[out] OutputBufferSize   A pointer to the size, in bytes, of an output buffer required\r
+                                 if the buffer specified by InputSection were decoded.\r
+  @param[out] ScratchBufferSize  A pointer to the size, in bytes, required as scratch space\r
+                                 if the buffer specified by InputSection were decoded.\r
+  @param[out] SectionAttribute   A pointer to the attributes of the GUIDed section. See the Attributes\r
+                                 field of EFI_GUID_DEFINED_SECTION in the PI Specification.\r
+\r
+  @retval  RETURN_SUCCESS            The information about InputSection was returned.\r
+  @retval  RETURN_UNSUPPORTED        The section specified by InputSection does not match the GUID this handler supports.\r
+  @retval  RETURN_INVALID_PARAMETER  The information can not be retrieved from the section specified by InputSection.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+LzmaGuidedSectionGetInfo (\r
+  IN  CONST VOID  *InputSection,\r
+  OUT UINT32      *OutputBufferSize,\r
+  OUT UINT32      *ScratchBufferSize,\r
+  OUT UINT16      *SectionAttribute\r
+  );\r
+\r
+/**\r
+  Decompress a LZAM compressed GUIDed section into a caller allocated output buffer.\r
+  \r
+  Decodes the GUIDed section specified by InputSection.  \r
+  If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned.  \r
+  If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned.\r
+  If the GUID of InputSection does match the GUID that this handler supports, then InputSection\r
+  is decoded into the buffer specified by OutputBuffer and the authentication status of this\r
+  decode operation is returned in AuthenticationStatus.  If the decoded buffer is identical to the\r
+  data in InputSection, then OutputBuffer is set to point at the data in InputSection.  Otherwise,\r
+  the decoded data will be placed in caller allocated buffer specified by OutputBuffer.\r
+  \r
+  If InputSection is NULL, then ASSERT().\r
+  If OutputBuffer is NULL, then ASSERT().\r
+  If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().\r
+  If AuthenticationStatus is NULL, then ASSERT().\r
+\r
+\r
+  @param[in]  InputSection  A pointer to a GUIDed section of an FFS formatted file.\r
+  @param[out] OutputBuffer  A pointer to a buffer that contains the result of a decode operation. \r
+  @param[out] ScratchBuffer A caller allocated buffer that may be required by this function\r
+                            as a scratch buffer to perform the decode operation. \r
+  @param[out] AuthenticationStatus \r
+                            A pointer to the authentication status of the decoded output buffer.\r
+                            See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI\r
+                            section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must\r
+                            never be set by this handler.\r
+\r
+  @retval  RETURN_SUCCESS            The buffer specified by InputSection was decoded.\r
+  @retval  RETURN_UNSUPPORTED        The section specified by InputSection does not match the GUID this handler supports.\r
+  @retval  RETURN_INVALID_PARAMETER  The section specified by InputSection can not be decoded.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+LzmaGuidedSectionExtraction (\r
+  IN CONST  VOID    *InputSection,\r
+  OUT       VOID    **OutputBuffer,\r
+  OUT       VOID    *ScratchBuffer,        OPTIONAL\r
+  OUT       UINT32  *AuthenticationStatus\r
+  );\r
+  \r
+#endif // __LZMADECOMPRESS_H__\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Pei/ModuleEntryPoint.S b/ArmPlatformPkg/ArmRealViewEbPkg/Pei/ModuleEntryPoint.S
new file mode 100644 (file)
index 0000000..2b5ee8f
--- /dev/null
@@ -0,0 +1,68 @@
+#------------------------------------------------------------------------------ \r
+#\r
+# ARM EB Entry point. Reset vector in FV header will brach to\r
+# _ModuleEntryPoint. \r
+#\r
+# We use crazy macros, like LoadConstantToReg, since Xcode assembler \r
+# does not support = assembly syntax for ldr.\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmEb/ArmEb.h>\r
+\r
+.text\r
+.align 3\r
+\r
+.globl ASM_PFX(CEntryPoint)\r
+.globl ASM_PFX(_ModuleEntryPoint)\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
\r
+  // Turn off remapping NOR to 0. We can now use DRAM in low memory\r
+  // CAN'T DO THIS HERE -- BRANCH FROM RESET VECTOR IS RELATIVE AND REMAINS IN REMAPPED NOR\r
+  //MmioOr32 (EB_SP810_CTRL_BASE ,BIT8) \r
+\r
+  // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+  mrc     p15, 0, r0, c1, c0, 2\r
+  orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)\r
+  mcr     p15, 0, r0, c1, c0, 2\r
+  mov     r0, #0x40000000       // Set EN bit in FPEXC\r
+  mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly\r
+   \r
+  // Set CPU vectors to 0 (which is currently flash)\r
+  LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r
+  mcr     p15, 0, r0, c12, c0, 0\r
+  isb                               // Sync changes to control registers\r
+\r
+  //\r
+  // Set stack based on PCD values. Need to do it this way to make C code work \r
+  // when it runs from FLASH. \r
+  //  \r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2)    // stack base arg2  \r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3)    // stack size arg3  \r
+  add     r4, r2, r3\r
+  mov     r13, r4\r
+\r
+  // Call C entry point\r
+  LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1)    // memory size arg1      \r
+  LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0)    // memory size arg0       \r
+  blx      ASM_PFX(CEntryPoint) \r
+\r
+ShouldNeverGetHere:\r
+  // _CEntryPoint should never return \r
+  b       ShouldNeverGetHere\r
+\r
\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Pei/ModuleEntryPoint.asm b/ArmPlatformPkg/ArmRealViewEbPkg/Pei/ModuleEntryPoint.asm
new file mode 100644 (file)
index 0000000..aa0b98f
--- /dev/null
@@ -0,0 +1,80 @@
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution.  The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmEb/ArmEb.h>\r
+#include <AutoGen.h>\r
+\r
+  INCLUDE AsmMacroIoLib.inc\r
+  \r
+  IMPORT  CEntryPoint\r
+  EXPORT  _ModuleEntryPoint\r
+        \r
+  PRESERVE8\r
+  AREA    ModuleEntryPoint, CODE, READONLY\r
+  \r
+\r
+StartupAddr        DCD      CEntryPoint\r
+\r
+_ModuleEntryPoint\r
\r
+  // Turn off remapping NOR to 0. We can now use DRAM in low memory\r
+  // CAN'T DO THIS HERE -- BRANCH FROM RESET VECTOR IS RELATIVE AND REMAINS IN REMAPPED NOR\r
+  //MmioOr32 (0x10001000 ,BIT8) //EB_SP810_CTRL_BASE\r
+\r
+  // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+  mrc     p15, 0, r0, c1, c0, 2\r
+  orr     r0, r0, #0x00f00000   // Enable VFP access (V* instructions)\r
+  mcr     p15, 0, r0, c1, c0, 2\r
+  mov     r0, #0x40000000       // Set EN bit in FPEXC\r
+  mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly\r
+   \r
+  // Set CPU vectors to 0 (which is currently flash)\r
+  LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r
+  mcr     p15, 0, r0, c12, c0, 0\r
+  isb                               // Sync changes to control registers\r
+\r
+  //\r
+  // Set stack based on PCD values. Need to do it this way to make C code work \r
+  // when it runs from FLASH. \r
+  //  \r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2)    // stack base arg2  \r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3)    // stack size arg3  \r
+  add     r4, r2, r3\r
+  mov     r13, r4\r
+  \r
+  LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1)    // memory size arg1      \r
+  LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0)    // memory size arg0 \r
+\r
+  // move sec startup address into a data register\r
+  // ensure we're jumping to FV version of the code (not boot remapped alias)\r
+  ldr   r4, StartupAddr\r
+\r
+  // jump to SEC C code\r
+  blx   r4\r
+  \r
+  // Call C entry point\r
+  // THIS DOESN'T WORK, WE NEED A LONG JUMP\r
+      \r
+  // blx     CEntryPoint \r
+\r
+ShouldNeverGetHere\r
+  // _CEntryPoint should never return \r
+  b       ShouldNeverGetHere\r
+  \r
+  END\r
+\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Sec.c b/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Sec.c
new file mode 100644 (file)
index 0000000..cb5eb0a
--- /dev/null
@@ -0,0 +1,164 @@
+/** @file\r
+  C Entry point for the SEC. First C code after the reset vector.\r
+\r
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+  \r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/PrePiLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/DebugAgentLib.h>\r
+\r
+#include <Ppi/GuidedSectionExtraction.h>\r
+#include <Guid/LzmaDecompress.h>\r
+\r
+#include <ArmEb/ArmEb.h>\r
+\r
+#include "LzmaDecompress.h"\r
+\r
+VOID\r
+EFIAPI \r
+_ModuleEntryPoint(\r
+  VOID\r
+  );\r
+\r
+CHAR8 *\r
+DeCygwinPathIfNeeded (\r
+  IN  CHAR8   *Name\r
+  );\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+SerialPortInitialize (\r
+  VOID\r
+  );\r
+  \r
+  \r
+VOID\r
+UartInit (\r
+  VOID\r
+  )\r
+{\r
+  // SEC phase needs to run library constructors by hand.\r
+  // This assumes we are linked agains the SerialLib\r
+  // In non SEC modules the init call is in autogenerated code.\r
+  SerialPortInitialize ();\r
+}\r
+\r
+VOID\r
+TimerInit (\r
+  VOID\r
+  )\r
+{\r
+  // configure SP810 to use 1MHz clock and disable\r
+  MmioAndThenOr32 (EB_SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r
+  // Enable\r
+  MmioOr32 (EB_SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER2_EN);\r
+\r
+  // configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled\r
+  MmioOr32 (EB_SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);\r
+\r
+  // preload the timer count register\r
+  MmioWrite32 (EB_SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1);\r
+\r
+  // enable the timer\r
+  MmioOr32 (EB_SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);\r
+}\r
+\r
+\r
+VOID\r
+InitCache (\r
+  IN  UINT32  MemoryBase,\r
+  IN  UINT32  MemoryLength\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ExtractGuidedSectionLibConstructor (\r
+  VOID\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+LzmaDecompressLibConstructor (\r
+  VOID\r
+  );\r
+\r
+\r
+VOID\r
+CEntryPoint (\r
+  IN  VOID  *MemoryBase,\r
+  IN  UINTN MemorySize,\r
+  IN  VOID  *StackBase,\r
+  IN  UINTN StackSize\r
+  )\r
+{\r
+  VOID *HobBase;\r
+\r
+  // HOB list is at bottom of stack area\r
+  // Stack grows from top-to-bottom towards HOB list\r
+  HobBase      = (VOID *)StackBase;\r
+  CreateHobList (MemoryBase, MemorySize, HobBase, StackBase);\r
+\r
+  // Turn off remapping NOR to 0. We can will now see DRAM in low memory\r
+  MmioOr32 (0x10001000 ,BIT8); //EB_SP810_CTRL_BASE\r
+\r
+  // Enable program flow prediction, if supported.\r
+  ArmEnableBranchPrediction ();\r
+\r
+  // Initialize CPU cache\r
+  InitCache ((UINT32)MemoryBase, (UINT32)MemorySize);\r
+\r
+  // Add memory allocation hob for relocated FD\r
+  BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r
+\r
+  // Add the FVs to the hob list\r
+  BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r
+\r
+  // Start talking\r
+  UartInit ();\r
+\r
+  InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);\r
+  SaveAndSetDebugTimerInterrupt (TRUE);\r
+\r
+  DEBUG ((EFI_D_ERROR, "UART Enabled\n"));\r
+\r
+  // Start up a free running timer so that the timer lib will work\r
+  TimerInit ();\r
+\r
+  // SEC phase needs to run library constructors by hand.\r
+  ExtractGuidedSectionLibConstructor ();\r
+  LzmaDecompressLibConstructor ();\r
+\r
+  // Build HOBs to pass up our version of stuff the DXE Core needs to save space\r
+  BuildPeCoffLoaderHob ();\r
+  BuildExtractSectionHob (\r
+    &gLzmaCustomDecompressGuid,\r
+    LzmaGuidedSectionGetInfo,\r
+    LzmaGuidedSectionExtraction\r
+    );\r
+\r
+  // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r
+  DecompressFirstFv ();\r
+\r
+  // Load the DXE Core and transfer control to it\r
+  LoadDxeCoreFromFv (NULL, 0);\r
+  \r
+  // DXE Core should always load and never return\r
+  ASSERT (FALSE);\r
+}\r
+\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Sec.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Pei/Sec.inf
new file mode 100644 (file)
index 0000000..3ee9017
--- /dev/null
@@ -0,0 +1,69 @@
+
+#/** @file
+#  SEC - Reset vector code that jumps to C and loads DXE core
+#  
+#  Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#  
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmEBSec
+  FILE_GUID                      = d959e387-7b91-452c-90e0-a1dbac90ddb8
+  MODULE_TYPE                    = SEC
+  VERSION_STRING                 = 1.0
+
+
+[Sources.ARM]
+  ModuleEntryPoint.S   | GCC
+  ModuleEntryPoint.asm | RVCT
+
+[Sources.ARM]
+  Sec.c
+  Cache.c
+  
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+  ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec
+  
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  ArmLib
+  IoLib
+  ExtractGuidedSectionLib
+  LzmaDecompressLib
+  PeCoffGetEntryPointLib
+  DebugAgentLib
+
+
+[FeaturePcd]  
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
+  gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
+  gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+  gEmbeddedTokenSpaceGuid.PcdPrePiStackSize
+  gEmbeddedTokenSpaceGuid.PcdPrePiStackBase
+  gEmbeddedTokenSpaceGuid.PcdMemoryBase
+  gEmbeddedTokenSpaceGuid.PcdMemorySize
+  
+
+  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
+   
+  
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/b.bat b/ArmPlatformPkg/ArmRealViewEbPkg/b.bat
new file mode 100644 (file)
index 0000000..28aab38
--- /dev/null
@@ -0,0 +1,43 @@
+@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+@REM This program and the accompanying materials\r
+@REM are licensed and made available under the terms and conditions of the BSD License\r
+@REM which accompanies this distribution.  The full text of the license may be found at\r
+@REM http://opensource.org/licenses/bsd-license.php\r
+@REM\r
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+@REM\r
+\r
+@REM Example usage of this script. default is a DEBUG build\r
+@REM b\r
+@REM b clean\r
+@REM b release \r
+@REM b release clean\r
+@REM b -v -y build.log\r
+\r
+ECHO OFF\r
+@REM Setup Build environment. Sets WORKSPACE and puts build in path\r
+CALL ..\edksetup.bat\r
+\r
+@REM Set for tools chain. Currently RVCT31\r
+SET TARGET_TOOLS=RVCT31\r
+SET TARGET=DEBUG\r
+\r
+@if /I "%1"=="RELEASE" (\r
+  @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it \r
+  SET TARGET=RELEASE\r
+  shift /1\r
+)\r
+\r
+SET BUILD_ROOT=%WORKSPACE%\Build\ArmRealViewEb\%TARGET%_%TARGET_TOOLS%\r
+\r
+@REM Build the ARM RealView EB firmware and creat an FD (FLASH Device) Image.\r
+CALL build -p ArmRealViewEbPkg\ArmRealViewEbPkg.dsc -a ARM -t RVCT31 -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8\r
+@if ERRORLEVEL 1 goto Exit\r
+\r
+@if /I "%1"=="CLEAN" goto Clean\r
+\r
+:Exit\r
+EXIT /B\r
+\r
+:Clean\r
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ba.bat b/ArmPlatformPkg/ArmRealViewEbPkg/ba.bat
new file mode 100644 (file)
index 0000000..545da38
--- /dev/null
@@ -0,0 +1,56 @@
+@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+@REM This program and the accompanying materials
+@REM are licensed and made available under the terms and conditions of the BSD License
+@REM which accompanies this distribution.  The full text of the license may be found at
+@REM http://opensource.org/licenses/bsd-license.php
+@REM
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+@REM
+
+@REM Example usage of this script. default is a DEBUG build
+@REM b
+@REM b clean
+@REM b release 
+@REM b release clean
+@REM b -v -y build.log
+
+ECHO OFF
+@REM Setup Build environment. Sets WORKSPACE and puts build in path
+CALL ..\edksetup.bat
+
+@REM Set for tools chain. Currently ARMGCC
+SET TARGET_TOOLS=ARMGCC
+SET TARGET=DEBUG
+
+
+@if /I "%1"=="RELEASE" (
+
+  @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it 
+
+  SET TARGET=RELEASE
+
+  shift /1
+
+)
+
+
+SET BUILD_ROOT=%WORKSPACE%\Build\ArmRealViewEb\%TARGET%_%TARGET_TOOLS%
+
+@REM Build the ARM RealView EB firmware and creat an FD (FLASH Device) Image.
+CALL build -p ArmRealViewEbPkg\ArmRealViewEbPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8
+@if ERRORLEVEL 1 goto Exit
+
+@if /I "%1"=="CLEAN" goto Clean
+
+
+ECHO Patching ..\Debugger_scripts ...
+SET DEBUGGER_SCRIPT=Debugger_scripts
+@for /f %%a IN ('dir /b %DEBUGGER_SCRIPT%\*.inc %DEBUGGER_SCRIPT%\*.cmm') do (
+  @CALL replace %DEBUGGER_SCRIPT%\%%a %BUILD_ROOT%\%%a ZZZZZZ %BUILD_ROOT% WWWWWW  %WORKSPACE%
+)
+
+:Exit
+EXIT /B
+
+:Clean
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/build.sh b/ArmPlatformPkg/ArmRealViewEbPkg/build.sh
new file mode 100644 (file)
index 0000000..89b176e
--- /dev/null
@@ -0,0 +1,118 @@
+#!/bin/bash
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+set -e
+shopt -s nocasematch
+
+function process_debug_scripts {
+  if [[ -d $1 ]]; then
+    for filename in `ls $1`
+    do
+      sed -e "s@ZZZZZZ@$BUILD_ROOT@g" -e "s@WWWWWW@$WORKSPACE@g" \
+            "$1/$filename" \
+            > "$BUILD_ROOT/$filename"
+
+      #For ARMCYGWIN, we have to change /cygdrive/c to c:
+      if [[ $TARGET_TOOLS == RVCT31CYGWIN ]]
+      then
+        mv "$BUILD_ROOT/$filename" "$BUILD_ROOT/$filename"_temp
+        sed -e "s@/cygdrive/\(.\)@\1:@g" \
+              "$BUILD_ROOT/$filename"_temp \
+              > "$BUILD_ROOT/$filename"
+        rm -f "$BUILD_ROOT/$filename"_temp
+      fi
+    done
+  fi
+}
+
+
+#
+# Setup workspace if it is not set
+#
+if [ -z "$WORKSPACE" ]
+then
+  echo Initializing workspace
+  cd ..
+  export EDK_TOOLS_PATH=`pwd`/BaseTools
+  source edksetup.sh BaseTools
+else
+  echo Building from: $WORKSPACE
+fi
+
+#
+# Pick a default tool type for a given OS
+#
+case `uname` in
+  CYGWIN*) 
+      TARGET_TOOLS=RVCT31CYGWIN 
+      ;;
+  Linux*)  
+      # Not tested
+      TARGET_TOOLS=ARMGCC 
+      ;;
+  Darwin*) 
+      Major=$(uname -r | cut -f 1 -d '.')
+      if [[ $Major == 9 ]]
+      then
+        # Not supported by this open source project
+        TARGET_TOOLS=XCODE31
+      else 
+        TARGET_TOOLS=XCODE32
+      fi  
+      ;;
+esac
+
+TARGET=DEBUG
+for arg in "$@"
+do
+  if [[ $arg == RELEASE ]]; 
+  then
+    TARGET=RELEASE
+  fi
+done
+
+BUILD_ROOT=$WORKSPACE/Build/ArmRealViewEb/"$TARGET"_"$TARGET_TOOLS"
+
+if  [[ ! -e $EDK_TOOLS_PATH/Source/C/bin ]];
+then
+  # build the tools if they don't yet exist
+  echo Building tools: $EDK_TOOLS_PATH
+  make -C $EDK_TOOLS_PATH
+else
+  echo using prebuilt tools
+fi
+
+#
+# Build the edk2 ArmEb code
+#
+if [[ $TARGET == RELEASE ]]; then
+  build -p $WORKSPACE/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dsc -a ARM -t $TARGET_TOOLS -b $TARGET -D DEBUG_TARGET=RELEASE $2 $3 $4 $5 $6 $7 $8
+else
+  build -p $WORKSPACE/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dsc -a ARM -t $TARGET_TOOLS -b $TARGET $1 $2 $3 $4 $5 $6 $7 $8
+fi
+
+
+for arg in "$@"
+do
+  if [[ $arg == clean ]]; then
+    # no need to post process if we are doing a clean
+    exit
+  elif [[ $arg == cleanall ]]; then
+    make -C $EDK_TOOLS_PATH clean
+    exit
+    
+  fi
+done
+
+
+echo Creating debugger scripts
+process_debug_scripts $WORKSPACE/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts
+
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
new file mode 100644 (file)
index 0000000..7103ab2
--- /dev/null
@@ -0,0 +1,499 @@
+#
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ArmVExpressPkg-CTA9x4
+  PLATFORM_GUID                  = eb2bd5ff-2379-4a06-9c12-db905cdee9ea 
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+!if $(EDK2_ARMVE_STANDALONE) == 1
+  OUTPUT_DIRECTORY               = Build/ArmVExpress-CTA9x4-Standalone
+!else
+  OUTPUT_DIRECTORY               = Build/ArmVExpress-CTA9x4
+!endif
+  SUPPORTED_ARCHITECTURES        = ARM
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf
+
+[LibraryClasses.common]
+!if $(BUILD_TARGETS) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+#  UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+!endif
+
+  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
+  ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
+  ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
+  ArmMPCoreMailBoxLib|ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBoxLib.inf
+  
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+
+  EfiResetSystemLib|ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  
+  EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf
+  EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  
+  #
+  # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window 
+  # in the debugger will show load and unload commands for symbols. You can cut and paste this
+  # into the command window to load symbols. We should be able to use a script to do this, but
+  # the version of RVD I have does not support scripts accessing system memory.
+  #
+#  PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+#  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  
+  SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+  
+  RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  
+  # ARM PL341 DMC Driver
+  PL341DmcLib|ArmPkg/Drivers/PL34xDmc/PL341Dmc.inf
+  # ARM PL301 Axi Driver
+  PL301AxiLib|ArmPkg/Drivers/PL301Axi/PL301Axi.inf
+
+#
+# Assume everything is fixed at build
+#
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+  EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
+
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+  EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+  
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
+
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+  TimerLib|ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf  
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+  
+  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+
+[LibraryClasses.common.SEC]
+  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
+  
+  # 1/123 faster than Stm or Vstm version
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+  # Uncomment to turn on GDB stub in SEC. 
+  #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+  
+  # ARM PL354 SMC Driver
+  PL354SmcSecLib|ArmPkg/Drivers/PL35xSmc/PL354SmcSec.inf
+  # ARM PL310 L2 Cache Driver
+  L2X0CacheLib|ArmPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf
+  # ARM PL390 General Interrupt Driver in Secure and Non-secure
+  PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
+  PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+
+[LibraryClasses.common.PEI_CORE]
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  # note: this won't actually work since globals in PEI are not writeable
+  # need to generate an ARM PEI services table pointer implementation
+  PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.PEIM]
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  # note: this won't actually work since globals in PEI are not writeable
+  # need to generate an ARM PEI services table pointer implementation
+  PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+  
+
+[LibraryClasses.common.DXE_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+#  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+  #
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+  # This library provides the instrinsic functions generate by a given compiler.
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[BuildOptions]
+  RVCT:*_*_ARM_ARCHCC_FLAGS  == --cpu Cortex-A9 --thumb -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+  RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A9 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+
+  ARMGCC:*_*_ARM_ARCHCC_FLAGS  == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+  ARMGCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+  
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+  
+  #
+  # Control what commands are supported from the UI
+  # Turn these on and off to add features or save size
+  #  
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE  
+  
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+  
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+!if $(EDK2_ARMVE_STANDALONE) == 1
+  gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE
+!endif
+
+!if $(EDK2_SKIP_PEICORE) == 1
+  gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE
+!endif
+
+[PcdsFixedAtBuild.common]
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress %a"
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+# DEBUG_ASSERT_ENABLED       0x01
+# DEBUG_PRINT_ENABLED        0x02
+# DEBUG_CODE_ENABLED         0x04
+# CLEAR_MEMORY_ENABLED       0x08
+# ASSERT_BREAKPOINT_ENABLED  0x10
+# ASSERT_DEADLOOP_ENABLED    0x20
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+
+#  DEBUG_INIT      0x00000001  // Initialization
+#  DEBUG_WARN      0x00000002  // Warnings
+#  DEBUG_LOAD      0x00000004  // Load events
+#  DEBUG_FS        0x00000008  // EFI File system
+#  DEBUG_POOL      0x00000010  // Alloc & Free's
+#  DEBUG_PAGE      0x00000020  // Alloc & Free's
+#  DEBUG_INFO      0x00000040  // Verbose
+#  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
+#  DEBUG_VARIABLE  0x00000100  // Variable
+#  DEBUG_BM        0x00000400  // Boot Manager
+#  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+#  DEBUG_NET       0x00004000  // SNI Driver
+#  DEBUG_UNDI      0x00010000  // UNDI Driver
+#  DEBUG_LOADFILE  0x00020000  // UNDI Driver
+#  DEBUG_EVENT     0x00080000  // Event messages
+#  DEBUG_ERROR     0x80000000  // Error
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+  
+#
+# Optional feature to help prevent EFI memory map fragments
+# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+# Values are in EFI Pages (4K). DXE Core will make sure that 
+# at least this much of each type of memory can be allocated 
+# from a single memory range. This way you only end up with
+# maximum of two fragements for each type in the memory map
+# (the memory used, and the free memory that was prereserved
+# but not used).
+#
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+  
+  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
+  gArmTokenSpaceGuid.PcdVFPEnabled|1
+  
+  # Stacks for MPCores in Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x49E00000            # Top of SEC Stack for Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000                   # Stack for each of the 4 CPU cores
+
+  # Stacks for MPCores in Monitor Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x49D00000     # Top of SEC Stack for Monitor World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x2000              # Stack for each of the 4 CPU cores
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000     # Top of SEC Stack for Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x00020000     # Stack for each of the 4 CPU cores
+  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004        # pei services ptr just above stack. Overlapped with the stack of CoreId 1
+
+  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000        # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+  
+  #
+  # ARM Pcds
+  #
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+    
+  #
+  # ARM PrimeCell
+  #
+  gArmTokenSpaceGuid.PcdPL180SysMciRegAddress|0x10000048
+  gArmTokenSpaceGuid.PcdPL180MciBaseAddress|0x10005000
+
+  #
+  # ARM PL390 General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x1e001000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x1e000100
+
+  #
+  # ARM OS Loader
+  #
+  # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: 
+  gArmTokenSpaceGuid.PcdArmMachineType|2272
+  gArmTokenSpaceGuid.PcdLinuxKernelDP|L"VenHw(02118005-9DA7-443a-92D5-781F022AEDBB)/MemoryMapped(0,0x46000000,0x46400000)"
+  gArmTokenSpaceGuid.PcdLinuxAtag|"rdinit=/bin/ash debug earlyprintk console=ttyAMA0,38400 mem=1G"
+  gArmTokenSpaceGuid.PcdFdtDP|L""
+
+  #
+  # ARM PL111 Colour LCD Controller
+  #
+  gArmVExpressTokenSpaceGuid.PcdPL111RegistersBaseMotherboard|0x1001F000
+  gArmVExpressTokenSpaceGuid.PcdPL111RegistersBaseDaughterboard|0x10020000
+  gArmVExpressTokenSpaceGuid.PcdPL111VRamBaseMotherboard|0x4C000000
+  gArmVExpressTokenSpaceGuid.PcdPL111VRamBaseDaughterboard|0x64000000
+  gArmVExpressTokenSpaceGuid.PcdPL111VRamSize|0x800000
+  
+  #
+  # ARM L2x0 PCDs
+  #
+  gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1E00A000
+
+  #
+  # ARM VE MP Core Mailbox
+  #
+  gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0x10000030
+  gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0x10000030
+  gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0x10000034
+  gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0xFFFFFFFF
+
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  
+#
+# SEC
+#
+  ArmPlatformPkg/Sec/Sec.inf
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  
+#
+# PEI Phase modules
+#
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf  {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  ArmPlatformPkg/PlatformPei/PlatformPei.inf
+  ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  Nt32Pkg/BootModePei/BootModePei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+
+#
+# DXE
+#
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf  
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf  
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  
+  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
+  ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashDxe.inf
+  ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+
+  #
+  # Semi-hosting filesystem
+  #
+  ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+  
+  #
+  # Multimedia Card Interface
+  #
+  ArmPkg/Universal/MmcDxe/MmcDxe.inf
+  ArmPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+  
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Application
+  #  
+  EmbeddedPkg/Ebl/Ebl.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  ArmPlatformPkg/Bds/Bds.inf
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf
new file mode 100644 (file)
index 0000000..d1e8780
--- /dev/null
@@ -0,0 +1,391 @@
+# FLASH layout file for ARM VE.
+#
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.Sec_ArmVExpress_EFI]
+BaseAddress   = 0x44000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress  #The base address of the Secure FLASH Device.
+Size          = 0x00200000|gArmTokenSpaceGuid.PcdSecureFdSize         #The size in bytes of the Secure FLASH Device
+ErasePolarity = 1
+BlockSize     = 0x00001000
+NumBlocks     = 0x200
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize
+FV = FVMAIN_SEC
+
+
+[FD.ArmVExpress_EFI]
+!if $(EDK2_ARMVE_STANDALONE) == 1
+BaseAddress   = 0x45000000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress  # The base address of the Firmware in NOR Flash.
+!else
+BaseAddress   = 0x80000000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress  # The base address of the Firmware in remapped DRAM.
+!endif
+Size          = 0x00200000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x200
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+
+[FD.NVVariableStore]
+BaseAddress   = 0x47FC0000
+Size          = 0x00030000
+ErasePolarity = 1
+BlockSize     = 0x00010000
+NumBlocks     = 0x3
+
+0x00000000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  #  { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x30000
+  0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x34, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 3 Blocks * 0x10000 Bytes / Block
+  0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  
+  ## This is the VARIABLE_STORE_HEADER
+  #Signature: gEfiVariableGuid =
+  #  { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  #Size: 0x10000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER: HeaderLength) = 0xFFB8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x00, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00010000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#FTW_SPARE_STORE - See EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER
+DATA = {
+  #Signature: gEfiSystemNvDataFvGuid =
+  #  { 0xfff12b8d, 0x7696, 0x4c8b, { 0xa9, 0x85, 0x27, 0x47, 0x07, 0x5b, 0x4f, 0x50 } }
+  0x8d, 0x2b, 0xf1, 0xff, 0x96, 0x32, 0x8b, 0x4c,
+  0xa9, 0x85, 0x27, 0x47, 0x07, 0x5b, 0x4f, 0x50,
+  #FIXME: 32bit CRC caculated for this header.
+  0x00, 0x00, 0x00, 0x00,
+  # Working block valid bit
+  0x00,
+  # Total size of the following write queue range. (64bit)
+  0xB8, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  
+  # Write Queue data: EFI_FAULT_TOLERANT_WRITE_HEADER
+  # State
+  0x00,
+  # CallerId: Guid
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # NumberOfWrites, PrivateDataSize
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00020000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+DATA = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf 
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services) 
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+   
+  INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
+  INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+  INF ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashDxe.inf
+
+  #
+  # Semi-hosting filesystem
+  #
+  INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+  
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  INF ArmPkg/Universal/MmcDxe/MmcDxe.inf
+  INF ArmPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+  
+  #
+  # UEFI application (Shell Embedded Boot Loader) 
+  #  
+  INF EmbeddedPkg/Ebl/Ebl.inf
+    
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF ArmPlatformPkg/Bds/Bds.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPei.inf
+  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+  
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   # 
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX Optional      |.depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    |.efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 8      |.efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE           |.efi
+    UI     STRING ="$(MODULE_NAME)" Optional         
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional        |.depex
+     TE       TE                         |.efi
+     UI       STRING="$(MODULE_NAME)" Optional         
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional         |.depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                     |.efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32           |.efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX Optional      |.depex
+    PE32         PE32                    |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX Optional      |.depex
+    PE32         PE32                    |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX Optional      |.depex
+    PE32         PE32                    |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)" Optional         
+    PE32   PE32                    |.efi
+  }
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
new file mode 100644 (file)
index 0000000..9cc9324
--- /dev/null
@@ -0,0 +1,39 @@
+#/** @file
+# Arm Versatile Express package.
+#
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = ArmVExpressPkg
+  PACKAGE_GUID                   = 9c0aaed4-74c5-4043-b417-a3223814ce76 
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
+
+[Guids.common]
+  gArmVExpressTokenSpaceGuid    =  { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
+
+[PcdsFeatureFlag.common]
+
+[PcdsFixedAtBuild.common]
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h
new file mode 100644 (file)
index 0000000..fa6e8d8
--- /dev/null
@@ -0,0 +1,150 @@
+/** @file\r
+*  Header defining Versatile Express constants (Base addresses, sizes, flags)\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  \r
+*  This program and the accompanying materials                          \r
+*  are licensed and made available under the terms and conditions of the BSD License         \r
+*  which accompanies this distribution.  The full text of the license may be found at        \r
+*  http://opensource.org/licenses/bsd-license.php                                            \r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*\r
+**/\r
+\r
+#ifndef __ARM_VEXPRESS_H__\r
+#define __ARM_VEXPRESS_H__\r
+\r
+/*******************************************\r
+// Platform Memory Map\r
+*******************************************/\r
+\r
+// Can be NOR0, NOR1, DRAM\r
+#define ARM_VE_REMAP_BASE                       0x00000000\r
+#define ARM_VE_REMAP_SZ                         0x04000000\r
+\r
+// Motherboard Peripheral and On-chip peripheral\r
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE       0x10000000\r
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ         0x10000000 /* 256 MB */\r
+#define ARM_VE_BOARD_PERIPH_BASE                0x10000000\r
+#define ARM_VE_CHIP_PERIPH_BASE                 0x10020000\r
+\r
+// SMC\r
+#define ARM_VE_SMC_BASE                         0x40000000\r
+#define ARM_VE_SMC_SZ                           0x1C000000\r
+\r
+// NOR Flash 1\r
+#define ARM_VE_SMB_NOR0_BASE                    0x40000000\r
+#define ARM_VE_SMB_NOR0_SZ                      0x04000000 /* 64 MB */\r
+// NOR Flash 2\r
+#define ARM_VE_SMB_NOR1_BASE                    0x44000000\r
+#define ARM_VE_SMB_NOR1_SZ                      0x04000000 /* 64 MB */\r
+// SRAM\r
+#define ARM_VE_SMB_SRAM_BASE                    0x48000000\r
+#define ARM_VE_SMB_SRAM_SZ                      0x02000000 /* 32 MB */\r
+// USB, Ethernet, VRAM\r
+#define ARM_VE_SMB_PERIPH_BASE                  0x4C000000\r
+#define ARM_VE_SMB_PERIPH_VRAM                  0x4C000000\r
+#define ARM_VE_SMB_PERIPH_SZ                    0x04000000 /* 32 MB */\r
+\r
+// DRAM\r
+#define ARM_VE_DRAM_BASE                        0x60000000\r
+#define ARM_VE_DRAM_SZ                          0x40000000\r
+\r
+// External AXI between daughterboards (Logic Tile)\r
+#define ARM_VE_EXT_AXI_BASE                     0xE0000000\r
+#define ARM_VE_EXT_AXI_SZ                       0x20000000\r
+\r
+/*******************************************\r
+// Motherboard peripherals\r
+*******************************************/\r
+\r
+// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r
+#define ARM_VE_SYS_FLAGS_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_VE_SYS_FLAGS_SET_REG                (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_VE_SYS_FLAGS_CLR_REG                (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r
+#define ARM_VE_SYS_FLAGS_NV_REG                 (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_VE_SYS_FLAGS_NV_SET_REG             (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_VE_SYS_FLAGS_NV_CLR_REG             (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r
+#define ARM_VE_SYS_PROCID0_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r
+#define ARM_VE_SYS_PROCID1_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r
+#define ARM_VE_SYS_CFGDATA_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r
+#define ARM_VE_SYS_CFGCTRL_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r
+#define ARM_VE_SYS_CFGSTAT_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r
+\r
+// SP810 Controller\r
+#define SP810_CTRL_BASE                      (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r
+\r
+// Uart0\r
+#define PL011_CONSOLE_UART_BASE                (ARM_VE_BOARD_PERIPH_BASE + 0x09000)\r
+#define PL011_CONSOLE_UART_SPEED               38400\r
+\r
+// SP804 Timer Bases\r
+#define SP804_TIMER0_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x11000)\r
+#define SP804_TIMER1_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x11020)\r
+#define SP804_TIMER2_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x12000)\r
+#define SP804_TIMER3_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x12020)\r
+\r
+// Dynamic Memory Controller Base\r
+#define ARM_VE_DMC_BASE                         0x100E0000\r
+\r
+// Static Memory Controller Base\r
+#define ARM_VE_SMC_CTRL_BASE                    0x100E1000\r
+\r
+// System Configuration Controller register Base addresses\r
+//#define ARM_VE_SYS_CFG_CTRL_BASE                0x100E2000\r
+#define ARM_VE_SYS_CFGRW0_REG                   0x100E2000\r
+#define ARM_VE_SYS_CFGRW1_REG                   0x100E2004\r
+#define ARM_VE_SYS_CFGRW2_REG                   0x100E2008\r
+\r
+#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK         0x2000\r
+#define ARM_VE_CFGRW1_REMAP_NOR0                0\r
+#define ARM_VE_CFGRW1_REMAP_NOR1                (1 << 28)\r
+#define ARM_VE_CFGRW1_REMAP_EXT_AXI             (1 << 29)\r
+#define ARM_VE_CFGRW1_REMAP_DRAM                (1 << 30)\r
+\r
+// TZPC Base Address\r
+#define ARM_VE_TZPC_BASE                        0x100E6000\r
+\r
+// PL301 Fast AXI Base Address\r
+#define ARM_VE_FAXI_BASE                        0x100E9000\r
+\r
+// TZASC Defintions\r
+#define ARM_VE_TZASC_BASE                       0x100EC000\r
+#define ARM_VE_DECPROT_BIT_TZPC                 (1 << 6)\r
+#define ARM_VE_DECPROT_BIT_DMC_TZASC            (1 << 11)\r
+#define ARM_VE_DECPROT_BIT_NMC_TZASC            (1 << 12)\r
+#define ARM_VE_DECPROT_BIT_SMC_TZASC            (1 << 13)\r
+#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ          (1)\r
+#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK       (1 << 3)\r
+#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK       (1 << 4)\r
+#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK       (1 << 5)\r
+\r
+// L2x0 Cache Controller Base Address\r
+//#define ARM_VE_L2x0_CTLR_BASE                   0x1E00A000\r
+\r
+\r
+/*******************************************\r
+// Interrupt Map\r
+*******************************************/\r
+\r
+// Timer Interrupts\r
+#define TIMER01_INTERRUPT_NUM                34\r
+#define TIMER23_INTERRUPT_NUM                35\r
+\r
+\r
+/*******************************************\r
+// EFI Memory Map in Permanent Memory (DRAM)\r
+*******************************************/\r
+\r
+// This region is allocated at the bottom of the DRAM. It will be used\r
+// for fixed address allocations such as Vector Table\r
+#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ        SIZE_8MB\r
+\r
+// This region is the memory declared to PEI as permanent memory for PEI\r
+// and DXE. EFI stacks and heaps will be declared in this region.\r
+#define ARM_VE_EFI_MEMORY_REGION_SZ             0x1000000\r
+\r
+\r
+#endif \r
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
new file mode 100644 (file)
index 0000000..7f68992
--- /dev/null
@@ -0,0 +1,49 @@
+#/* @file
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = CTA9x4ArmVExpressLib
+  FILE_GUID                      = b16c63a0-f417-11df-b3af-0002a5d5c51b
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  ArmTrustZoneLib
+  MemoryAllocationLib
+  PL341DmcLib
+  PL301AxiLib
+
+[Sources.common]
+  CTA9x4.c
+  CTA9x4Mem.c
+
+[Protocols]
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdStandalone
+
+[FixedPcd]
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
new file mode 100644 (file)
index 0000000..5a05479
--- /dev/null
@@ -0,0 +1,50 @@
+#/* @file\r
+#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+#  \r
+#  This program and the accompanying materials                          \r
+#  are licensed and made available under the terms and conditions of the BSD License         \r
+#  which accompanies this distribution.  The full text of the license may be found at        \r
+#  http://opensource.org/licenses/bsd-license.php                                            \r
+#\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+#\r
+#*/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = CTA9x4ArmVExpressLib\r
+  FILE_GUID                      = b16c63a0-f417-11df-b3af-0002a5d5c51b\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmPlatformLib\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  EmbeddedPkg/EmbeddedPkg.dec\r
+  ArmPkg/ArmPkg.dec\r
+  ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  IoLib\r
+  ArmLib\r
+  ArmTrustZoneLib\r
+  PL354SmcSecLib\r
+  PL341DmcLib\r
+  PL301AxiLib\r
+\r
+[Sources.common]\r
+  CTA9x4.c\r
+  CTA9x4Helper.asm   | RVCT\r
+  CTA9x4Helper.S     | GCC\r
+\r
+[Protocols]\r
+\r
+[FeaturePcd]\r
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+  gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
+[FixedPcd]\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
new file mode 100644 (file)
index 0000000..497e0da
--- /dev/null
@@ -0,0 +1,157 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  
+*  This program and the accompanying materials                          
+*  are licensed and made available under the terms and conditions of the BSD License         
+*  which accompanies this distribution.  The full text of the license may be found at        
+*  http://opensource.org/licenses/bsd-license.php                                            
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmTrustZoneLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Drivers/PL341Dmc.h>
+
+// DDR2 timings
+struct pl341_dmc_config ddr_timings = {
+    .base              = ARM_VE_DMC_BASE,
+    .has_qos           = 1,
+    .refresh_prd       = 0x3D0,
+    .cas_latency       = 0x8,
+    .write_latency     = 0x3,
+    .t_mrd             = 0x2,
+    .t_ras             = 0xA,
+    .t_rc              = 0xE,
+    .t_rcd             = 0x104,
+    .t_rfc             = 0x2f32,
+    .t_rp              = 0x14,
+    .t_rrd             = 0x2,
+    .t_wr              = 0x4,
+    .t_wtr             = 0x2,
+    .t_xp              = 0x2,
+    .t_xsr             = 0xC8,
+    .t_esr             = 0x14,
+    .memory_cfg                = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
+                          DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
+    .memory_cfg2       = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
+                                                 DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
+    .memory_cfg3       = 0x00000001,
+    .chip_cfg0         = 0x00010000,
+    .t_faw             = 0x00000A0D,
+};
+
+/**
+  Return if Trustzone is supported by your platform
+
+  A non-zero value must be returned if you want to support a Secure World on your platform.
+  ArmVExpressTrustzoneInit() will later set up the secure regions.
+  This function can return 0 even if Trustzone is supported by your processor. In this case,
+  the platform will continue to run in Secure World.
+
+  @return   A non-zero value if Trustzone supported.
+
+**/
+UINTN ArmPlatformTrustzoneSupported(VOID) {
+    return (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK);
+}
+
+/**
+  Initialize the Secure peripherals and memory regions
+
+  If Trustzone is supported by your platform then this function makes the required initialization
+  of the secure peripherals and memory regions.
+
+**/
+VOID ArmPlatformTrustzoneInit(VOID) {
+    //
+    // Setup TZ Protection Controller
+    //
+    
+    // Set Non Secure access for all devices
+    TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0, 0xFFFFFFFF);
+    TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_1, 0xFFFFFFFF);
+    TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2, 0xFFFFFFFF);
+
+    // Remove Non secure access to secure devices
+    TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0,
+         ARM_VE_DECPROT_BIT_TZPC | ARM_VE_DECPROT_BIT_DMC_TZASC | ARM_VE_DECPROT_BIT_NMC_TZASC | ARM_VE_DECPROT_BIT_SMC_TZASC);
+
+    TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2,
+         ARM_VE_DECPROT_BIT_EXT_MAST_TZ | ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK);
+
+
+    //
+    // Setup TZ Address Space Controller for the SMC. Create 5 Non Secure regions (NOR0, NOR1, SRAM, SMC Peripheral regions)
+    //
+
+    // NOR Flash 0 non secure (BootMon)
+    TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED,
+        ARM_VE_SMB_NOR0_BASE,0,
+        TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
+
+    // NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin)
+#if EDK2_ARMVE_SECURE_SYSTEM
+    //Note: Your OS Kernel must be aware of the secure regions before to enable this region
+    TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,
+        ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0,
+        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);
+#else
+    TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,
+        ARM_VE_SMB_NOR1_BASE,0,
+        TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
+#endif
+
+    // Base of SRAM. Only half of SRAM in Non Secure world
+    // First half non secure (16MB) + Second Half secure (16MB) = 32MB of SRAM
+#if EDK2_ARMVE_SECURE_SYSTEM
+    //Note: Your OS Kernel must be aware of the secure regions before to enable this region
+    TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,
+        ARM_VE_SMB_SRAM_BASE,0,
+        TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW);
+#else
+    TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,
+        ARM_VE_SMB_SRAM_BASE,0,
+        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);
+#endif
+
+    // Memory Mapped Peripherals. All in non secure world
+    TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED,
+        ARM_VE_SMB_PERIPH_BASE,0,
+        TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
+
+    // MotherBoard Peripherals and On-chip peripherals.
+    TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED,
+        ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0,
+        TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW);
+}
+
+/**
+  Remap the memory at 0x0
+
+  Some platform requires or gives the ability to remap the memory at the address 0x0.
+  This function can do nothing if this feature is not relevant to your platform.
+
+**/
+VOID ArmPlatformBootRemapping(VOID) {
+    UINT32 val32  = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
+    // we remap the DRAM to 0x0
+    MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (val32 & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID ArmPlatformInitializeSystemMemory(VOID) {
+    PL341DmcInit(&ddr_timings);
+    PL301AxiInit(ARM_VE_FAXI_BASE);
+}
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
new file mode 100644 (file)
index 0000000..f18d056
--- /dev/null
@@ -0,0 +1,74 @@
+#------------------------------------------------------------------------------ \r
+#\r
+# ARM VE Entry point. Reset vector in FV header will brach to\r
+# _ModuleEntryPoint. \r
+#\r
+# We use crazy macros, like LoadConstantToReg, since Xcode assembler \r
+# does not support = assembly syntax for ldr.\r
+#\r
+#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+#  \r
+#  This program and the accompanying materials                          \r
+#  are licensed and made available under the terms and conditions of the BSD License         \r
+#  which accompanies this distribution.  The full text of the license may be found at        \r
+#  http://opensource.org/licenses/bsd-license.php                                            \r
+#\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <AutoGen.h>\r
+\r
+#Start of Code section\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)\r
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)\r
+.extern ASM_PFX(InitializeSMC)\r
+\r
+/**\r
+  Called at the early stage of the Boot phase to know if the memory has already been initialized\r
+\r
+  Running the code from the reset vector does not mean we start from cold boot. In some case, we\r
+  can go through this code with the memory already initialized.\r
+  Because this function is called at the early stage, the implementation must not use the stack.\r
+  Its implementation must probably done in assembly to ensure this requirement.\r
+\r
+  @return   Return the condition value into the 'Z' flag\r
+\r
+**/\r
+ASM_PFX(ArmPlatformIsMemoryInitialized):\r
+  // Check if the memory has been already mapped, if so skipped the memory initialization\r
+  LoadConstantToReg (ARM_VE_SYS_CFGRW1_REG ,r0)\r
+  ldr   r0, [r0, #0]\r
+  \r
+  // 0x40000000 = Value of Physical Configuration Switch SW[0]\r
+  and   r0, r0, #0x40000000\r
+  tst   r0, #0x40000000\r
+  bx   lr\r
+\r
+/**\r
+  Initialize the memory where the initial stacks will reside\r
+\r
+  This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+  In some platform, this region is already initialized and the implementation of this function can\r
+  do nothing. This memory can also represent the Secure RAM.\r
+  This function is called before the satck has been set up. Its implementation must ensure the stack\r
+  pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ASM_PFX(ArmPlatformInitializeBootMemory):\r
+  mov   r5, lr\r
+  // Initialize PL354 SMC\r
+  LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
+  LoadConstantToReg (ARM_VE_SMB_PERIPH_VRAM, r2)\r
+  blx   ASM_PFX(InitializeSMC)\r
+  bx   r5\r
+\r
+.end\r
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
new file mode 100644 (file)
index 0000000..673052f
--- /dev/null
@@ -0,0 +1,68 @@
+//\r
+//  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//  \r
+//  This program and the accompanying materials                          \r
+//  are licensed and made available under the terms and conditions of the BSD License         \r
+//  which accompanies this distribution.  The full text of the license may be found at        \r
+//  http://opensource.org/licenses/bsd-license.php                                            \r
+//\r
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+  INCLUDE AsmMacroIoLib.inc\r
+  \r
+  EXPORT  ArmPlatformIsMemoryInitialized\r
+  EXPORT  ArmPlatformInitializeBootMemory\r
+  IMPORT  InitializeSMC\r
+  \r
+  PRESERVE8\r
+  AREA    CTA9x4Helper, CODE, READONLY\r
+\r
+/**\r
+  Called at the early stage of the Boot phase to know if the memory has already been initialized\r
+\r
+  Running the code from the reset vector does not mean we start from cold boot. In some case, we\r
+  can go through this code with the memory already initialized.\r
+  Because this function is called at the early stage, the implementation must not use the stack.\r
+  Its implementation must probably done in assembly to ensure this requirement.\r
+\r
+  @return   Return the condition value into the 'Z' flag\r
+\r
+**/\r
+ArmPlatformIsMemoryInitialized\r
+  // Check if the memory has been already mapped, if so skipped the memory initialization\r
+  LoadConstantToReg (ARM_VE_SYS_CFGRW1_REG ,r0)\r
+  ldr   r0, [r0, #0]\r
+  \r
+  // 0x40000000 = Value of Physical Configuration Switch SW[0]\r
+  and   r0, r0, #0x40000000\r
+  tst   r0, #0x40000000\r
+  bx   lr\r
+    \r
+/**\r
+  Initialize the memory where the initial stacks will reside\r
+\r
+  This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+  In some platform, this region is already initialized and the implementation of this function can\r
+  do nothing. This memory can also represent the Secure RAM.\r
+  This function is called before the satck has been set up. Its implementation must ensure the stack\r
+  pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ArmPlatformInitializeBootMemory\r
+  mov   r5, lr\r
+  // Initialize PL354 SMC\r
+  LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
+  LoadConstantToReg (ARM_VE_SMB_PERIPH_VRAM, r2)\r
+  blx   InitializeSMC\r
+  bx   r5\r
+  \r
+  END\r
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c
new file mode 100644 (file)
index 0000000..27eb362
--- /dev/null
@@ -0,0 +1,212 @@
+/** @file\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  \r
+*  This program and the accompanying materials                          \r
+*  are licensed and made available under the terms and conditions of the BSD License         \r
+*  which accompanies this distribution.  The full text of the license may be found at        \r
+*  http://opensource.org/licenses/bsd-license.php                                            \r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*\r
+**/\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+#define DDR_ATTRIBUTES_SECURE_CACHED    ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_SECURE_UNCACHED  ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED\r
+\r
+/**\r
+  Return the information about the memory region in permanent memory used by PEI\r
+\r
+  One of the PEI Module must install the permament memory used by PEI. This function returns the\r
+  information about this region for your platform to this PEIM module.\r
+\r
+  @param[out]   PeiMemoryBase       Base of the memory region used by PEI core and modules\r
+  @param[out]   PeiMemorySize       Size of the memory region used by PEI core and modules\r
+\r
+**/\r
+VOID ArmPlatformGetPeiMemory (\r
+    OUT UINTN*                                   PeiMemoryBase,\r
+    OUT UINTN*                                   PeiMemorySize\r
+    ) {\r
+    ASSERT((PeiMemoryBase != NULL) && (PeiMemorySize != NULL));\r
+    \r
+    *PeiMemoryBase = ARM_VE_DRAM_BASE + ARM_VE_EFI_FIX_ADDRESS_REGION_SZ;\r
+    *PeiMemorySize = ARM_VE_EFI_MEMORY_REGION_SZ;\r
+}\r
+\r
+/**\r
+  Return the Virtual Memory Map of your platform\r
+\r
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
+\r
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
+                                    Virtual Memory mapping. This array must be ended by a zero-filled\r
+                                    entry\r
+\r
+**/\r
+VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {\r
+    UINT32                        val32;\r
+    UINT32                        CacheAttributes;\r
+    BOOLEAN                       bTrustzoneSupport;\r
+    UINTN                         Index = 0;\r
+    ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;\r
+\r
+    ASSERT(VirtualMemoryMap != NULL);\r
+\r
+    VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9);\r
+    if (VirtualMemoryTable == NULL) {\r
+        return;\r
+    }\r
+\r
+    // Check if SMC TZASC is enabled. If Trustzone not enabled then all the entries remain in Secure World.\r
+    // As this value can be changed in the Board Configuration file, the UEFI firmware needs to work for both case\r
+    val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG);\r
+    if (ARM_VE_CFGRW1_TZASC_EN_BIT_MASK & val32) {\r
+        bTrustzoneSupport = TRUE;\r
+    } else {\r
+        bTrustzoneSupport = FALSE;\r
+    }\r
+\r
+    if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+        CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);\r
+    } else {\r
+        CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);\r
+    }\r
+\r
+    // ReMap (Either NOR Flash or DRAM)\r
+    VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_REMAP_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_VE_REMAP_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+    // DDR\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_DRAM_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_VE_DRAM_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+    // SMC CS7\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+    // SMB CS0-CS1 - NOR Flash 1 & 2\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_NOR0_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+    // SMB CS2 - SRAM\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_SRAM_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_VE_SMB_SRAM_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+    // SMB CS3-CS6 - Motherboard Peripherals\r
+    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
+    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_PERIPH_BASE;\r
+    VirtualMemoryTable[Index].Length       = ARM_VE_SMB_PERIPH_SZ;\r
+    VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+    // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
+    if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {\r
+        VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;\r
+        VirtualMemoryTable[Index].VirtualBase  = ARM_VE_EXT_AXI_BASE;\r
+        VirtualMemoryTable[Index].Length       = ARM_VE_EXT_AXI_SZ;\r
+        VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+    }\r
+\r
+    // End of Table\r
+    VirtualMemoryTable[++Index].PhysicalBase = 0;\r
+    VirtualMemoryTable[Index].VirtualBase  = 0;\r
+    VirtualMemoryTable[Index].Length       = 0;\r
+    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
+    *VirtualMemoryMap = VirtualMemoryTable;\r
+}\r
+\r
+/**\r
+  Return the EFI Memory Map of your platform\r
+\r
+  This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource\r
+  Descriptor HOBs used by DXE core.\r
+\r
+  @param[out]   EfiMemoryMap        Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an\r
+                                    EFI Memory region. This array must be ended by a zero-filled entry\r
+\r
+**/\r
+VOID ArmPlatformGetEfiMemoryMap (\r
+    OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
+) {\r
+    EFI_RESOURCE_ATTRIBUTE_TYPE     Attributes;\r
+    UINT64                          MemoryBase;\r
+    UINTN                           Index = 0;\r
+    ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR  *EfiMemoryTable;\r
+\r
+    ASSERT(EfiMemoryMap != NULL);\r
+\r
+    EfiMemoryTable = (ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR) * 6);\r
+\r
+    Attributes =\r
+    (\r
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_TESTED\r
+    );\r
+    MemoryBase = ARM_VE_DRAM_BASE;\r
+  \r
+    // Memory Reserved for fixed address allocations (such as Exception Vector Table)\r
+    EfiMemoryTable[Index].ResourceAttribute = Attributes;\r
+    EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+    EfiMemoryTable[Index].NumberOfBytes = ARM_VE_EFI_FIX_ADDRESS_REGION_SZ;\r
+    \r
+    MemoryBase += ARM_VE_EFI_FIX_ADDRESS_REGION_SZ;\r
+\r
+    // Memory declared to PEI as permanent memory for PEI and DXE\r
+    EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
+    EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+    EfiMemoryTable[Index].NumberOfBytes = ARM_VE_EFI_MEMORY_REGION_SZ;\r
+\r
+    MemoryBase += ARM_VE_EFI_MEMORY_REGION_SZ;\r
+\r
+    // We must reserve the memory used by the Firmware Volume copied in DRAM at 0x80000000\r
+    if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
+        // Chunk between the EFI Memory region and the firmware\r
+        EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
+        EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+        EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdBaseAddress) - MemoryBase;\r
+\r
+        // Chunk reserved by the firmware in DRAM\r
+        EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_PRESENT);\r
+        EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdEmbeddedFdBaseAddress);\r
+        EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdSize);\r
+\r
+        MemoryBase = PcdGet32(PcdEmbeddedFdBaseAddress) + PcdGet32(PcdEmbeddedFdSize);\r
+    }\r
+      \r
+    // We allocate all the remain memory as untested system memory\r
+    EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_TESTED);\r
+    EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+    EfiMemoryTable[Index].NumberOfBytes = ARM_VE_DRAM_SZ - (MemoryBase-ARM_VE_DRAM_BASE);\r
+\r
+    EfiMemoryTable[++Index].ResourceAttribute = 0;\r
+    EfiMemoryTable[Index].PhysicalStart = 0;\r
+    EfiMemoryTable[Index].NumberOfBytes = 0;\r
+\r
+    *EfiMemoryMap = EfiMemoryTable;\r
+}\r
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.c
new file mode 100644 (file)
index 0000000..88d075a
--- /dev/null
@@ -0,0 +1,84 @@
+/** @file
+  Template library implementation to support ResetSystem Runtime call.
+  
+  Fill in the templates with what ever makes you system reset.
+
+
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/EfiResetSystemLib.h>
+
+#include <ArmPlatform.h>
+
+/**
+  Resets the entire platform.
+
+  @param  ResetType             The type of reset to perform.
+  @param  ResetStatus           The status code for the reset.
+  @param  DataSize              The size, in bytes, of WatchdogData.
+  @param  ResetData             For a ResetType of EfiResetCold, EfiResetWarm, or
+                                EfiResetShutdown the data buffer starts with a Null-terminated
+                                Unicode string, optionally followed by additional binary data.
+
+**/
+EFI_STATUS
+EFIAPI
+LibResetSystem (
+  IN EFI_RESET_TYPE   ResetType,
+  IN EFI_STATUS       ResetStatus,
+  IN UINTN            DataSize,
+  IN CHAR16           *ResetData OPTIONAL
+  )
+{
+  if (ResetData != NULL) {
+    DEBUG ((EFI_D_ERROR, "%s", ResetData));
+  }
+
+  switch (ResetType) {
+  case EfiResetWarm:
+    // Map a warm reset into a cold reset
+  case EfiResetCold:
+  case EfiResetShutdown:
+  default:
+    CpuDeadLoop ();
+    break;
+  }
+
+  // If the reset didn't work, return an error.
+  ASSERT (FALSE);
+  return EFI_DEVICE_ERROR;
+}
+
+/**
+  Initialize any infrastructure required for LibResetSystem () to function.
+
+  @param  ImageHandle   The firmware allocated handle for the EFI image.
+  @param  SystemTable   A pointer to the EFI System Table.
+  
+  @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+LibInitializeResetSystem (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  return EFI_SUCCESS;
+}
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf
new file mode 100644 (file)
index 0000000..23d4715
--- /dev/null
@@ -0,0 +1,34 @@
+#/** @file
+# Reset System lib to make it easy to port new platforms
+#
+# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmVeResetSystemLib
+  FILE_GUID                      = 36885202-0854-4373-bfd2-95d229b44d44 
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = EfiResetSystemLib
+
+[Sources.common]
+  ResetSystemLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
+
+[LibraryClasses]
+  DebugLib
+  BaseLib
diff --git a/ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashBlockIoDxe.c b/ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashBlockIoDxe.c
new file mode 100644 (file)
index 0000000..ad2c87b
--- /dev/null
@@ -0,0 +1,149 @@
+/** @file  NorFlashBlockIoDxe.c
+
+  Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "NorFlashDxe.h"
+
+EFI_STATUS
+EFIAPI
+NorFlashBlkIoInitialize (
+  IN NOR_FLASH_INSTANCE* Instance
+  ) {
+  UINT32                Reply;
+  EFI_STATUS            Status = EFI_SUCCESS;
+
+  DEBUG((DEBUG_BLKIO,"NorFlashBlkIoInitialize()\n"));
+
+  //
+  // Verify that there is a physical hardware device where we expect it to be.
+  //
+
+  // Read a specific CFI query that returns back "QRY"
+  // This ensures that there is really a device present there
+  SEND_NOR_COMMAND( Instance->BaseAddress, 0, P30_CMD_READ_CFI_QUERY );
+
+  // Read CFI 'QRY' data
+  Status = NorFlashReadCfiData( Instance->BaseAddress,
+                                 P30_CFI_ADDR_QUERY_UNIQUE_QRY,
+                                 3,
+                                 &Reply
+                               );
+  if (EFI_ERROR(Status)) {
+    goto EXIT;
+  }
+
+  if ( Reply != CFI_QRY ) {
+    DEBUG((EFI_D_ERROR, "NorFlashBlkIoInitialize: CFI QRY=0x%x (expected 0x595251)\n", Reply));
+    Status = EFI_DEVICE_ERROR;
+    goto EXIT;
+  }
+
+EXIT:
+  // Reset the device
+  Status = NorFlashBlockIoReset( &Instance->BlockIoProtocol, FALSE );
+  if (EFI_ERROR(Status)) {
+    goto EXIT;
+  }
+
+  Instance->Initialized = TRUE;
+  return EFI_SUCCESS;
+}
+
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReset (
+  IN EFI_BLOCK_IO_PROTOCOL  *This,
+  IN BOOLEAN                ExtendedVerification
+  )
+{
+  EFI_STATUS     Status;
+  NOR_FLASH_INSTANCE *Instance;
+
+  Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+  DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReset(MediaId=0x%x)\n", This->Media->MediaId));
+
+  Status = NorFlashReset(Instance);
+
+  return Status;
+
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReadBlocks (
+  IN  EFI_BLOCK_IO_PROTOCOL   *This,
+  IN  UINT32                  MediaId,
+  IN  EFI_LBA                 Lba,
+  IN  UINTN                   BufferSizeInBytes,
+  OUT VOID                    *Buffer
+  )
+{
+  NOR_FLASH_INSTANCE *Instance;
+
+  Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+  DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+  return NorFlashReadBlocks(Instance,Lba,BufferSizeInBytes,Buffer);
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoWriteBlocks (
+  IN  EFI_BLOCK_IO_PROTOCOL   *This,
+  IN  UINT32                  MediaId,
+  IN  EFI_LBA                 Lba,
+  IN  UINTN                   BufferSizeInBytes,
+  IN  VOID                    *Buffer
+  )
+{
+  NOR_FLASH_INSTANCE *Instance;
+
+  Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+  DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoWriteBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+  return NorFlashWriteBlocks(Instance,Lba,BufferSizeInBytes,Buffer);
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoFlushBlocks (
+  IN EFI_BLOCK_IO_PROTOCOL  *This
+  )
+{
+  // No Flush required for the NOR Flash driver
+  // because cache operations are not permitted.
+
+  DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoFlushBlocks: Function NOT IMPLEMENTED (not required).\n"));
+
+  // Nothing to do so just return without error
+  return EFI_SUCCESS;
+}
diff --git a/ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashDxe.c b/ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashDxe.c
new file mode 100644 (file)
index 0000000..333e7d4
--- /dev/null
@@ -0,0 +1,802 @@
+/** @file  NorFlashDxe.c
+
+  Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "NorFlashDxe.h"
+
+
+//
+// Global variable declarations
+//
+
+#define NOR_FLASH_LAST_DEVICE                     4
+
+NOR_FLASH_DESCRIPTION mNorFlashDescription[NOR_FLASH_LAST_DEVICE] = {
+  { // BootMon
+    ARM_VE_SMB_NOR0_BASE,
+    SIZE_256KB * 255,
+    SIZE_256KB,
+    FALSE,
+    {0xE7223039, 0x5836, 0x41E1, 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59}
+  },
+  { // BootMon non-volatile storage
+    ARM_VE_SMB_NOR0_BASE + SIZE_256KB * 255,
+    SIZE_64KB * 4,
+    SIZE_64KB,
+    FALSE,
+    {0x02118005, 0x9DA7, 0x443A, 0x92, 0xD5, 0x78, 0x1F, 0x02, 0x2A, 0xED, 0xBB}
+  },
+  { // UEFI
+    ARM_VE_SMB_NOR1_BASE,
+    SIZE_256KB * 255,
+    SIZE_256KB,
+    FALSE,
+    {0x1F15DA3C, 0x37FF, 0x4070, 0xB4, 0x71, 0xBB, 0x4A, 0xF1, 0x2A, 0x72, 0x4A}
+  },
+  { // UEFI Variable Services non-volatile storage
+    ARM_VE_SMB_NOR1_BASE + SIZE_256KB * 255,
+    SIZE_64KB * 3, //FIXME: Set 3 blocks because I did not succeed to copy 4 blocks into the ARM Versastile Express NOR Falsh in the last NOR Flash. It should be 4 blocks
+    SIZE_64KB,
+    TRUE,
+    {0xCC2CBF29, 0x1498, 0x4CDD, 0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, 0x09, 0x09}
+  }
+};
+
+NOR_FLASH_INSTANCE *mNorFlashInstances[ NOR_FLASH_LAST_DEVICE ];
+
+NOR_FLASH_INSTANCE  mNorFlashInstanceTemplate = {
+  NOR_FLASH_SIGNATURE, // Signature
+  NULL, // Handle ... NEED TO BE FILLED
+
+  FALSE, // Initialized
+  NULL, // Initialize
+
+  0, // BaseAddress ... NEED TO BE FILLED
+  0, // Size ... NEED TO BE FILLED
+
+  {\r
+    EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision\r
+    NULL, // Media ... NEED TO BE FILLED\r
+    NorFlashBlockIoReset, // Reset;\r
+    NorFlashBlockIoReadBlocks,          // ReadBlocks
+    NorFlashBlockIoWriteBlocks,         // WriteBlocks
+    NorFlashBlockIoFlushBlocks          // FlushBlocks\r
+  }, // BlockIoProtocol
+
+  {\r
+    0, // MediaId ... NEED TO BE FILLED\r
+    FALSE, // RemovableMedia\r
+    TRUE, // MediaPresent\r
+    FALSE, // LogicalPartition\r
+    FALSE, // ReadOnly\r
+    FALSE, // WriteCaching;\r
+    0, // BlockSize ... NEED TO BE FILLED\r
+    4, //  IoAlign\r
+    0, // LastBlock ... NEED TO BE FILLED\r
+    0, // LowestAlignedLba\r
+    1, // LogicalBlocksPerPhysicalBlock\r
+  }, //Media;
+
+  FALSE, // SupportFvb ... NEED TO BE FILLED
+  {\r
+    FvbGetAttributes, // GetAttributes
+    FvbSetAttributes, // SetAttributes
+    FvbGetPhysicalAddress,  // GetPhysicalAddress
+    FvbGetBlockSize,  // GetBlockSize
+    FvbRead,  // Read
+    FvbWrite, // Write
+    FvbEraseBlocks, // EraseBlocks\r
+    NULL, //ParentHandle\r
+  }, //  FvbProtoccol;
+
+  {
+    {
+      {
+        HARDWARE_DEVICE_PATH,
+        HW_VENDOR_DP,
+        (UINT8)( sizeof(VENDOR_DEVICE_PATH)      ),
+        (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8),
+      },
+      { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, // GUID ... NEED TO BE FILLED
+    },
+    {
+      END_DEVICE_PATH_TYPE,
+      END_ENTIRE_DEVICE_PATH_SUBTYPE,
+      sizeof (EFI_DEVICE_PATH_PROTOCOL),
+      0
+    }
+    } // DevicePath
+};
+
+EFI_STATUS NorFlashCreateInstance(
+    IN UINTN NorFlashBase,
+    IN UINTN NorFlashSize,
+    IN UINT32 MediaId,
+    IN UINT32  BlockSize,
+    IN BOOLEAN SupportFvb,
+    IN CONST GUID  *NorFlashGuid,
+    OUT NOR_FLASH_INSTANCE** NorFlashInstance
+  ) {
+  EFI_STATUS Status;
+  NOR_FLASH_INSTANCE* Instance;
+
+  ASSERT(NorFlashInstance != NULL);
+
+  Instance = AllocateCopyPool (sizeof(NOR_FLASH_INSTANCE),&mNorFlashInstanceTemplate);
+  if (Instance == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Instance->BaseAddress = NorFlashBase;
+  Instance->Size = NorFlashSize;
+
+  Instance->BlockIoProtocol.Media = &Instance->Media;
+  Instance->Media.MediaId = MediaId;
+  Instance->Media.BlockSize = BlockSize;
+  Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1;
+\r
+  CopyGuid (&Instance->DevicePath.Vendor.Guid,NorFlashGuid);\r
+
+  if (SupportFvb) {
+    Instance->SupportFvb = TRUE;
+    Instance->Initialize = NorFlashFvbInitialize;
+
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Instance->Handle,
+                  &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+                  //&gEfiBlockIoProtocolGuid,  &Instance->BlockIoProtocol,
+                  &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol,
+                  NULL
+                  );
+    if (EFI_ERROR(Status)) {
+      FreePool(Instance);
+      return Status;
+    }
+  } else {
+    Instance->Initialize = NorFlashBlkIoInitialize;
+
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Instance->Handle,
+                    &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+                    &gEfiBlockIoProtocolGuid,  &Instance->BlockIoProtocol,
+                    NULL
+                    );
+    if (EFI_ERROR(Status)) {
+      FreePool(Instance);
+      return Status;
+    }
+  }
+\r
+  *NorFlashInstance = Instance;\r
+  return Status;\r
+}
+
+EFI_STATUS
+NorFlashReadCfiData (
+  IN UINTN   BaseAddress,
+  IN UINTN   CFI_Offset,
+  IN UINT32  NumberOfBytes,
+  OUT UINT32 *Data
+)
+{
+  UINT32          CurrentByte;
+  volatile UINTN  *ReadAddress;
+  UINT32          ReadData;
+  UINT32          Byte1;
+  UINT32          Byte2;
+  UINT32          CombinedData = 0;
+  EFI_STATUS      Status = EFI_SUCCESS;
+
+
+  if( NumberOfBytes > 4 ) {
+    // Using 32 bit variable so can only read 4 bytes
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // First combine the base address with the offset address
+  // to create an absolute read address.
+  // However, because we are in little endian, read from the last address down to the first
+  ReadAddress = CREATE_NOR_ADDRESS( BaseAddress, CFI_Offset ) + NumberOfBytes - 1;
+
+  // Although each read returns 32 bits, because of the NOR Flash structure,
+  // each 16 bits (16 MSB and 16 LSB) come from two different chips.
+  // When in CFI mode, each chip read returns valid data in only the 8 LSBits;
+  // the 8 MSBits are invalid and can be ignored.
+  // Therefore, each read address returns one byte from each chip.
+  //
+  // Also note: As we are in little endian notation and we are reading
+  // bytes from incremental addresses, we should assemble them in little endian order.
+  for( CurrentByte=0; CurrentByte<NumberOfBytes; CurrentByte++  ) {
+
+    // Read the bytes from the two chips
+    ReadData = *ReadAddress;
+
+    // Check the data validity:
+    // The 'Dual Data' function means that
+    // each chip should return identical data.
+    // If that is not the case then we have a problem.
+    Byte1 = GET_LOW_BYTE ( ReadData );
+    Byte2 = GET_HIGH_BYTE( ReadData );
+
+    if( Byte1 != Byte2 ) {
+      // The two bytes should have been identical
+      return EFI_DEVICE_ERROR;
+    } else {
+
+      // Each successive iteration of the 'for' loop reads a lower address.
+      // As we read lower addresses and as we use little endian,
+      // we read lower significance bytes. So combine them in the correct order.
+      CombinedData = (CombinedData << 8) | Byte1;
+
+      // Decrement down to the next address
+      ReadAddress--;
+    }
+  }
+
+  *Data = CombinedData;
+
+  return Status;
+}
+
+EFI_STATUS
+NorFlashReadStatusRegister(
+  IN UINTN SR_Address
+  )
+{
+  volatile UINT32       *pStatusRegister;
+  UINT32                StatusRegister;
+  UINT32                ErrorMask;
+  EFI_STATUS            Status = EFI_SUCCESS;
+
+  // Prepare the read address
+  pStatusRegister = (UINT32 *) SR_Address;
+
+  do {
+    // Prepare to read the status register
+    SEND_NOR_COMMAND( SR_Address, 0, P30_CMD_READ_STATUS_REGISTER );
+    // Snapshot the status register
+    StatusRegister = *pStatusRegister;
+  }
+  // The chip is busy while the WRITE bit is not asserted
+  while ( (StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE );
+
+
+  // Perform a full status check:
+  // Mask the relevant bits of Status Register.
+  // Everything should be zero, if not, we have a problem
+
+  // Prepare the Error Mask by setting bits 5, 4, 3, 1
+  ErrorMask = P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM | P30_SR_BIT_VPP | P30_SR_BIT_BLOCK_LOCKED ;
+
+  if ( (StatusRegister & ErrorMask) != 0 ) {
+    if ( (StatusRegister & P30_SR_BIT_VPP) != 0 ) {
+      DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: VPP Range Error\n"));
+    } else if ( (StatusRegister & (P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM) ) != 0 ) {
+      DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: Command Sequence Error\n"));
+    } else if ( (StatusRegister & P30_SR_BIT_PROGRAM) != 0 ) {
+      DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: Program Error\n"));
+    } else if ( (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) != 0 ) {
+      DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: Device Protect Error\n"));
+    } else {\r
+      DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: Error (0x%X)\n",Status));\r
+    }
+
+    // If an error is detected we must clear the Status Register
+    SEND_NOR_COMMAND( SR_Address, 0, P30_CMD_CLEAR_STATUS_REGISTER );
+    Status = EFI_DEVICE_ERROR;
+  }
+
+  SEND_NOR_COMMAND( SR_Address, 0, P30_CMD_READ_ARRAY );
+
+  return Status;
+}
+
+
+BOOLEAN
+NorFlashBlockIsLocked(
+  IN UINTN BlockAddress
+  )
+{
+  volatile UINT32       *pReadData;
+  UINT32                LockStatus;
+  BOOLEAN               BlockIsLocked = TRUE;
+
+  // Prepare the read address
+  pReadData = (UINT32 *) CREATE_NOR_ADDRESS( BlockAddress, 2 );
+
+  // Send command for reading device id
+  SEND_NOR_COMMAND( BlockAddress, 2, P30_CMD_READ_DEVICE_ID );
+
+  // Read block lock status
+  LockStatus = *pReadData;
+
+  // Decode block lock status
+  LockStatus = FOLD_32BIT_INTO_16BIT(LockStatus);
+
+  if( (LockStatus & 0x2) != 0 ) {
+    DEBUG((EFI_D_ERROR, "UnlockSingleBlock: WARNING: Block LOCKED DOWN\n"));
+  }
+
+  if( (LockStatus & 0x1) == 0 ) {
+    // This means the block is unlocked
+    DEBUG((DEBUG_BLKIO, "UnlockSingleBlock: Block 0x%08x unlocked\n", BlockAddress ));
+    BlockIsLocked = FALSE;
+  }
+
+  return BlockIsLocked;
+}
+
+
+EFI_STATUS
+NorFlashUnlockSingleBlock(
+  IN UINTN  BlockAddress
+  )
+{
+  EFI_STATUS            Status = EFI_SUCCESS;
+
+  // Raise the Task Priority Level to TPL_NOTIFY to serialise all its operations
+  // and to protect shared data structures.
+
+  //while( NorFlashBlockIsLocked( BlockAddress ) )
+  {
+    // Request a lock setup
+    SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_LOCK_BLOCK_SETUP );
+
+    // Request an unlock
+    SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_UNLOCK_BLOCK );
+  }
+
+  // Put device back into Read Array mode
+  SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_READ_ARRAY );
+
+  DEBUG((DEBUG_BLKIO, "UnlockSingleBlock: BlockAddress=0x%08x, Exit Status = \"%r\".\n", BlockAddress, Status));
+
+  return Status;
+}
+
+
+EFI_STATUS
+NorFlashUnlockSingleBlockIfNecessary(
+  IN UINTN BlockAddress
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+
+  if ( NorFlashBlockIsLocked( BlockAddress ) == TRUE ) {
+    Status = NorFlashUnlockSingleBlock( BlockAddress );
+  }
+
+  return Status;
+}
+
+
+/**
+ * The following function presumes that the block has already been unlocked.
+ **/
+EFI_STATUS
+NorFlashEraseSingleBlock(
+  IN UINTN BlockAddress
+  )
+{
+  EFI_STATUS            Status = EFI_SUCCESS;
+
+  // Request a block erase and then confirm it
+  SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_BLOCK_ERASE_SETUP );
+  SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_BLOCK_ERASE_CONFIRM );
+  // Wait until the status register gives us the all clear
+  Status = NorFlashReadStatusRegister( BlockAddress );
+
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_BLKIO, "EraseSingleBlock(BlockAddress=0x%08x) = '%r'\n", BlockAddress, Status));
+  }
+  return Status;
+}
+
+/**
+ * The following function presumes that the block has already been unlocked.
+ **/
+EFI_STATUS
+NorFlashUnlockAndEraseSingleBlock(
+  IN  UINTN   BlockAddress
+  )
+{
+  EFI_STATUS   Status;
+
+  // Unlock the block if we have to
+  Status = NorFlashUnlockSingleBlockIfNecessary( BlockAddress );
+  if (!EFI_ERROR(Status)) {
+    Status = NorFlashEraseSingleBlock( BlockAddress );
+  }
+
+  return Status;
+}
+
+
+EFI_STATUS
+NorFlashWriteSingleWord (
+    IN  UINTN   WordAddress,
+    IN  UINT32  WriteData
+  )
+{
+  EFI_STATUS            Status;
+  volatile UINT32       *Data;
+
+  // Prepare the read address
+  Data = (UINT32 *)WordAddress;
+
+  // Request a write single word command
+  SEND_NOR_COMMAND( WordAddress, 0, P30_CMD_WORD_PROGRAM_SETUP );
+
+  // Store the word into NOR Flash;
+  *Data = WriteData;
+
+  // Wait for the write to complete and then check for any errors; i.e. check the Status Register
+  Status = NorFlashReadStatusRegister( WordAddress );
+
+  return Status;
+}
+
+/*
+ * Writes data to the NOR Flash using the Buffered Programming method.
+ *
+ * The maximum size of the on-chip buffer is 32-words, because of hardware restrictions.
+ * Therefore this function will only handle buffers up to 32 words or 128 bytes.
+ * To deal with larger buffers, call this function again.
+ *
+ * This function presumes that both the TargetAddress and the TargetAddress+BufferSize
+ * exist entirely within the NOR Flash. Therefore these conditions will not be checked here.
+ *
+ * In buffered programming, if the target address not at the beginning of a 32-bit word boundary,
+ * then programming time is doubled and power consumption is increased.
+ * Therefore, it is a requirement to align buffer writes to 32-bit word boundaries.
+ * i.e. the last 4 bits of the target start address must be zero: 0x......00
+ */
+EFI_STATUS
+NorFlashWriteBuffer (
+    IN  UINTN   TargetAddress,
+    IN  UINTN   BufferSizeInBytes,
+    IN  UINT32  *Buffer
+  )
+{
+  EFI_STATUS            Status;
+  UINTN                 BufferSizeInWords;
+  UINTN                 Count;
+  volatile UINT32       *Data;
+  UINTN                 WaitForBuffer   = MAX_BUFFERED_PROG_ITERATIONS;
+  BOOLEAN               BufferAvailable = FALSE;
+
+
+  // Check that the target address does not cross a 32-word boundary.
+  if ( (TargetAddress & BOUNDARY_OF_32_WORDS) != 0 ) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Check there are some data to program
+  if ( BufferSizeInBytes == 0 ) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+
+  // Check that the buffer size does not exceed the maximum hardware buffer size on chip.
+  if ( BufferSizeInBytes > P30_MAX_BUFFER_SIZE_IN_BYTES ) {
+    return EFI_BAD_BUFFER_SIZE;
+  }
+
+  // Check that the buffer size is a multiple of 32-bit words
+  if ( (BufferSizeInBytes % 4) != 0 ) {
+    return EFI_BAD_BUFFER_SIZE;
+  }
+
+  // Pre-programming conditions checked, now start the algorithm.
+
+  // Prepare the data destination address
+  Data = (UINT32 *)TargetAddress;
+
+  // Check the availability of the buffer
+  do {
+    // Issue the Buffered Program Setup command
+    SEND_NOR_COMMAND( TargetAddress, 0, P30_CMD_BUFFERED_PROGRAM_SETUP );
+
+    // Read back the status register bit#7 from the same address
+    if ( ((*Data) & P30_SR_BIT_WRITE) == P30_SR_BIT_WRITE ) {
+      BufferAvailable = TRUE;
+    }
+
+    // Update the loop counter
+    WaitForBuffer--;
+
+  } while (( WaitForBuffer > 0 ) && ( BufferAvailable == FALSE ));
+
+  // The buffer was not available for writing
+  if ( WaitForBuffer == 0 ) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  // From now on we work in 32-bit words
+  BufferSizeInWords = BufferSizeInBytes / (UINTN)4;
+
+  // Write the word count, which is (buffer_si