--- /dev/null
+#/** @file
+# Arm Versatile Express package.
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = ArmPlatformPkg
+ PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
+[Guids.common]
+ gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
+
+[PcdsFeatureFlag.common]
+ gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE|BOOLEAN|0x00000001
+
+[PcdsFixedAtBuild.common]
+ # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
+ # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
+ gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000002
+
+ gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0|UINT32|0x00000003
+
+ # Stack for CPU Cores in Secure Mode
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000004
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000005
+
+ # Stack for CPU Cores in Secure Monitor Mode
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000006
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0|UINT32|0x00000007
+
+ # Stack for CPU Cores in Non Secure Mode
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0|UINT32|0x00000008
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0|UINT32|0x00000009
--- /dev/null
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = ArmRealViewEbPkg\r
+ PLATFORM_GUID = F4C1AD3E-9D3E-4F61-8791-B3BB1C43D04C\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/ArmRealViewEb-RTSM-A8\r
+ SUPPORTED_ARCHITECTURES = ARM\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf\r
+\r
+[LibraryClasses.common]\r
+!if $(BUILD_TARGETS) == RELEASE\r
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf\r
+!else\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf\r
+# UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf\r
+!endif\r
+\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf\r
+ \r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf\r
+\r
+ EfiResetSystemLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.inf\r
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ \r
+ EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf\r
+ EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ \r
+ #\r
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window \r
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this\r
+ # into the command window to load symbols. We should be able to use a script to do this, but\r
+ # the version of RVD I have does not support scripts accessing system memory.\r
+ #\r
+# PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf\r
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf\r
+# PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+ \r
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf\r
+ DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf\r
+ \r
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf\r
+ \r
+ RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf\r
+\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+ \r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ \r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf\r
+\r
+#\r
+# Assume everything is fixed at build\r
+#\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+\r
+ EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf\r
+\r
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+\r
+ EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf\r
+ \r
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+ DebugAgentTimerLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf\r
+\r
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf\r
+ TimerLib|ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf \r
+ GdbSerialLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.inf\r
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
+ \r
+ BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf\r
+\r
+[LibraryClasses.common.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf\r
+ \r
+ # 1/123 faster than Stm or Vstm version\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+\r
+ # Uncomment to turn on GDB stub in SEC. \r
+ #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf\r
+ \r
+ # L2 Cache Driver\r
+ L2X0CacheLib|ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf\r
+ # ARM PL390 General Interrupt Driver in Secure and Non-secure\r
+ PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf\r
+\r
+[LibraryClasses.common.PEI_CORE]\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ # note: this won't actually work since globals in PEI are not writeable\r
+ # need to generate an ARM PEI services table pointer implementation\r
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.PEIM]\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ # note: this won't actually work since globals in PEI are not writeable\r
+ # need to generate an ARM PEI services table pointer implementation\r
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.DXE_CORE]\r
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+\r
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf\r
+ \r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+\r
+\r
+[LibraryClasses.common.UEFI_APPLICATION]\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+\r
+[LibraryClasses.common.UEFI_DRIVER]\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+\r
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+# PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+\r
+[LibraryClasses.ARM]\r
+ #\r
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.\r
+ # This library provides the instrinsic functions generate by a given compiler.\r
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.\r
+ #\r
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r
+\r
+[BuildOptions]\r
+ RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8 --thumb --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+ RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+\r
+ GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform \r
+ GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+\r
+ XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+ XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+ XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+ XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag.common]\r
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE\r
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE\r
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE\r
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE\r
+ \r
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE\r
+ \r
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress\r
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE\r
+ \r
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE\r
+ \r
+ gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE\r
+\r
+!if $(EDK2_SKIP_PEICORE) == 1\r
+ gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE\r
+!endif\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmRealViewEb %a"\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF\r
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1\r
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0\r
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320\r
+\r
+# DEBUG_ASSERT_ENABLED 0x01\r
+# DEBUG_PRINT_ENABLED 0x02\r
+# DEBUG_CODE_ENABLED 0x04\r
+# CLEAR_MEMORY_ENABLED 0x08\r
+# ASSERT_BREAKPOINT_ENABLED 0x10\r
+# ASSERT_DEADLOOP_ENABLED 0x20\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f\r
+\r
+# DEBUG_INIT 0x00000001 // Initialization\r
+# DEBUG_WARN 0x00000002 // Warnings\r
+# DEBUG_LOAD 0x00000004 // Load events\r
+# DEBUG_FS 0x00000008 // EFI File system\r
+# DEBUG_POOL 0x00000010 // Alloc & Free's\r
+# DEBUG_PAGE 0x00000020 // Alloc & Free's\r
+# DEBUG_INFO 0x00000040 // Verbose\r
+# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers\r
+# DEBUG_VARIABLE 0x00000100 // Variable\r
+# DEBUG_BM 0x00000400 // Boot Manager\r
+# DEBUG_BLKIO 0x00001000 // BlkIo Driver\r
+# DEBUG_NET 0x00004000 // SNI Driver\r
+# DEBUG_UNDI 0x00010000 // UNDI Driver\r
+# DEBUG_LOADFILE 0x00020000 // UNDI Driver\r
+# DEBUG_EVENT 0x00080000 // Event messages\r
+# DEBUG_ERROR 0x80000000 // Error\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
+\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000\r
+ \r
+#\r
+# Optional feature to help prevent EFI memory map fragments\r
+# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob\r
+# Values are in EFI Pages (4K). DXE Core will make sure that \r
+# at least this much of each type of memory can be allocated \r
+# from a single memory range. This way you only end up with\r
+# maximum of two fragements for each type in the memory map\r
+# (the memory used, and the free memory that was prereserved\r
+# but not used).\r
+#\r
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000\r
+ \r
+ # Stack for CPU Cores in Secure Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000 # Top of SEC Stack for Secure World\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Size of SEC Stack for Secure World\r
+\r
+ # Stack for CPU Cores in Secure Monitor Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x4A000000 # Top of SEC Stack for Monitor World\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x2000 # Size of SEC Stack for Monitor World\r
+\r
+ # Stack for CPU Cores in Non Secure Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Size of SEC Stack for Normal World\r
+ gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # Pei Services Ptr just above stack\r
+\r
+ # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
+ \r
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms\r
+ \r
+ #\r
+ # ARM Pcds\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000\r
+ \r
+ #\r
+ # ARM EB PCDS\r
+ #\r
+ gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase|0x1000a000\r
+ \r
+ #\r
+ # ARM PL390 General Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x10041000\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x10040000\r
+\r
+ #\r
+ # ARM OS Loader\r
+ #\r
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: \r
+ gArmTokenSpaceGuid.PcdArmMachineType|2272\r
+ gArmTokenSpaceGuid.PcdLinuxKernelDP|L"VenHw(02118005-9DA7-443a-92D5-781F022AEDBB)/MemoryMapped(0,0x46000000,0x46400000)"\r
+ gArmTokenSpaceGuid.PcdLinuxAtag|"rdinit=/bin/ash debug earlyprintk console=ttyAMA0,38400 mem=1G"\r
+ gArmTokenSpaceGuid.PcdFdtDP|L""\r
+ \r
+ #\r
+ # ARM L2x0 PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1F002000\r
+ \r
+\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform\r
+#\r
+################################################################################\r
+[Components.common]\r
+ \r
+#\r
+# SEC\r
+#\r
+ ArmPlatformPkg/Sec/Sec.inf\r
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf\r
+ \r
+#\r
+# PEI Phase modules\r
+#\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ ArmPlatformPkg/PlatformPei/PlatformPei.inf\r
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf\r
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+ Nt32Pkg/BootModePei/BootModePei.inf\r
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+\r
+#\r
+# DXE\r
+#\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
+ }\r
+\r
+ #\r
+ # Architectural Protocols\r
+ #\r
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf \r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf \r
+ \r
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+ \r
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf\r
+\r
+ ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf\r
+ ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf\r
+ ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
+\r
+ #\r
+ # Semi-hosting filesystem\r
+ #\r
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+ \r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ FatPkg/EnhancedFatDxe/Fat.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+ \r
+ \r
+ #\r
+ # Application\r
+ # \r
+ EmbeddedPkg/Ebl/Ebl.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ ArmPlatformPkg/Bds/Bds.inf\r
--- /dev/null
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmRealViewEb-RTSM-A9x2
+ PLATFORM_GUID = f6c2f4a0-2027-11e0-a2a1-0002a5d5c51b
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/ArmRealViewEb-RTSM-A9x2
+ SUPPORTED_ARCHITECTURES = ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf
+
+[LibraryClasses.common]
+!if $(BUILD_TARGETS) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+# UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+!endif
+
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
+ ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
+ ArmMPCoreMailBoxLib|ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBoxLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
+
+ EfiResetSystemLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ResetSystemLib/ResetSystemLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+
+ EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf
+ EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+# PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+# PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+
+ RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+
+#
+# Assume everything is fixed at build
+#
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
+
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+ EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
+
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+ TimerLib|ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf
+ GdbSerialLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+
+ BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf
+
+ # 1/123 faster than Stm or Vstm version
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+ # Uncomment to turn on GDB stub in SEC.
+ #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+
+ # L2 Cache Driver
+ L2X0CacheLib|ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
+ # ARM PL390 General Interrupt Driver in Secure and Non-secure
+ PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
+ PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+
+[LibraryClasses.common.PEI_CORE]
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ # note: this won't actually work since globals in PEI are not writeable
+ # need to generate an ARM PEI services table pointer implementation
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.PEIM]
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ # note: this won't actually work since globals in PEI are not writeable
+ # need to generate an ARM PEI services table pointer implementation
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+# PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[BuildOptions]
+ RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A9 --thumb --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+ RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A9 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+
+ GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+ GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+
+ XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+ XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+ XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+ XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+ gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE
+!endif
+
+[PcdsFixedAtBuild.common]
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmRealViewEb %a"
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+# DEBUG_ASSERT_ENABLED 0x01
+# DEBUG_PRINT_ENABLED 0x02
+# DEBUG_CODE_ENABLED 0x04
+# CLEAR_MEMORY_ENABLED 0x08
+# ASSERT_BREAKPOINT_ENABLED 0x10
+# ASSERT_DEADLOOP_ENABLED 0x20
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+
+# DEBUG_INIT 0x00000001 // Initialization
+# DEBUG_WARN 0x00000002 // Warnings
+# DEBUG_LOAD 0x00000004 // Load events
+# DEBUG_FS 0x00000008 // EFI File system
+# DEBUG_POOL 0x00000010 // Alloc & Free's
+# DEBUG_PAGE 0x00000020 // Alloc & Free's
+# DEBUG_INFO 0x00000040 // Verbose
+# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+# DEBUG_VARIABLE 0x00000100 // Variable
+# DEBUG_BM 0x00000400 // Boot Manager
+# DEBUG_BLKIO 0x00001000 // BlkIo Driver
+# DEBUG_NET 0x00004000 // SNI Driver
+# DEBUG_UNDI 0x00010000 // UNDI Driver
+# DEBUG_LOADFILE 0x00020000 // UNDI Driver
+# DEBUG_EVENT 0x00080000 // Event messages
+# DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+#
+# Optional feature to help prevent EFI memory map fragments
+# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+# Values are in EFI Pages (4K). DXE Core will make sure that
+# at least this much of each type of memory can be allocated
+# from a single memory range. This way you only end up with
+# maximum of two fragements for each type in the memory map
+# (the memory used, and the free memory that was prereserved
+# but not used).
+#
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000
+
+ gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
+
+ # Stacks for MPCores in Secure World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000 # Top of SEC Stack for Secure World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Stack for each of the 4 CPU cores
+
+ # Stacks for MPCores in Monitor Mode
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x4A000000 # Top of SEC Stack for Monitor World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x2000 # Stack for each of the 4 CPU cores
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Stack for each of the 4 CPU cores
+ gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # Pei Services Ptr just above stack
+
+ # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+
+ #
+ # ARM Pcds
+ #
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+ #
+ # ARM EB PCDS
+ #
+ gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase|0x1000a000
+
+ #
+ # ARM PL390 General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x10041000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x10040000
+
+ #
+ # ARM OS Loader
+ #
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+ gArmTokenSpaceGuid.PcdArmMachineType|2272
+ gArmTokenSpaceGuid.PcdLinuxKernelDP|L"VenHw(02118005-9DA7-443a-92D5-781F022AEDBB)/MemoryMapped(0,0x46000000,0x46400000)"
+ gArmTokenSpaceGuid.PcdLinuxAtag|"rdinit=/bin/ash debug earlyprintk console=ttyAMA0,38400 mem=1G"
+ gArmTokenSpaceGuid.PcdFdtDP|L""
+
+ #
+ # ARM L2x0 PCDs
+ #
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1F002000
+
+ #
+ # ARM VE MP Core Mailbox
+ #
+ gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0x10000030
+ gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0x10000030
+ gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0x10000034
+ gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0xFFFFFFFF
+
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+#
+# SEC
+#
+ ArmPlatformPkg/Sec/Sec.inf
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+
+#
+# PEI Phase modules
+#
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPei.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ Nt32Pkg/BootModePei/BootModePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+#
+# DXE
+#
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf
+ ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf
+ ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+
+ #
+ # Application
+ #
+ EmbeddedPkg/Ebl/Ebl.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ ArmPlatformPkg/Bds/Bds.inf
--- /dev/null
+# FLASH layout file for ARM VE.
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+
+[FD.ArmRealViewEb_EFI]
+BaseAddress = 0x40000000 # The base address of the FLASH Device.
+Size = 0x00200000 # The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x00010000
+NumBlocks = 0x20
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00050000
+gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize
+FV = FVMAIN_SEC
+
+0x00050000|0x00100000
+gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+0x00150000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x20000
+ 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ #Signature "_FVH" #Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
+ #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ #Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ #Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ #Size: 0xc000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xBFB8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xBF, 0x00, 0x00,
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ INF ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf
+ INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF EmbeddedPkg/Ebl/Ebl.inf
+
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF ArmPlatformPkg/Bds/Bds.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional |.depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 |.efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 8 |.efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE |.efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ TE TE |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 |.efi
+ }
--- /dev/null
+# FLASH layout file for ARM RealView EB.\r
+#\r
+# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+\r
+\r
+[FD.ArmRealViewEb_EFI]\r
+BaseAddress = 0x40000000 # The base address of the FLASH Device.\r
+Size = 0x00200000 # The size in bytes of the FLASH Device\r
+ErasePolarity = 1\r
+BlockSize = 0x00010000\r
+NumBlocks = 0x20\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+\r
+0x00000000|0x00050000\r
+gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize\r
+FV = FVMAIN_SEC\r
+\r
+0x00050000|0x00100000\r
+gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
+FV = FVMAIN_COMPACT\r
+\r
+0x00150000|0x00010000\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+#NV_VARIABLE_STORE\r
+DATA = {\r
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER\r
+ # ZeroVector []\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =\r
+ # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}\r
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,\r
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,\r
+ # FvLength: 0x20000\r
+ 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ #Signature "_FVH" #Attributes\r
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,\r
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision\r
+ 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,\r
+ #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block\r
+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,\r
+ #Blockmap[1]: End\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ ## This is the VARIABLE_STORE_HEADER\r
+ #Signature: gEfiVariableGuid =\r
+ # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}\r
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,\r
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,\r
+ #Size: 0xc000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xBFB8\r
+ # This can speed up the Variable Dispatch a bit.\r
+ 0xB8, 0xBF, 0x00, 0x00,\r
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32\r
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
+}\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+\r
+[FV.FVMAIN_SEC]\r
+FvAlignment = 8\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF ArmPlatformPkg/Sec/Sec.inf\r
+\r
+\r
+[FV.FvMain]\r
+BlockSize = 0x40\r
+NumBlocks = 0 # This FV gets compressed so make it just big enough\r
+FvAlignment = 8 # FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf \r
+\r
+ #\r
+ # PI DXE Drivers producing Architectural Protocols (EFI Services) \r
+ #\r
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf\r
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+ \r
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf\r
+ \r
+ INF ArmPlatformPkg/ArmRealViewEbPkg/InterruptDxe/InterruptDxe.inf\r
+ INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
+\r
+ #\r
+ # Semi-hosting filesystem\r
+ #\r
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+ \r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ INF FatPkg/EnhancedFatDxe/Fat.inf\r
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # UEFI application (Shell Embedded Boot Loader) \r
+ # \r
+ INF EmbeddedPkg/Ebl/Ebl.inf\r
+ \r
+\r
+ #\r
+ # Bds\r
+ #\r
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ INF ArmPlatformPkg/Bds/Bds.inf\r
+\r
+\r
+[FV.FVMAIN_COMPACT]\r
+FvAlignment = 8\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf\r
+ INF MdeModulePkg/Core/Pei/PeiMain.inf\r
+ INF ArmPlatformPkg/PlatformPei/PlatformPei.inf\r
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf\r
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+ \r
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
+ SECTION FV_IMAGE = FVMAIN\r
+ }\r
+ }\r
+\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+\r
+############################################################################\r
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # \r
+############################################################################\r
+#\r
+#[Rule.Common.DXE_DRIVER]\r
+# FILE DRIVER = $(NAMED_GUID) {\r
+# DXE_DEPEX DXE_DEPEX Optional |.depex\r
+# COMPRESS PI_STD {\r
+# GUIDED {\r
+# PE32 PE32 |.efi\r
+# UI STRING="$(MODULE_NAME)" Optional\r
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+# }\r
+# }\r
+# }\r
+#\r
+############################################################################\r
+\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 8 |.efi\r
+ }\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ TE TE |.efi\r
+ UI STRING ="$(MODULE_NAME)" Optional \r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional |.depex\r
+ TE TE |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional \r
+ }\r
+\r
+[Rule.Common.PEIM.TIANOCOMPRESSED]\r
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
+ PEI_DEPEX PEI_DEPEX Optional |.depex\r
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ UI STRING ="$(MODULE_NAME)" Optional \r
+ PE32 PE32 |.efi\r
+ }\r
--- /dev/null
+#/** @file
+# Arm RealView EB package.
+#
+# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = ArmRealViewEbPkg
+ PACKAGE_GUID = 44577A0D-361A-45B2-B33D-BB9EE60D5A4F
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
+[Guids.common]
+ gArmRealViewEbPkgTokenSpaceGuid = { 0x44577A0D, 0x361A, 0x45B2, { 0xb3, 0x3d, 0xbb, 0x9e, 0xe6, 0x0d, 0x5a, 0x4f} }
+
+[PcdsFeatureFlag.common]
+
+[PcdsFixedAtBuild.common]
+ gArmRealViewEbPkgTokenSpaceGuid.PcdPeiServicePtrAddr|0|UINT32|0x00000003
--- /dev/null
+// returns the base address of the SEC FV in flash on the EB board\r
+// change this address for where your platform's SEC FV is located\r
+// (or make it more intelligent to search for it)\r
+define /r FindFv()\r
+{\r
+ return 0x40000000;\r
+}\r
+.\r
+\r
+include /s 'ZZZZZZ/EfiFuncs.inc'\r
+error=continue\r
+unload ,all\r
+error=abort\r
+LoadPeiSec()\r
+include C:\loadfiles.inc\r
+\r
--- /dev/null
+error=abort\r
+\r
+// NOTE: THIS MAY NEED TO BE ADJUSTED\r
+// change to reflect the total amount of ram in your system\r
+define /r GetMaxMem()\r
+{\r
+ return 0x10000000; // 256 MB\r
+}\r
+.\r
+\r
+define /r GetWord(Addr)\r
+{\r
+ unsigned long data;\r
+ \r
+ if( (Addr & 0x2) == 0 )\r
+ {\r
+ data = dword(Addr);\r
+ data = data & 0xffff;\r
+ //$printf "getword data is %x\n", data$;\r
+ return data;\r
+ }\r
+ else\r
+ {\r
+ data = dword(Addr & 0xfffffffc);\r
+ //data = data >> 16;\r
+ data = data / 0x10000;\r
+ //$printf "getword data is %x (1)\n", data$;\r
+ return data;\r
+ }\r
+}\r
+.\r
+\r
+define /r ProcessPE32(imgstart)\r
+unsigned long imgstart;\r
+{\r
+ unsigned long filehdrstart;\r
+ unsigned long debugdirentryrva;\r
+ unsigned long debugtype;\r
+ unsigned long debugrva;\r
+ unsigned long dwarfsig;\r
+ unsigned long baseofcode;\r
+ unsigned long baseofdata;\r
+ unsigned long elfbase;\r
+ char *elfpath;\r
+\r
+ $printf "PE32 image found at %x",imgstart$;\r
+\r
+ //$printf "PE file hdr offset %x",dword(imgstart+0x3C)$;\r
+\r
+ // offset from dos hdr to PE file hdr\r
+ filehdrstart = imgstart + dword(imgstart+0x3C);\r
+\r
+ // offset to debug dir in PE hdrs\r
+ //$printf "debug dir is at %x",(filehdrstart+0xA8)$;\r
+ debugdirentryrva = dword(filehdrstart + 0xA8);\r
+ if(debugdirentryrva == 0)\r
+ {\r
+ $printf "no debug dir for image at %x",imgstart$;\r
+ return;\r
+ }\r
+\r
+ //$printf "debug dir entry rva is %x",debugdirentryrva$;\r
+\r
+ debugtype = dword(imgstart + debugdirentryrva + 0xc);\r
+ if( (debugtype != 0xdf) && (debugtype != 0x2) )\r
+ {\r
+ $printf "debug type is not dwarf for image at %x",imgstart$;\r
+ $printf "debug type is %x",debugtype$;\r
+ return;\r
+ }\r
+ \r
+ debugrva = dword(imgstart + debugdirentryrva + 0x14);\r
+ dwarfsig = dword(imgstart + debugrva);\r
+ if(dwarfsig != 0x66727764)\r
+ {\r
+ $printf "dwarf debug signature not found for image at %x",imgstart$;\r
+ return;\r
+ }\r
+\r
+ elfpath = (char *)(imgstart + debugrva + 0xc);\r
+\r
+ baseofcode = imgstart + dword(filehdrstart + 0x28);\r
+ baseofdata = imgstart + dword(filehdrstart + 0x2c);\r
+ \r
+ if( (baseofcode < baseofdata) && (baseofcode != 0) )\r
+ {\r
+ elfbase = baseofcode;\r
+ }\r
+ else\r
+ {\r
+ elfbase = baseofdata;\r
+ }\r
+\r
+ $printf "found path %s",elfpath$;\r
+ $fprintf 50, "load /ni /np /a %s &0x%x\n",elfpath,elfbase$;\r
+}\r
+.\r
+\r
+define /r ProcessTE(imgstart)\r
+unsigned long imgstart;\r
+{\r
+ unsigned long strippedsize;\r
+ unsigned long debugdirentryrva;\r
+ unsigned long debugtype;\r
+ unsigned long debugrva;\r
+ unsigned long dwarfsig;\r
+ unsigned long elfbase;\r
+ char *elfpath;\r
+\r
+ $printf "TE image found at %x",imgstart$;\r
+\r
+ // determine pe header bytes removed to account for in rva references\r
+ //strippedsize = word(imgstart + 0x6);\r
+ //strippedsize = (dword(imgstart + 0x4) & 0xffff0000) >> 16;\r
+ strippedsize = (dword(imgstart + 0x4) & 0xffff0000) / 0x10000;\r
+ strippedsize = strippedsize - 0x28;\r
+\r
+ debugdirentryrva = dword(imgstart + 0x20);\r
+ if(debugdirentryrva == 0)\r
+ {\r
+ $printf "no debug dir for image at %x",imgstart$;\r
+ return;\r
+ }\r
+ debugdirentryrva = debugdirentryrva - strippedsize;\r
+\r
+ //$printf "debug dir entry rva is %x",debugdirentryrva$;\r
+\r
+ debugtype = dword(imgstart + debugdirentryrva + 0xc);\r
+ if( (debugtype != 0xdf) && (debugtype != 0x2) )\r
+ {\r
+ $printf "debug type is not dwarf for image at %x",imgstart$;\r
+ $printf "debug type is %x",debugtype$;\r
+ return;\r
+ }\r
+ \r
+ debugrva = dword(imgstart + debugdirentryrva + 0x14);\r
+ debugrva = debugrva - strippedsize;\r
+ dwarfsig = dword(imgstart + debugrva);\r
+ if( (dwarfsig != 0x66727764) && (dwarfsig != 0x3031424e) )\r
+ {\r
+ $printf "dwarf debug signature not found for image at %x",imgstart$;\r
+ $printf "found %x", dwarfsig$;\r
+ return;\r
+ }\r
+ \r
+ if( dwarfsig == 0x66727764 )\r
+ {\r
+ elfpath = (char *)(imgstart + debugrva + 0xc);\r
+ $printf "looking for elf path at 0x%x", elfpath$; \r
+ }\r
+ else \r
+ {\r
+ elfpath = (char *)(imgstart + debugrva + 0x10);\r
+ $printf "looking for elf path at 0x%x", elfpath$; \r
+ }\r
+\r
+ // elf base is baseofcode (we hope that for TE images it's not baseofdata)\r
+ elfbase = imgstart + dword(imgstart + 0xc) - strippedsize;\r
+\r
+ $printf "found path %s",elfpath$;\r
+ $fprintf 50, "load /ni /np /a %s &0x%x\n",elfpath,elfbase$;\r
+}\r
+.\r
+\r
+define /r ProcessFvSection(secstart)\r
+unsigned long secstart;\r
+{\r
+ unsigned long sectionsize;\r
+ unsigned char sectiontype;\r
+\r
+ sectionsize = dword(secstart);\r
+ //sectiontype = (sectionsize & 0xff000000) >> 24;\r
+ sectiontype = (sectionsize & 0xff000000) / 0x1000000;\r
+ sectionsize = sectionsize & 0x00ffffff;\r
+\r
+ $printf "fv section at %x size %x type %x",secstart,sectionsize,sectiontype$;\r
+\r
+ if(sectiontype == 0x10) // PE32\r
+ {\r
+ ProcessPE32(secstart+0x4);\r
+ }\r
+ else if(sectiontype == 0x12) // TE\r
+ {\r
+ ProcessTE(secstart+0x4); \r
+ }\r
+}\r
+.\r
+\r
+define /r ProcessFfsFile(ffsfilestart)\r
+unsigned long ffsfilestart;\r
+{\r
+ unsigned long ffsfilesize;\r
+ unsigned long ffsfiletype;\r
+ unsigned long secoffset;\r
+ unsigned long secsize;\r
+\r
+ //ffsfiletype = byte(ffsfilestart + 0x12);\r
+ ffsfilesize = dword(ffsfilestart + 0x14);\r
+ //ffsfiletype = (ffsfilesize & 0xff000000) >> 24;\r
+ ffsfiletype = (ffsfilesize & 0xff000000) / 0x1000000;\r
+ ffsfilesize = ffsfilesize & 0x00ffffff;\r
+\r
+ if(ffsfiletype == 0xff) return;\r
+\r
+ $printf "ffs file at %x size %x type %x",ffsfilestart,ffsfilesize,ffsfiletype$;\r
+\r
+ secoffset = ffsfilestart + 0x18;\r
+\r
+ // loop through sections in file\r
+ while(secoffset < (ffsfilestart + ffsfilesize))\r
+ {\r
+ // process fv section and increment section offset by size\r
+ secsize = dword(secoffset) & 0x00ffffff;\r
+ ProcessFvSection(secoffset);\r
+ secoffset = secoffset + secsize;\r
+\r
+ // align to next 4 byte boundary\r
+ if( (secoffset & 0x3) != 0 )\r
+ {\r
+ secoffset = secoffset + (0x4 - (secoffset & 0x3));\r
+ }\r
+ } // end section loop\r
+}\r
+.\r
+\r
+define /r LoadPeiSec()\r
+{\r
+ unsigned long fvbase;\r
+ unsigned long fvlen;\r
+ unsigned long fvsig;\r
+ unsigned long ffsoffset;\r
+ unsigned long ffsfilesize;\r
+\r
+ fvbase = FindFv();\r
+ $printf "fvbase %x",fvbase$;\r
+\r
+ // get fv signature field\r
+ fvsig = dword(fvbase + 0x28);\r
+ if(fvsig != 0x4856465F)\r
+ {\r
+ $printf "FV does not have proper signature, exiting"$;\r
+ return 0;\r
+ }\r
+\r
+ $printf "FV signature found"$;\r
+\r
+ $fopen 50, 'C:\loadfiles.inc'$;\r
+\r
+ fvlen = dword(fvbase + 0x20);\r
+ \r
+ // first ffs file is after fv header, use headerlength field\r
+ //ffsoffset = (dword(fvbase + 0x30) & 0xffff0000) >> 16;\r
+ ffsoffset = (dword(fvbase + 0x30) & 0xffff0000) / 0x10000;\r
+ ffsoffset = fvbase + GetWord(fvbase + 0x30);\r
+\r
+ // loop through ffs files\r
+ while(ffsoffset < (fvbase+fvlen))\r
+ {\r
+ // process ffs file and increment by ffs file size field\r
+ ProcessFfsFile(ffsoffset); \r
+ ffsfilesize = (dword(ffsoffset + 0x14) & 0x00ffffff);\r
+ if(ffsfilesize == 0)\r
+ {\r
+ break;\r
+ }\r
+ ffsoffset = ffsoffset + ffsfilesize;\r
+ \r
+\r
+ // align to next 8 byte boundary\r
+ if( (ffsoffset & 0x7) != 0 )\r
+ {\r
+ ffsoffset = ffsoffset + (0x8 - (ffsoffset & 0x7));\r
+ }\r
+ \r
+ } // end fv ffs loop\r
+\r
+ $vclose 50$;\r
+\r
+}\r
+.\r
+\r
+define /r FindSystemTable(TopOfRam)\r
+unsigned long TopOfRam;\r
+{\r
+ unsigned long offset;\r
+ \r
+ $printf "FindSystemTable"$;\r
+ $printf "top of mem is %x",TopOfRam$;\r
+ \r
+ offset = TopOfRam;\r
+ \r
+ // align to highest 4MB boundary\r
+ offset = offset & 0xFFC00000;\r
+ \r
+ // start at top and look on 4MB boundaries for system table ptr structure\r
+ while(offset > 0)\r
+ {\r
+ //$printf "checking %x",offset$;\r
+ //$printf "value is %x",dword(offset)$;\r
+ \r
+ // low signature match\r
+ if(dword(offset) == 0x20494249)\r
+ {\r
+ // high signature match\r
+ if(dword(offset+4) == 0x54535953)\r
+ {\r
+ // less than 4GB?\r
+ if(dword(offset+0x0c) == 0)\r
+ {\r
+ // less than top of ram?\r
+ if(dword(offset+8) < TopOfRam)\r
+ {\r
+ return(dword(offset+8));\r
+ }\r
+ }\r
+ }\r
+ \r
+ }\r
+ \r
+ if(offset < 0x400000) break;\r
+ offset = offset - 0x400000; \r
+ }\r
+ \r
+ return 0;\r
+}\r
+.\r
+\r
+define /r ProcessImage(ImageBase)\r
+unsigned long ImageBase;\r
+{\r
+ $printf "ProcessImage %x", ImageBase$;\r
+}\r
+.\r
+\r
+define /r FindDebugInfo(SystemTable)\r
+unsigned long SystemTable;\r
+{\r
+ unsigned long CfgTableEntries;\r
+ unsigned long ConfigTable;\r
+ unsigned long i;\r
+ unsigned long offset;\r
+ unsigned long dbghdr;\r
+ unsigned long dbgentries;\r
+ unsigned long dbgptr;\r
+ unsigned long dbginfo;\r
+ unsigned long loadedimg;\r
+ \r
+ $printf "FindDebugInfo"$;\r
+ \r
+ dbgentries = 0;\r
+ CfgTableEntries = dword(SystemTable + 0x40);\r
+ ConfigTable = dword(SystemTable + 0x44);\r
+ \r
+ $printf "config table is at %x (%d entries)", ConfigTable, CfgTableEntries$;\r
+ \r
+ // now search for debug info entry with guid 49152E77-1ADA-4764-B7A2-7AFEFED95E8B\r
+ // 0x49152E77 0x47641ADA 0xFE7AA2B7 0x8B5ED9FE\r
+ for(i=0; i<CfgTableEntries; i++)\r
+ {\r
+ offset = ConfigTable + (i*0x14);\r
+ if(dword(offset) == 0x49152E77)\r
+ {\r
+ if(dword(offset+4) == 0x47641ADA)\r
+ {\r
+ if(dword(offset+8) == 0xFE7AA2B7)\r
+ {\r
+ if(dword(offset+0xc) == 0x8B5ED9FE)\r
+ {\r
+ dbghdr = dword(offset+0x10);\r
+ dbgentries = dword(dbghdr + 4);\r
+ dbgptr = dword(dbghdr + 8);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ \r
+ if(dbgentries == 0)\r
+ {\r
+ $printf "no debug entries found"$;\r
+ return;\r
+ }\r
+ \r
+ $printf "debug table at %x (%d entries)", dbgptr, dbgentries$;\r
+ \r
+ for(i=0; i<dbgentries; i++)\r
+ {\r
+ dbginfo = dword(dbgptr + (i*4));\r
+ if(dbginfo != 0)\r
+ {\r
+ if(dword(dbginfo) == 1) // normal debug info type\r
+ {\r
+ loadedimg = dword(dbginfo + 4);\r
+ ProcessPE32(dword(loadedimg + 0x20));\r
+ }\r
+ }\r
+ }\r
+}\r
+.\r
+\r
+define /r LoadDxe()\r
+{\r
+ unsigned long maxmem;\r
+ unsigned long systbl;\r
+ \r
+ $printf "LoadDxe"$;\r
+ \r
+ $fopen 50, 'C:\loadfiles.inc'$;\r
+ \r
+ maxmem = GetMaxMem();\r
+ systbl = FindSystemTable(maxmem);\r
+ if(systbl != 0)\r
+ {\r
+ $printf "found system table at %x",systbl$;\r
+ FindDebugInfo(systbl);\r
+ }\r
+ \r
+ $vclose 50$;\r
+}\r
+.\r
+\r
+define /r LoadRuntimeDxe()\r
+\r
+{\r
+ unsigned long maxmem;\r
+ unsigned long SystemTable;\r
+ unsigned long CfgTableEntries;\r
+ unsigned long ConfigTable;\r
+ unsigned long i;\r
+ unsigned long offset;\r
+ unsigned long numentries;\r
+ unsigned long RuntimeDebugInfo;\r
+ unsigned long DebugInfoOffset;\r
+ unsigned long imgbase;\r
+ \r
+ $printf "LoadRuntimeDxe"$;\r
+ \r
+ $fopen 50, 'C:\loadfiles.inc'$;\r
+ \r
+ RuntimeDebugInfo = 0x80000010;\r
+ \r
+ if(RuntimeDebugInfo != 0)\r
+ {\r
+ numentries = dword(RuntimeDebugInfo);\r
+ \r
+ $printf "runtime debug info is at %x (%d entries)", RuntimeDebugInfo, numentries$;\r
+ \r
+ DebugInfoOffset = RuntimeDebugInfo + 0x4;\r
+ for(i=0; i<numentries; i++)\r
+ {\r
+ imgbase = dword(DebugInfoOffset);\r
+ if(imgbase != 0)\r
+ {\r
+ $printf "found image at %x",imgbase$;\r
+ ProcessPE32(imgbase);\r
+ }\r
+ DebugInfoOffset = DebugInfoOffset + 0x4;\r
+ }\r
+ }\r
+ \r
+ $vclose 50$;\r
+}\r
+.\r
--- /dev/null
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+error = continue
+unload
+error = abort
+
+setreg @CP15_CONTROL = 0x0005107E
+setreg @pc=0x80008208
+setreg @cpsr=0x000000D3
+dis/D
+readfile,raw,nowarn "ZZZZZZ/FV/BEAGLEBOARD_EFI.fd"=0x80008000
+
--- /dev/null
+#!/bin/sh\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http:#opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+\r
+IN=`/usr/bin/cygpath -u $1`\r
+OUT=`/usr/bin/cygpath -u $2`\r
+\r
+/usr/bin/sed -e "s/\/cygdrive\/\(.\)/load\/a\/ni\/np \"\1:/g" \\r
+ -e 's:\\:/:g' \\r
+ -e "s/^/load\/a\/ni\/np \"/g" \\r
+ -e "s/dll /dll\" \&/g" \\r
+ $IN | /usr/bin/sort.exe --key=3 --output=$OUT\r
+\r
--- /dev/null
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+
+error = continue
+unload
+error = abort
+
+setreg @CP15_CONTROL = 0x0005107E
+setreg @cpsr=0x000000D3
+
+; General clock settings.
+setmem /32 0x48307270=0x00000080
+setmem /32 0x48306D40=0x00000003
+setmem /32 0x48005140=0x03020A50
+
+;Clock configuration
+setmem /32 0x48004A40=0x0000030A
+setmem /32 0x48004C40=0x00000015
+
+;DPLL3 (Core) settings
+setmem /32 0x48004D00=0x00370037
+setmem /32 0x48004D30=0x00000000
+setmem /32 0x48004D40=0x094C0C00
+
+;DPLL4 (Peripheral) settings
+setmem /32 0x48004D00=0x00370037
+setmem /32 0x48004D30=0x00000000
+setmem /32 0x48004D44=0x0001B00C
+setmem /32 0x48004D48=0x00000009
+
+;DPLL1 (MPU) settings
+setmem /32 0x48004904=0x00000037
+setmem /32 0x48004934=0x00000000
+setmem /32 0x48004940=0x0011F40C
+setmem /32 0x48004944=0x00000001
+setmem /32 0x48004948=0x00000000
+
+;RAM setup.
+setmem /16 0x6D000010=0x0000
+setmem /16 0x6D000040=0x0001
+setmem /16 0x6D000044=0x0100
+setmem /16 0x6D000048=0x0000
+setmem /32 0x6D000060=0x0000000A
+setmem /32 0x6D000070=0x00000081
+setmem /16 0x6D000040=0x0003
+setmem /32 0x6D000080=0x02D04011
+setmem /16 0x6D000084=0x0032
+setmem /16 0x6D00008C=0x0000
+setmem /32 0x6D00009C=0xBA9DC4C6
+setmem /32 0x6D0000A0=0x00012522
+setmem /32 0x6D0000A4=0x0004E201
+setmem /16 0x6D000040=0x0003
+setmem /32 0x6D0000B0=0x02D04011
+setmem /16 0x6D0000B4=0x0032
+setmem /16 0x6D0000BC=0x0000
+setmem /32 0x6D0000C4=0xBA9DC4C6
+setmem /32 0x6D0000C8=0x00012522
+setmem /32 0x6D0000D4=0x0004E201
\ No newline at end of file
--- /dev/null
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+// \r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+\r
+include 'ZZZZZZ/rvi_symbols_macros.inc'\r
+\r
+macro write_symbols_file("ZZZZZZ/rvi_symbols.tmp", 0x00000000, 0x10000000)\r
+\r
+host "bash -o igncr ZZZZZZ/rvi_convert_symbols.sh ZZZZZZ/rvi_symbols.tmp ZZZZZZ/rvi_symbols.inc"\r
+include 'ZZZZZZ/rvi_symbols.inc'\r
+load /NI /NP 'ZZZZZZ/rvi_dummy.axf' ;.constdata\r
+unload rvi_dummy.axf\r
+delfile rvi_dummy.axf\r
+\r
+\r
--- /dev/null
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+// \r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+\r
+define /R int compare_guid(guid1, guid2)\r
+ unsigned char *guid1;\r
+ unsigned char *guid2;\r
+{\r
+ return strncmp(guid1, guid2, 16);\r
+}\r
+.\r
+\r
+define /R unsigned char * find_system_table(mem_start, mem_size)\r
+ unsigned char *mem_start;\r
+ unsigned long mem_size;\r
+{\r
+ unsigned char *mem_ptr;\r
+ \r
+ mem_ptr = mem_start + mem_size;\r
+ \r
+ do\r
+ {\r
+ mem_ptr -= 0x400000; // 4 MB\r
+ \r
+ if (strncmp(mem_ptr, "IBI SYST", 8) == 0)\r
+ {\r
+ return *(unsigned long *)(mem_ptr + 8); // EfiSystemTableBase\r
+ } \r
+ \r
+ } while (mem_ptr > mem_start);\r
+ \r
+ return 0;\r
+}\r
+.\r
+\r
+define /R unsigned char * find_debug_info_table_header(system_table)\r
+ unsigned char *system_table;\r
+{\r
+ unsigned long configuration_table_entries;\r
+ unsigned char *configuration_table;\r
+ unsigned long index;\r
+ unsigned char debug_table_guid[16];\r
+ \r
+ // Fill in the debug table's guid\r
+ debug_table_guid[ 0] = 0x77;\r
+ debug_table_guid[ 1] = 0x2E;\r
+ debug_table_guid[ 2] = 0x15;\r
+ debug_table_guid[ 3] = 0x49;\r
+ debug_table_guid[ 4] = 0xDA;\r
+ debug_table_guid[ 5] = 0x1A;\r
+ debug_table_guid[ 6] = 0x64;\r
+ debug_table_guid[ 7] = 0x47;\r
+ debug_table_guid[ 8] = 0xB7;\r
+ debug_table_guid[ 9] = 0xA2;\r
+ debug_table_guid[10] = 0x7A;\r
+ debug_table_guid[11] = 0xFE;\r
+ debug_table_guid[12] = 0xFE;\r
+ debug_table_guid[13] = 0xD9;\r
+ debug_table_guid[14] = 0x5E;\r
+ debug_table_guid[15] = 0x8B;\r
+ \r
+ configuration_table_entries = *(unsigned long *)(system_table + 64);\r
+ configuration_table = *(unsigned long *)(system_table + 68);\r
+ \r
+ for (index = 0; index < configuration_table_entries; index++)\r
+ {\r
+ if (compare_guid(configuration_table, debug_table_guid) == 0)\r
+ {\r
+ return *(unsigned long *)(configuration_table + 16);\r
+ }\r
+ \r
+ configuration_table += 20;\r
+ }\r
+ \r
+ return 0;\r
+}\r
+.\r
+\r
+define /R int valid_pe_header(header)\r
+ unsigned char *header;\r
+{\r
+ if ((header[0x00] == 'M') &&\r
+ (header[0x01] == 'Z') &&\r
+ (header[0x80] == 'P') &&\r
+ (header[0x81] == 'E'))\r
+ {\r
+ return 1;\r
+ }\r
+ \r
+ return 0;\r
+}\r
+.\r
+\r
+define /R unsigned long pe_headersize(header)\r
+ unsigned char *header;\r
+{\r
+ unsigned long *size;\r
+ \r
+ size = header + 0x00AC;\r
+ \r
+ return *size;\r
+}\r
+.\r
+\r
+define /R unsigned char *pe_filename(header)\r
+ unsigned char *header;\r
+{\r
+ unsigned long *debugOffset;\r
+ unsigned char *stringOffset;\r
+ \r
+ if (valid_pe_header(header))\r
+ {\r
+ debugOffset = header + 0x0128;\r
+ stringOffset = header + *debugOffset + 0x002C;\r
+ \r
+ return stringOffset;\r
+ }\r
+ \r
+ return 0;\r
+}\r
+.\r
+\r
+define /R int char_is_valid(c)\r
+ unsigned char c;\r
+{\r
+ if (c >= 32 && c < 127)\r
+ return 1;\r
+\r
+ return 0;\r
+}\r
+.\r
+\r
+define /R write_symbols_file(filename, mem_start, mem_size)\r
+ unsigned char *filename;\r
+ unsigned char *mem_start;\r
+ unsigned long mem_size; \r
+{\r
+ unsigned char *system_table;\r
+ unsigned char *debug_info_table_header;\r
+ unsigned char *debug_info_table;\r
+ unsigned long debug_info_table_size;\r
+ unsigned long index;\r
+ unsigned char *debug_image_info;\r
+ unsigned char *loaded_image_protocol;\r
+ unsigned char *image_base;\r
+ unsigned char *debug_filename;\r
+ unsigned long header_size;\r
+ int status;\r
+ \r
+ system_table = find_system_table(mem_start, mem_size);\r
+ if (system_table == 0)\r
+ {\r
+ return;\r
+ }\r
+ \r
+ status = fopen(88, filename, "w");\r
+ \r
+ debug_info_table_header = find_debug_info_table_header(system_table);\r
+ \r
+ debug_info_table = *(unsigned long *)(debug_info_table_header + 8);\r
+ debug_info_table_size = *(unsigned long *)(debug_info_table_header + 4);\r
+ \r
+ for (index = 0; index < (debug_info_table_size * 4); index += 4)\r
+ {\r
+ debug_image_info = *(unsigned long *)(debug_info_table + index); \r
+ \r
+ if (debug_image_info == 0)\r
+ {\r
+ break;\r
+ }\r
+ \r
+ loaded_image_protocol = *(unsigned long *)(debug_image_info + 4);\r
+ \r
+ image_base = *(unsigned long *)(loaded_image_protocol + 32);\r
+ \r
+ debug_filename = pe_filename(image_base);\r
+ header_size = pe_headersize(image_base);\r
+ \r
+ $fprintf 88, "%s 0x%08x\n", debug_filename, image_base + header_size$;\r
+ }\r
+ \r
+ \r
+ fclose(88);\r
+}\r
+.\r
+\r
--- /dev/null
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+// \r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+\r
+error = continue\r
+\r
+unload\r
+\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+delfile 1\r
+\r
+error = abort\r
--- /dev/null
+/*++\r
+RealView EB FVB DXE Driver\r
+\r
+Copyright (c) 2010, Apple Inc. All rights reserved.<BR> \r
+This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+\r
+--*/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+\r
+\r
+\r
+/**\r
+ The GetAttributes() function retrieves the attributes and\r
+ current settings of the block.\r
+\r
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+\r
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the\r
+ attributes and current settings are\r
+ returned. Type EFI_FVB_ATTRIBUTES_2 is defined\r
+ in EFI_FIRMWARE_VOLUME_HEADER.\r
+\r
+ @retval EFI_SUCCESS The firmware volume attributes were\r
+ returned.\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetAttributes (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+ The SetAttributes() function sets configurable firmware volume\r
+ attributes and returns the new settings of the firmware volume.\r
+ \r
+\r
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+\r
+ @param Attributes On input, Attributes is a pointer to\r
+ EFI_FVB_ATTRIBUTES_2 that contains the\r
+ desired firmware volume settings. On\r
+ successful return, it contains the new\r
+ settings of the firmware volume. Type\r
+ EFI_FVB_ATTRIBUTES_2 is defined in\r
+ EFI_FIRMWARE_VOLUME_HEADER.\r
+ \r
+ @retval EFI_SUCCESS The firmware volume attributes were returned.\r
+\r
+ @retval EFI_INVALID_PARAMETER The attributes requested are in\r
+ conflict with the capabilities\r
+ as declared in the firmware\r
+ volume header.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbSetAttributes (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+ The GetPhysicalAddress() function retrieves the base address of\r
+ a memory-mapped firmware volume. This function should be called\r
+ only for memory-mapped firmware volumes.\r
+\r
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+ \r
+ @param Address Pointer to a caller-allocated\r
+ EFI_PHYSICAL_ADDRESS that, on successful\r
+ return from GetPhysicalAddress(), contains the\r
+ base address of the firmware volume.\r
+ \r
+ @retval EFI_SUCCESS The firmware volume base address was returned.\r
+ \r
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetPhysicalAddress (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+ OUT EFI_PHYSICAL_ADDRESS *Address\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+ The GetBlockSize() function retrieves the size of the requested\r
+ block. It also returns the number of additional blocks with\r
+ the identical size. The GetBlockSize() function is used to\r
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).\r
+\r
+\r
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+\r
+ @param Lba Indicates the block for which to return the size.\r
+\r
+ @param BlockSize Pointer to a caller-allocated UINTN in which\r
+ the size of the block is returned.\r
+\r
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in\r
+ which the number of consecutive blocks,\r
+ starting with Lba, is returned. All\r
+ blocks in this range have a size of\r
+ BlockSize.\r
+\r
+ \r
+ @retval EFI_SUCCESS The firmware volume base address was returned.\r
+ \r
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetBlockSize (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+ IN EFI_LBA Lba,\r
+ OUT UINTN *BlockSize,\r
+ OUT UINTN *NumberOfBlocks\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Reads the specified number of bytes into a buffer from the specified block.\r
+\r
+ The Read() function reads the requested number of bytes from the\r
+ requested block and stores them in the provided buffer.\r
+ Implementations should be mindful that the firmware volume\r
+ might be in the ReadDisabled state. If it is in this state,\r
+ the Read() function must return the status code\r
+ EFI_ACCESS_DENIED without modifying the contents of the\r
+ buffer. The Read() function must also prevent spanning block\r
+ boundaries. If a read is requested that would span a block\r
+ boundary, the read must read up to the boundary but not\r
+ beyond. The output parameter NumBytes must be set to correctly\r
+ indicate the number of bytes actually read. The caller must be\r
+ aware that a read may be partially completed.\r
+\r
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+ \r
+ @param Lba The starting logical block index\r
+ from which to read.\r
+\r
+ @param Offset Offset into the block at which to begin reading.\r
+\r
+ @param NumBytes Pointer to a UINTN. At entry, *NumBytes\r
+ contains the total size of the buffer. At\r
+ exit, *NumBytes contains the total number of\r
+ bytes read.\r
+\r
+ @param Buffer Pointer to a caller-allocated buffer that will\r
+ be used to hold the data that is read.\r
+\r
+ @retval EFI_SUCCESS The firmware volume was read successfully,\r
+ and contents are in Buffer.\r
+ \r
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA\r
+ boundary. On output, NumBytes\r
+ contains the total number of bytes\r
+ returned in Buffer.\r
+ \r
+ @retval EFI_ACCESS_DENIED The firmware volume is in the\r
+ ReadDisabled state.\r
+ \r
+ @retval EFI_DEVICE_ERROR The block device is not\r
+ functioning correctly and could\r
+ not be read.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbRead (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN Offset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN OUT UINT8 *Buffer\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+ Writes the specified number of bytes from the input buffer to the block.\r
+\r
+ The Write() function writes the specified number of bytes from\r
+ the provided buffer to the specified block and offset. If the\r
+ firmware volume is sticky write, the caller must ensure that\r
+ all the bits of the specified range to write are in the\r
+ EFI_FVB_ERASE_POLARITY state before calling the Write()\r
+ function, or else the result will be unpredictable. This\r
+ unpredictability arises because, for a sticky-write firmware\r
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY\r
+ state but cannot flip it back again. Before calling the\r
+ Write() function, it is recommended for the caller to first call \r
+ the EraseBlocks() function to erase the specified block to\r
+ write. A block erase cycle will transition bits from the\r
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the\r
+ EFI_FVB_ERASE_POLARITY state. Implementations should be\r
+ mindful that the firmware volume might be in the WriteDisabled\r
+ state. If it is in this state, the Write() function must\r
+ return the status code EFI_ACCESS_DENIED without modifying the\r
+ contents of the firmware volume. The Write() function must\r
+ also prevent spanning block boundaries. If a write is\r
+ requested that spans a block boundary, the write must store up\r
+ to the boundary but not beyond. The output parameter NumBytes\r
+ must be set to correctly indicate the number of bytes actually\r
+ written. The caller must be aware that a write may be\r
+ partially completed. All writes, partial or otherwise, must be\r
+ fully flushed to the hardware before the Write() service\r
+ returns.\r
+\r
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+ \r
+ @param Lba The starting logical block index to write to.\r
+ \r
+ @param Offset Offset into the block at which to begin writing.\r
+ \r
+ @param NumBytes The pointer to a UINTN. At entry, *NumBytes\r
+ contains the total size of the buffer. At\r
+ exit, *NumBytes contains the total number of\r
+ bytes actually written.\r
+ \r
+ @param Buffer The pointer to a caller-allocated buffer that\r
+ contains the source for the write.\r
+ \r
+ @retval EFI_SUCCESS The firmware volume was written successfully.\r
+ \r
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an\r
+ LBA boundary. On output, NumBytes\r
+ contains the total number of bytes\r
+ actually written.\r
+ \r
+ @retval EFI_ACCESS_DENIED The firmware volume is in the\r
+ WriteDisabled state.\r
+ \r
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning\r
+ and could not be written.\r
+\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbWrite (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN Offset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+ Erases and initializes a firmware volume block.\r
+\r
+ The EraseBlocks() function erases one or more blocks as denoted\r
+ by the variable argument list. The entire parameter list of\r
+ blocks must be verified before erasing any blocks. If a block is\r
+ requested that does not exist within the associated firmware\r
+ volume (it has a larger index than the last block of the\r
+ firmware volume), the EraseBlocks() function must return the\r
+ status code EFI_INVALID_PARAMETER without modifying the contents\r
+ of the firmware volume. Implementations should be mindful that\r
+ the firmware volume might be in the WriteDisabled state. If it\r
+ is in this state, the EraseBlocks() function must return the\r
+ status code EFI_ACCESS_DENIED without modifying the contents of\r
+ the firmware volume. All calls to EraseBlocks() must be fully\r
+ flushed to the hardware before the EraseBlocks() service\r
+ returns.\r
+\r
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL\r
+ instance.\r
+\r
+ @param ... The variable argument list is a list of tuples.\r
+ Each tuple describes a range of LBAs to erase\r
+ and consists of the following:\r
+ - An EFI_LBA that indicates the starting LBA\r
+ - A UINTN that indicates the number of blocks to\r
+ erase.\r
+\r
+ The list is terminated with an\r
+ EFI_LBA_LIST_TERMINATOR. For example, the\r
+ following indicates that two ranges of blocks\r
+ (5-7 and 10-11) are to be erased: EraseBlocks\r
+ (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);\r
+\r
+ @retval EFI_SUCCESS The erase request successfully\r
+ completed.\r
+ \r
+ @retval EFI_ACCESS_DENIED The firmware volume is in the\r
+ WriteDisabled state.\r
+ @retval EFI_DEVICE_ERROR The block device is not functioning\r
+ correctly and could not be written.\r
+ The firmware device may have been\r
+ partially erased.\r
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed\r
+ in the variable argument list do\r
+ not exist in the firmware volume. \r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbEraseBlocks (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
+ ...\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+//\r
+// Making this global saves a few bytes in image size\r
+//\r
+EFI_HANDLE gFvbHandle = NULL;\r
+\r
+\r
+///\r
+/// The Firmware Volume Block Protocol is the low-level interface\r
+/// to a firmware volume. File-level access to a firmware volume\r
+/// should not be done using the Firmware Volume Block Protocol.\r
+/// Normal access to a firmware volume must use the Firmware\r
+/// Volume Protocol. Typically, only the file system driver that\r
+/// produces the Firmware Volume Protocol will bind to the\r
+/// Firmware Volume Block Protocol.\r
+///\r
+EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL gFvbProtocol = {\r
+ FvbGetAttributes,\r
+ FvbSetAttributes,\r
+ FvbGetPhysicalAddress,\r
+ FvbGetBlockSize,\r
+ FvbRead,\r
+ FvbWrite,\r
+ FvbEraseBlocks,\r
+ ///\r
+ /// The handle of the parent firmware volume.\r
+ /// \r
+ NULL\r
+};\r
+\r
+// NvStorageVariableBase = (EFI_PHYSICAL_ADDRESS) FixedPcdGet32 (PcdFlashNvStorageVariableBase);\r
+\r
+\r
+/**\r
+ Initialize the state information for the CPU Architectural Protocol\r
+\r
+ @param ImageHandle of the loaded driver\r
+ @param SystemTable Pointer to the System Table\r
+\r
+ @retval EFI_SUCCESS Protocol registered\r
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r
+ @retval EFI_DEVICE_ERROR Hardware problems\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbDxeInitialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ \r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &gFvbHandle,\r
+ &gEfiFirmwareVolumeBlockProtocolGuid, &gFvbProtocol,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ \r
+ // SetVertAddressEvent ()\r
+ \r
+ // GCD Map NAND as RT\r
+ \r
+ return Status;\r
+}\r
+\r
--- /dev/null
+#/** @file\r
+# \r
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = FvbDxe\r
+ FILE_GUID = 43ECE281-D9E2-4DD0-B304-E6A5689256F4\r
+ MODULE_TYPE = DXE_RUNTIME_DRIVER\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = FvbDxeInitialize\r
+\r
+\r
+[Sources.common]\r
+ FvbDxe.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ UefiLib\r
+ UefiBootServicesTableLib\r
+ DebugLib\r
+ PrintLib\r
+ UefiDriverEntryPoint\r
+ IoLib\r
+\r
+[Guids]\r
+ \r
+\r
+[Protocols]\r
+ gEfiFirmwareVolumeBlockProtocolGuid\r
+\r
+[FixedPcd.common]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+\r
+[depex]\r
+ TRUE\r
--- /dev/null
+/** @file\r
+* Header defining RealView EB constants (Base addresses, sizes, flags)\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#ifndef __ARM_EB_H__\r
+#define __ARM_EB_H__\r
+\r
+/*******************************************\r
+// Platform Memory Map\r
+*******************************************/\r
+\r
+// Can be NOR, DOC, DRAM, SRAM\r
+#define ARM_EB_REMAP_BASE 0x00000000\r
+#define ARM_EB_REMAP_SZ 0x04000000\r
+\r
+// Motherboard Peripheral and On-chip peripheral\r
+#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
+#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000\r
+#define ARM_EB_BOARD_PERIPH_BASE 0x10000000\r
+//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000\r
+\r
+// SMC\r
+#define ARM_EB_SMC_BASE 0x40000000\r
+#define ARM_EB_SMC_SZ 0x20000000\r
+\r
+// NOR Flash 1\r
+#define ARM_EB_SMB_NOR_BASE 0x40000000\r
+#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */\r
+// DOC Flash\r
+#define ARM_EB_SMB_DOC_BASE 0x44000000\r
+#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */\r
+// SRAM\r
+#define ARM_EB_SMB_SRAM_BASE 0x48000000\r
+#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */\r
+// USB, Ethernet, VRAM\r
+#define ARM_EB_SMB_PERIPH_BASE 0x4E000000\r
+//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000\r
+#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */\r
+\r
+// DRAM\r
+#define ARM_EB_DRAM_BASE 0x70000000\r
+#define ARM_EB_DRAM_SZ 0x10000000\r
+\r
+// Logic Tile\r
+#define ARM_EB_LOGIC_TILE_BASE 0xC0000000\r
+#define ARM_EB_LOGIC_TILE_SZ 0x40000000\r
+\r
+/*******************************************\r
+// Motherboard peripherals\r
+*******************************************/\r
+\r
+// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r
+#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
+#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
+#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
+#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
+#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
+#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
+#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
+\r
+// SP810 Controller\r
+#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
+\r
+// SYSTRCL Register\r
+#define ARM_EB_SYSCTRL 0x10001000\r
+\r
+// Uart0\r
+#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
+#define PL011_CONSOLE_UART_SPEED 115200\r
+\r
+// SP804 Timer Bases\r
+#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
+#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
+#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
+#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
+\r
+// Dynamic Memory Controller Base\r
+#define ARM_EB_DMC_BASE 0x10018000\r
+\r
+// Static Memory Controller Base\r
+#define ARM_EB_SMC_CTRL_BASE 0x10080000\r
+\r
+/*// System Configuration Controller register Base addresses\r
+//#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000\r
+#define ARM_EB_SYS_CFGRW0_REG 0x100E2000\r
+#define ARM_EB_SYS_CFGRW1_REG 0x100E2004\r
+#define ARM_EB_SYS_CFGRW2_REG 0x100E2008\r
+\r
+#define ARM_EB_CFGRW1_REMAP_NOR0 0\r
+#define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28)\r
+#define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29)\r
+#define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30)\r
+\r
+// PL301 Fast AXI Base Address\r
+#define ARM_EB_FAXI_BASE 0x100E9000\r
+\r
+// L2x0 Cache Controller Base Address\r
+//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/\r
+\r
+\r
+/*******************************************\r
+// Interrupt Map\r
+*******************************************/\r
+\r
+// Timer Interrupts\r
+#define TIMER01_INTERRUPT_NUM 34\r
+#define TIMER23_INTERRUPT_NUM 35\r
+\r
+\r
+/*******************************************\r
+// EFI Memory Map in Permanent Memory (DRAM)\r
+*******************************************/\r
+\r
+// This region is allocated at the bottom of the DRAM. It will be used\r
+// for fixed address allocations such as Vector Table\r
+#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB\r
+\r
+// This region is the memory declared to PEI as permanent memory for PEI\r
+// and DXE. EFI stacks and heaps will be declared in this region.\r
+#define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000\r
+\r
+#endif \r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR> \r
+This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ Gic.c\r
+\r
+Abstract:\r
+\r
+ Driver implementing the GIC interrupt controller protocol\r
+\r
+--*/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+\r
+#include <Protocol/Cpu.h>\r
+#include <Protocol/HardwareInterrupt.h>\r
+\r
+\r
+//\r
+// EB board definitions\r
+//\r
+#define EB_GIC1_CPU_INTF_BASE 0x10040000\r
+#define EB_GIC1_DIST_BASE 0x10041000\r
+#define EB_GIC2_CPU_INTF_BASE 0x10050000\r
+#define EB_GIC2_DIST_BASE 0x10051000\r
+#define EB_GIC3_CPU_INTF_BASE 0x10060000\r
+#define EB_GIC3_DIST_BASE 0x10061000\r
+#define EB_GIC4_CPU_INTF_BASE 0x10070000\r
+#define EB_GIC5_DIST_BASE 0x10071000\r
+\r
+// number of interrupts sources supported by each GIC on the EB\r
+#define EB_NUM_GIC_INTERRUPTS 96 \r
+\r
+// number of 32-bit registers needed to represent those interrupts as a bit\r
+// (used for enable set, enable clear, pending set, pending clear, and active regs)\r
+#define EB_NUM_GIC_REG_PER_INT_BITS (EB_NUM_GIC_INTERRUPTS / 32)\r
+\r
+// number of 32-bit registers needed to represent those interrupts as two bits\r
+// (used for configuration reg)\r
+#define EB_NUM_GIC_REG_PER_INT_CFG (EB_NUM_GIC_INTERRUPTS / 16)\r
+\r
+// number of 32-bit registers needed to represent interrupts as 8-bit priority field\r
+// (used for priority regs)\r
+#define EB_NUM_GIC_REG_PER_INT_BYTES (EB_NUM_GIC_INTERRUPTS / 4)\r
+\r
+#define GIC_DEFAULT_PRIORITY 0x80\r
+\r
+//\r
+// GIC definitions\r
+//\r
+\r
+// Distributor\r
+#define GIC_ICDDCR 0x000 // Distributor Control Register\r
+#define GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
+#define GIC_ICDIIDR 0x008 // Implementer Identification Register\r
+\r
+// each reg base below repeats for EB_NUM_GIC_REG_PER_INT_BITS (see GIC spec)\r
+#define GIC_ICDISR 0x080 // Interrupt Security Registers\r
+#define GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
+#define GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
+#define GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
+#define GIC_ICDCPR 0x280 // Interrupt Clear-Pending Registers\r
+#define GIC_ICDABR 0x300 // Active Bit Registers\r
+\r
+// each reg base below repeats for EB_NUM_GIC_REG_PER_INT_BYTES\r
+#define GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
+\r
+// each reg base below repeats for EB_NUM_GIC_INTERRUPTS\r
+#define GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
+#define GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
+\r
+// just one of these\r
+#define GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
+\r
+\r
+// Cpu interface\r
+#define GIC_ICCICR 0x00 // CPU Interface Controler Register\r
+#define GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
+#define GIC_ICCBPR 0x08 // Binary Point Register\r
+#define GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
+#define GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
+#define GIC_ICCRPR 0x14 // Running Priority Register\r
+#define GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
+#define GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
+#define GIC_ICCIDR 0xFC // Identification Register\r
+\r
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;\r
+\r
+//\r
+// Notifications\r
+//\r
+VOID *CpuProtocolNotificationToken = NULL;\r
+EFI_EVENT CpuProtocolNotificationEvent = (EFI_EVENT)NULL;\r
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
+\r
+\r
+HARDWARE_INTERRUPT_HANDLER gRegisteredInterruptHandlers[EB_NUM_GIC_INTERRUPTS];\r
+\r
+/**\r
+ Register Handler for the specified interrupt source.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+ @param Handler Callback for interrupt. NULL to unregister\r
+\r
+ @retval EFI_SUCCESS Source was updated to support Handler.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RegisterInterruptSource (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN HARDWARE_INTERRUPT_HANDLER Handler\r
+ )\r
+{\r
+ if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ } \r
+ \r
+ if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {\r
+ return EFI_ALREADY_STARTED;\r
+ }\r
+\r
+ gRegisteredInterruptHandlers[Source] = Handler;\r
+ return This->EnableInterruptSource(This, Source);\r
+}\r
+\r
+\r
+/**\r
+ Enable interrupt source Source.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+\r
+ @retval EFI_SUCCESS Source interrupt enabled.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EnableInterruptSource (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
+ )\r
+{\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ \r
+ if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ \r
+ // calculate enable register offset and bit position\r
+ RegOffset = Source / 32;\r
+ RegShift = Source % 32;\r
+\r
+ // write set-enable register\r
+ MmioWrite32 (EB_GIC1_DIST_BASE+GIC_ICDISER+(4*RegOffset), 1 << RegShift);\r
+ \r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Disable interrupt source Source.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+\r
+ @retval EFI_SUCCESS Source interrupt disabled.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+DisableInterruptSource (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
+ )\r
+{\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ \r
+ if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ \r
+ // calculate enable register offset and bit position\r
+ RegOffset = Source / 32;\r
+ RegShift = Source % 32;\r
+\r
+ // write set-enable register\r
+ MmioWrite32 (EB_GIC1_DIST_BASE+GIC_ICDICER+(4*RegOffset), 1 << RegShift);\r
+ \r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Return current state of interrupt source Source.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+ @param InterruptState TRUE: source enabled, FALSE: source disabled.\r
+\r
+ @retval EFI_SUCCESS InterruptState is valid\r
+ @retval EFI_DEVICE_ERROR InterruptState is not valid\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetInterruptSourceState (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN BOOLEAN *InterruptState\r
+ )\r
+{\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ \r
+ if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ \r
+ // calculate enable register offset and bit position\r
+ RegOffset = Source / 32;\r
+ RegShift = Source % 32;\r
+ \r
+ if ((MmioRead32 (EB_GIC1_DIST_BASE+GIC_ICDISER+(4*RegOffset)) & (1<<RegShift)) == 0) {\r
+ *InterruptState = FALSE;\r
+ } else {\r
+ *InterruptState = TRUE;\r
+ }\r
+ \r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Signal to the hardware that the End Of Intrrupt state \r
+ has been reached.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+\r
+ @retval EFI_SUCCESS Source interrupt EOI'ed.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EndOfInterrupt (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
+ )\r
+{\r
+ if (Source > EB_NUM_GIC_INTERRUPTS) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ MmioWrite32 (EB_GIC1_CPU_INTF_BASE+GIC_ICCEIOR, Source);\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
+\r
+ @param InterruptType Defines the type of interrupt or exception that\r
+ occurred on the processor.This parameter is processor architecture specific.\r
+ @param SystemContext A pointer to the processor context when\r
+ the interrupt occurred on the processor.\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IrqInterruptHandler (\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
+ )\r
+{\r
+ UINT32 GicInterrupt;\r
+ HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
+\r
+ GicInterrupt = MmioRead32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCIAR);\r
+ if (GicInterrupt >= EB_NUM_GIC_INTERRUPTS) {\r
+ MmioWrite32 (EB_GIC1_CPU_INTF_BASE+GIC_ICCEIOR, GicInterrupt);\r
+ }\r
+ \r
+ InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r
+ if (InterruptHandler != NULL) {\r
+ // Call the registered interrupt handler.\r
+ InterruptHandler (GicInterrupt, SystemContext);\r
+ } else {\r
+ DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: %x\n", GicInterrupt));\r
+ }\r
+\r
+ EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);\r
+}\r
+\r
+\r
+//\r
+// Making this global saves a few bytes in image size\r
+//\r
+EFI_HANDLE gHardwareInterruptHandle = NULL;\r
+\r
+//\r
+// The protocol instance produced by this driver\r
+//\r
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {\r
+ RegisterInterruptSource,\r
+ EnableInterruptSource,\r
+ DisableInterruptSource,\r
+ GetInterruptSourceState,\r
+ EndOfInterrupt\r
+};\r
+\r
+\r
+/**\r
+ Shutdown our hardware\r
+ \r
+ DXE Core will disable interrupts and turn off the timer and disable interrupts\r
+ after all the event handlers have run.\r
+\r
+ @param[in] Event The Event that is being processed\r
+ @param[in] Context Event Context\r
+**/\r
+VOID\r
+EFIAPI\r
+ExitBootServicesEvent (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ UINTN i;\r
+ \r
+ for (i = 0; i < EB_NUM_GIC_INTERRUPTS; i++) {\r
+ DisableInterruptSource (&gHardwareInterruptProtocol, i);\r
+ }\r
+}\r
+\r
+\r
+//\r
+// Notification routines\r
+//\r
+VOID\r
+CpuProtocolInstalledNotification (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_CPU_ARCH_PROTOCOL *Cpu;\r
+ \r
+ //\r
+ // Get the cpu protocol that this driver requires.\r
+ //\r
+ Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ //\r
+ // Unregister the default exception handler.\r
+ //\r
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ //\r
+ // Register to receive interrupts\r
+ //\r
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);\r
+ ASSERT_EFI_ERROR(Status);\r
+}\r
+\r
+/**\r
+ Initialize the state information for the CPU Architectural Protocol\r
+\r
+ @param ImageHandle of the loaded driver\r
+ @param SystemTable Pointer to the System Table\r
+\r
+ @retval EFI_SUCCESS Protocol registered\r
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r
+ @retval EFI_DEVICE_ERROR Hardware problems\r
+\r
+**/\r
+EFI_STATUS\r
+InterruptDxeInitialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN i;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+\r
+ \r
+ // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
+\r
+ for (i = 0; i < EB_NUM_GIC_INTERRUPTS; i++) {\r
+ DisableInterruptSource (&gHardwareInterruptProtocol, i);\r
+ \r
+ // Set Priority \r
+ RegOffset = i / 4;\r
+ RegShift = (i % 4) * 8;\r
+ MmioAndThenOr32 (\r
+ EB_GIC1_DIST_BASE+GIC_ICDIPR+(4*RegOffset), \r
+ ~(0xff << RegShift), \r
+ GIC_DEFAULT_PRIORITY << RegShift\r
+ );\r
+ }\r
+\r
+ // configure interrupts for cpu 0\r
+ for (i = 0; i < EB_NUM_GIC_REG_PER_INT_BYTES; i++) {\r
+ MmioWrite32 (EB_GIC1_DIST_BASE + GIC_ICDIPTR + (i*4), 0x01010101);\r
+ }\r
+\r
+ // set binary point reg to 0x7 (no preemption)\r
+ MmioWrite32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCBPR, 0x7);\r
+\r
+ // set priority mask reg to 0xff to allow all priorities through\r
+ MmioWrite32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCPMR, 0xff);\r
+ \r
+ // enable gic cpu interface\r
+ MmioWrite32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCICR, 0x1);\r
+\r
+ // enable gic distributor\r
+ MmioWrite32 (EB_GIC1_DIST_BASE + GIC_ICCICR, 0x1);\r
+\r
+ \r
+ ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));\r
+ \r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &gHardwareInterruptHandle,\r
+ &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ \r
+ // Set up to be notified when the Cpu protocol is installed.\r
+ Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK, CpuProtocolInstalledNotification, NULL, &CpuProtocolNotificationEvent); \r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->RegisterProtocolNotify (&gEfiCpuArchProtocolGuid, CpuProtocolNotificationEvent, (VOID *)&CpuProtocolNotificationToken);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // Register for an ExitBootServicesEvent\r
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
+\r
--- /dev/null
+#/** @file\r
+# \r
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = GicInterruptDxe\r
+ FILE_GUID = A7496828-946E-43BF-97D6-AA0272001899\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = InterruptDxeInitialize\r
+\r
+\r
+[Sources.common]\r
+ InterruptDxe.c\r
+\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ UefiLib\r
+ UefiBootServicesTableLib\r
+ DebugLib\r
+ PrintLib\r
+ UefiDriverEntryPoint\r
+ IoLib\r
+\r
+[Guids]\r
+ \r
+\r
+[Protocols]\r
+ gHardwareInterruptProtocolGuid\r
+ gEfiCpuArchProtocolGuid\r
+ \r
+[FixedPcd.common]\r
+ gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress\r
+\r
+[depex]\r
+ TRUE\r
--- /dev/null
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Drivers/PL341Dmc.h>
+
+/**
+ Return if Trustzone is supported by your platform
+
+ A non-zero value must be returned if you want to support a Secure World on your platform.
+ ArmPlatformTrustzoneInit() will later set up the secure regions.
+ This function can return 0 even if Trustzone is supported by your processor. In this case,
+ the platform will continue to run in Secure World.
+
+ @return A non-zero value if Trustzone supported.
+
+**/
+UINTN ArmPlatformTrustzoneSupported(VOID) {
+ // There is no Trustzone controllers (TZPC & TZASC) and no Secure Memory on RTSM
+ return FALSE;
+}
+
+/**
+ Initialize the Secure peripherals and memory regions
+
+ If Trustzone is supported by your platform then this function makes the required initialization
+ of the secure peripherals and memory regions.
+
+**/
+VOID ArmPlatformTrustzoneInit(VOID) {
+ ASSERT(FALSE);
+}
+
+/**
+ Remap the memory at 0x0
+
+ Some platform requires or gives the ability to remap the memory at the address 0x0.
+ This function can do nothing if this feature is not relevant to your platform.
+
+**/
+VOID ArmPlatformBootRemapping(VOID) {
+ // Disable memory remapping and return to normal mapping
+ MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE
+}
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID ArmPlatformInitializeSystemMemory(VOID) {
+ // We do not need to initialize the System Memory on RTSM
+}
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+#Start of Code section\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)\r
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)\r
+\r
+/**
+ Called at the early stage of the Boot phase to know if the memory has already been initialized
+
+ Running the code from the reset vector does not mean we start from cold boot. In some case, we
+ can go through this code with the memory already initialized.
+ Because this function is called at the early stage, the implementation must not use the stack.
+ Its implementation must probably done in assembly to ensure this requirement.
+
+ @return Return the condition value into the 'Z' flag
+
+**/
+ASM_PFX(ArmPlatformIsMemoryInitialized):\r
+ // Check if the memory has been already mapped, if so skipped the memory initialization
+ LoadConstantToReg (ARM_EB_SYSCTRL, r0)
+ ldr r0, [r0, #0]
+
+ // 0x200 (BIT9): This read-only bit returns the remap status.
+ and r0, r0, #0x200
+ tst r0, #0x200
+ bx lr\r
+ \r
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ASM_PFX(ArmPlatformInitializeBootMemory):\r
+ // The SMC does not need to be initialized for RTSM\r
+ bx lr\r
+\r
+.end\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ EXPORT ArmPlatformIsMemoryInitialized\r
+ EXPORT ArmPlatformInitializeBootMemory\r
+ \r
+ PRESERVE8\r
+ AREA ArmRealViewEbHelper, CODE, READONLY\r
+\r
+/**\r
+ Called at the early stage of the Boot phase to know if the memory has already been initialized\r
+\r
+ Running the code from the reset vector does not mean we start from cold boot. In some case, we\r
+ can go through this code with the memory already initialized.\r
+ Because this function is called at the early stage, the implementation must not use the stack.\r
+ Its implementation must probably done in assembly to ensure this requirement.\r
+\r
+ @return Return the condition value into the 'Z' flag\r
+\r
+**/\r
+ArmPlatformIsMemoryInitialized\r
+ // Check if the memory has been already mapped, if so skipped the memory initialization\r
+ LoadConstantToReg (ARM_EB_SYSCTRL, r0)\r
+ ldr r0, [r0, #0]\r
+ \r
+ // 0x200 (BIT9): This read-only bit returns the remap status.\r
+ and r0, r0, #0x200\r
+ tst r0, #0x200\r
+ bx lr\r
+ \r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ArmPlatformInitializeBootMemory\r
+ // The SMC does not need to be initialized for RTSM\r
+ bx lr\r
+ \r
+ END\r
--- /dev/null
+#/* @file
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmRealViewEbLib
+ FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ MemoryAllocationLib
+
+[Sources.common]
+ ArmRealViewEb.c
+ ArmRealViewEbMem.c
+
+[Protocols]
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdStandalone
+
+[FixedPcd]
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+#define DDR_ATTRIBUTES_SECURE_CACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_SECURE_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED\r
+\r
+/**\r
+ Return the information about the memory region in permanent memory used by PEI\r
+\r
+ One of the PEI Module must install the permament memory used by PEI. This function returns the\r
+ information about this region for your platform to this PEIM module.\r
+\r
+ @param[out] PeiMemoryBase Base of the memory region used by PEI core and modules\r
+ @param[out] PeiMemorySize Size of the memory region used by PEI core and modules\r
+\r
+**/\r
+VOID ArmPlatformGetPeiMemory (\r
+ OUT UINTN* PeiMemoryBase,\r
+ OUT UINTN* PeiMemorySize\r
+ ) {\r
+ ASSERT((PeiMemoryBase != NULL) && (PeiMemorySize != NULL));\r
+ \r
+ *PeiMemoryBase = ARM_EB_DRAM_BASE + ARM_EB_EFI_FIX_ADDRESS_REGION_SZ;\r
+ *PeiMemorySize = ARM_EB_EFI_MEMORY_REGION_SZ;\r
+}\r
+\r
+/**\r
+ Return the Virtual Memory Map of your platform\r
+\r
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
+\r
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
+ Virtual Memory mapping. This array must be ended by a zero-filled\r
+ entry\r
+\r
+**/\r
+VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {\r
+ UINT32 val32;\r
+ UINT32 CacheAttributes;\r
+ BOOLEAN bTrustzoneSupport = FALSE;\r
+ UINTN Index = 0;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+\r
+ ASSERT(VirtualMemoryMap != NULL);\r
+\r
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9);\r
+ if (VirtualMemoryTable == NULL) {\r
+ return;\r
+ }\r
+\r
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);\r
+ } else {\r
+ CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);\r
+ }\r
+\r
+ // ReMap (Either NOR Flash or DRAM)\r
+ VirtualMemoryTable[Index].PhysicalBase = ARM_EB_REMAP_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_REMAP_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_REMAP_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // DDR\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_DRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_DRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_DRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // SMC CS7\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ // SMB CS0-CS1 - NOR Flash 1 & 2\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_NOR_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_NOR_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_SMB_NOR_SZ + ARM_EB_SMB_DOC_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ // SMB CS2 - SRAM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_SMB_SRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // SMB CS3-CS6 - Motherboard Peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_SMB_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
+ if (MmioRead32(ARM_EB_SYS_PROCID1_REG) != 0) {\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_LOGIC_TILE_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_LOGIC_TILE_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_LOGIC_TILE_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+ }\r
+\r
+ // End of Table\r
+ VirtualMemoryTable[++Index].PhysicalBase = 0;\r
+ VirtualMemoryTable[Index].VirtualBase = 0;\r
+ VirtualMemoryTable[Index].Length = 0;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
+}\r
+\r
+/**\r
+ Return the EFI Memory Map of your platform\r
+\r
+ This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource\r
+ Descriptor HOBs used by DXE core.\r
+\r
+ @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an\r
+ EFI Memory region. This array must be ended by a zero-filled entry\r
+\r
+**/\r
+VOID ArmPlatformGetEfiMemoryMap (\r
+ OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
+) {\r
+ EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;\r
+ UINT64 MemoryBase;\r
+ UINTN Index = 0;\r
+ ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR *EfiMemoryTable;\r
+\r
+ ASSERT(EfiMemoryMap != NULL);\r
+\r
+ EfiMemoryTable = (ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR) * 6);\r
+\r
+ Attributes =\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED\r
+ );\r
+ MemoryBase = ARM_EB_DRAM_BASE;\r
+ \r
+ // Memory Reserved for fixed address allocations (such as Exception Vector Table)\r
+ EfiMemoryTable[Index].ResourceAttribute = Attributes;\r
+ EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = ARM_EB_EFI_FIX_ADDRESS_REGION_SZ;\r
+ \r
+ MemoryBase += ARM_EB_EFI_FIX_ADDRESS_REGION_SZ;\r
+\r
+ // Memory declared to PEI as permanent memory for PEI and DXE\r
+ EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
+ EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = ARM_EB_EFI_MEMORY_REGION_SZ;\r
+\r
+ MemoryBase += ARM_EB_EFI_MEMORY_REGION_SZ;\r
+\r
+ // We must reserve the memory used by the Firmware Volume copied in DRAM at 0x80000000\r
+ if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
+ // Chunk between the EFI Memory region and the firmware\r
+ EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
+ EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdBaseAddress) - MemoryBase;\r
+\r
+ // Chunk reserved by the firmware in DRAM\r
+ EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_PRESENT);\r
+ EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdEmbeddedFdBaseAddress);\r
+ EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdSize);\r
+\r
+ MemoryBase = PcdGet32(PcdEmbeddedFdBaseAddress) + PcdGet32(PcdEmbeddedFdSize);\r
+ }\r
+ \r
+ // We allocate all the remain memory as untested system memory\r
+ EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_TESTED);\r
+ EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = ARM_EB_DRAM_SZ - (MemoryBase-ARM_EB_DRAM_BASE);\r
+\r
+ EfiMemoryTable[++Index].ResourceAttribute = 0;\r
+ EfiMemoryTable[Index].PhysicalStart = 0;\r
+ EfiMemoryTable[Index].NumberOfBytes = 0;\r
+\r
+ *EfiMemoryMap = EfiMemoryTable;\r
+}\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmRealViewEbLib\r
+ FILE_GUID = 6e02ebe0-1d96-11e0-b9cb-0002a5d5c51b\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmPlatformLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ ArmLib\r
+\r
+[Sources.common]\r
+ ArmRealViewEb.c\r
+ ArmRealViewEbHelper.asm | RVCT\r
+ ArmRealViewEbHelper.S | GCC\r
+\r
+[Protocols]\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
+[FixedPcd]\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
--- /dev/null
+/** @file\r
+ Template for ArmEb DebugAgentLib. \r
+\r
+ For ARM we reserve FIQ for the Debug Agent Timer. We don't care about \r
+ laytency as we only really need the timer to run a few times a second \r
+ (how fast can some one type a ctrl-c?), but it works much better if\r
+ the interrupt we are using to break into the debugger is not being\r
+ used, and masked, by the system. \r
+\r
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+ \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+\r
+#include <Library/DebugAgentTimerLib.h>\r
+\r
+#include <ArmEb/ArmEb.h>\r
+\r
+\r
+/**\r
+ Setup all the hardware needed for the debug agents timer.\r
+\r
+ This function is used to set up debug enviroment. \r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DebugAgentTimerIntialize (\r
+ VOID\r
+ )\r
+{\r
+ // Map Timer to FIQ\r
+}\r
+ \r
+ \r
+/**\r
+ Set the period for the debug agent timer. Zero means disable the timer.\r
+\r
+ @param[in] TimerPeriodMilliseconds Frequency of the debug agent timer.\r
+\r
+**/ \r
+VOID\r
+EFIAPI\r
+DebugAgentTimerSetPeriod (\r
+ IN UINT32 TimerPeriodMilliseconds\r
+ )\r
+{\r
+ if (TimerPeriodMilliseconds == 0) {\r
+ // Disable timer and Disable FIQ\r
+ return;\r
+ } \r
+\r
+ // Set timer period and unmask FIQ\r
+}\r
+ \r
+\r
+/**\r
+ Perform End Of Interrupt for the debug agent timer. This is called in the \r
+ interrupt handler after the interrupt has been processed. \r
+\r
+**/ \r
+VOID\r
+EFIAPI\r
+DebugAgentTimerEndOfInterrupt (\r
+ VOID\r
+ )\r
+{\r
+ // EOI Timer interrupt for FIQ\r
+}\r
+ \r
+
\ No newline at end of file
--- /dev/null
+#/** @file\r
+# Component description file for Base PCI Cf8 Library.\r
+#\r
+# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.\r
+# Layers on top of an I/O Library instance.\r
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmEbDebugAgentTimerLib\r
+ FILE_GUID = 80949BBB-68EE-4a4c-B434-D5DB5A232F0C\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = DebugAgentTimerLib|SEC BASE DXE_CORE\r
+\r
+\r
+[Sources.common]\r
+ DebugAgentTimerLib.c\r
+\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+\r
--- /dev/null
+/** @file
+ Basic serial IO abstaction for GDB
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/GdbSerialLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Drivers/PL011Uart.h>
+
+RETURN_STATUS
+EFIAPI
+GdbSerialLibConstructor (
+ VOID
+ )
+{
+ return GdbSerialInit (115200, 0, 8, 1);
+}
+
+RETURN_STATUS
+EFIAPI
+GdbSerialInit (
+ IN UINT64 BaudRate,
+ IN UINT8 Parity,
+ IN UINT8 DataBits,
+ IN UINT8 StopBits
+ )
+{
+ if ((Parity != 0) || (DataBits != 8) || (StopBits != 1)) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ if (BaudRate != 115200) {
+ // Could add support for different Baud rates....
+ return RETURN_UNSUPPORTED;
+ }
+
+ UINT32 Base = PcdGet32 (PcdGdbUartBase);\r
+ \r
+ // initialize baud rate generator to 115200 based on EB clock REFCLK24MHZ\r
+ MmioWrite32 (Base + UARTIBRD, UART_115200_IDIV);\r
+ MmioWrite32 (Base + UARTFBRD, UART_115200_FDIV);\r
+\r
+ // no parity, 1 stop, no fifo, 8 data bits\r
+ MmioWrite32 (Base + UARTLCR_H, 0x60);\r
+\r
+ // clear any pending errors\r
+ MmioWrite32 (Base + UARTECR, 0);\r
+\r
+ // enable tx, rx, and uart overall\r
+ MmioWrite32 (Base + UARTCR, 0x301);\r
+\r
+ return RETURN_SUCCESS;\r
+}
+
+BOOLEAN
+EFIAPI
+GdbIsCharAvailable (
+ VOID
+ )
+{
+ UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;\r
+\r
+ if ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0) {\r
+ return TRUE;\r
+ } else {\r
+ return FALSE;\r
+ }\r
+}
+
+CHAR8
+EFIAPI
+GdbGetChar (
+ VOID
+ )
+{
+ UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;\r
+ UINT32 DR = PcdGet32 (PcdGdbUartBase) + UARTDR;\r
+ \r
+ while ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0);\r
+ return MmioRead8 (DR);\r
+}
+
+VOID
+EFIAPI
+GdbPutChar (
+ IN CHAR8 Char
+ )
+{
+ UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;\r
+ UINT32 DR = PcdGet32 (PcdGdbUartBase) + UARTDR;\r
+\r
+ while ((MmioRead32 (FR) & UART_TX_EMPTY_FLAG_MASK) != 0);\r
+ MmioWrite8 (DR, Char);\r
+ return;
+}
+
+VOID
+GdbPutString (
+ IN CHAR8 *String
+ )
+{
+ while (*String != '\0') {
+ GdbPutChar (*String);
+ String++;
+ }
+}
--- /dev/null
+#/** @file
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = GdbSerialLib
+ FILE_GUID = E8EA1309-2F14-428f-ABE3-7016CE4B4305
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = GdbSerialLib
+
+ CONSTRUCTOR = GdbSerialLibConstructor
+
+
+[Sources.common]
+ GdbSerialLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+
+[FixedPcd]
+
+ gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase
\ No newline at end of file
--- /dev/null
+/** @file\r
+ Template library implementation to support ResetSystem Runtime call.\r
+ \r
+ Fill in the templates with what ever makes you system reset.\r
+\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/EfiResetSystemLib.h>\r
+#include <Drivers/PL011Uart.h>\r
+\r
+/**\r
+ Resets the entire platform.\r
+\r
+ @param ResetType The type of reset to perform.\r
+ @param ResetStatus The status code for the reset.\r
+ @param DataSize The size, in bytes, of WatchdogData.\r
+ @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or\r
+ EfiResetShutdown the data buffer starts with a Null-terminated\r
+ Unicode string, optionally followed by additional binary data.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibResetSystem (\r
+ IN EFI_RESET_TYPE ResetType,\r
+ IN EFI_STATUS ResetStatus,\r
+ IN UINTN DataSize,\r
+ IN CHAR16 *ResetData OPTIONAL\r
+ )\r
+{\r
+ if (ResetData != NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%s", ResetData));\r
+ }\r
+\r
+ switch (ResetType) {\r
+ case EfiResetWarm:\r
+ // Map a warm reset into a cold reset\r
+ case EfiResetCold:\r
+ case EfiResetShutdown:\r
+ default:\r
+ CpuDeadLoop ();\r
+ break;\r
+ }\r
+\r
+ // If the reset didn't work, return an error.\r
+ ASSERT (FALSE);\r
+ return EFI_DEVICE_ERROR;\r
+}\r
+ \r
+\r
+\r
+/**\r
+ Initialize any infrastructure required for LibResetSystem () to function.\r
+\r
+ @param ImageHandle The firmware allocated handle for the EFI image.\r
+ @param SystemTable A pointer to the EFI System Table.\r
+ \r
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibInitializeResetSystem (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+#/** @file\r
+# Reset System lib to make it easy to port new platforms\r
+#\r
+# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmEbResetSystemLib\r
+ FILE_GUID = CEFFA65C-B568-453e-9E11-B81AE683D035\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = EfiResetSystemLib\r
+\r
+\r
+[Sources.common]\r
+ ResetSystemLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ BaseLib\r
--- /dev/null
+#------------------------------------------------------------------------------ \r
+#\r
+# ARM EB Entry point. Reset vector in FV header will brach to\r
+# _ModuleEntryPoint. \r
+#\r
+# We use crazy macros, like LoadConstantToReg, since Xcode assembler \r
+# does not support = assembly syntax for ldr.\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmEb/ArmEb.h>\r
+\r
+.text\r
+.align 3\r
+\r
+.globl ASM_PFX(CEntryPoint)\r
+.globl ASM_PFX(_ModuleEntryPoint)\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+ \r
+ // Turn off remapping NOR to 0. We can now use DRAM in low memory\r
+ // CAN'T DO THIS HERE -- BRANCH FROM RESET VECTOR IS RELATIVE AND REMAINS IN REMAPPED NOR\r
+ //MmioOr32 (EB_SP810_CTRL_BASE ,BIT8) \r
+\r
+ // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ mov r0, #0x40000000 // Set EN bit in FPEXC\r
+ mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly\r
+ \r
+ // Set CPU vectors to 0 (which is currently flash)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r
+ mcr p15, 0, r0, c12, c0, 0\r
+ isb // Sync changes to control registers\r
+\r
+ //\r
+ // Set stack based on PCD values. Need to do it this way to make C code work \r
+ // when it runs from FLASH. \r
+ // \r
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2 \r
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3 \r
+ add r4, r2, r3\r
+ mov r13, r4\r
+\r
+ // Call C entry point\r
+ LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1 \r
+ LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory size arg0 \r
+ blx ASM_PFX(CEntryPoint) \r
+\r
+ShouldNeverGetHere:\r
+ // _CEntryPoint should never return \r
+ b ShouldNeverGetHere\r
+\r
+ \r
--- /dev/null
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmEb/ArmEb.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ IMPORT CEntryPoint\r
+ EXPORT _ModuleEntryPoint\r
+ \r
+ PRESERVE8\r
+ AREA ModuleEntryPoint, CODE, READONLY\r
+ \r
+\r
+StartupAddr DCD CEntryPoint\r
+\r
+_ModuleEntryPoint\r
+ \r
+ // Turn off remapping NOR to 0. We can now use DRAM in low memory\r
+ // CAN'T DO THIS HERE -- BRANCH FROM RESET VECTOR IS RELATIVE AND REMAINS IN REMAPPED NOR\r
+ //MmioOr32 (0x10001000 ,BIT8) //EB_SP810_CTRL_BASE\r
+\r
+ // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ orr r0, r0, #0x00f00000 // Enable VFP access (V* instructions)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ mov r0, #0x40000000 // Set EN bit in FPEXC\r
+ mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly\r
+ \r
+ // Set CPU vectors to 0 (which is currently flash)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r
+ mcr p15, 0, r0, c12, c0, 0\r
+ isb // Sync changes to control registers\r
+\r
+ //\r
+ // Set stack based on PCD values. Need to do it this way to make C code work \r
+ // when it runs from FLASH. \r
+ // \r
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2 \r
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3 \r
+ add r4, r2, r3\r
+ mov r13, r4\r
+ \r
+ LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1 \r
+ LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory size arg0 \r
+\r
+ // move sec startup address into a data register\r
+ // ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r4, StartupAddr\r
+\r
+ // jump to SEC C code\r
+ blx r4\r
+ \r
+ // Call C entry point\r
+ // THIS DOESN'T WORK, WE NEED A LONG JUMP\r
+ \r
+ // blx CEntryPoint \r
+\r
+ShouldNeverGetHere\r
+ // _CEntryPoint should never return \r
+ b ShouldNeverGetHere\r
+ \r
+ END\r
+\r
+\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/PrePiLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+\r
+// SoC registers. L3 interconnects\r
+#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000\r
+#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000\r
+#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
+\r
+// SoC registers. L4 interconnects\r
+#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000\r
+#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000\r
+#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
+\r
+VOID\r
+InitCache (\r
+ IN UINT32 MemoryBase,\r
+ IN UINT32 MemoryLength\r
+ )\r
+{\r
+ UINT32 CacheAttributes;\r
+ ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[5];\r
+ VOID *TranslationTableBase;\r
+ UINTN TranslationTableSize;\r
+\r
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
+ } else {\r
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
+ }\r
+\r
+ // DDR\r
+ MemoryTable[0].PhysicalBase = MemoryBase;\r
+ MemoryTable[0].VirtualBase = MemoryBase;\r
+ MemoryTable[0].Length = MemoryLength;\r
+ MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // SOC Registers. L3 interconnects\r
+ MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+ MemoryTable[1].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+ MemoryTable[1].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
+ MemoryTable[1].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;\r
+ \r
+ // SOC Registers. L4 interconnects\r
+ MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+ MemoryTable[2].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+ MemoryTable[2].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
+ MemoryTable[2].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;\r
+\r
+ // End of Table\r
+ MemoryTable[3].PhysicalBase = 0;\r
+ MemoryTable[3].VirtualBase = 0;\r
+ MemoryTable[3].Length = 0;\r
+ MemoryTable[3].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+ \r
+ ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
+ \r
+ BuildMemoryAllocationHob ((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r
+}\r
--- /dev/null
+/** @file\r
+ LZMA Decompress Library header file\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __LZMA_DECOMPRESS_H___\r
+#define __LZMA_DECOMPRESS_H___\r
+\r
+/**\r
+ Examines a GUIDed section and returns the size of the decoded buffer and the\r
+ size of an scratch buffer required to actually decode the data in a GUIDed section.\r
+\r
+ Examines a GUIDed section specified by InputSection. \r
+ If GUID for InputSection does not match the GUID that this handler supports,\r
+ then RETURN_UNSUPPORTED is returned. \r
+ If the required information can not be retrieved from InputSection,\r
+ then RETURN_INVALID_PARAMETER is returned.\r
+ If the GUID of InputSection does match the GUID that this handler supports,\r
+ then the size required to hold the decoded buffer is returned in OututBufferSize,\r
+ the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field\r
+ from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute.\r
+ \r
+ If InputSection is NULL, then ASSERT().\r
+ If OutputBufferSize is NULL, then ASSERT().\r
+ If ScratchBufferSize is NULL, then ASSERT().\r
+ If SectionAttribute is NULL, then ASSERT().\r
+\r
+\r
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.\r
+ @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required\r
+ if the buffer specified by InputSection were decoded.\r
+ @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space\r
+ if the buffer specified by InputSection were decoded.\r
+ @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes\r
+ field of EFI_GUID_DEFINED_SECTION in the PI Specification.\r
+\r
+ @retval RETURN_SUCCESS The information about InputSection was returned.\r
+ @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.\r
+ @retval RETURN_INVALID_PARAMETER The information can not be retrieved from the section specified by InputSection.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+LzmaGuidedSectionGetInfo (\r
+ IN CONST VOID *InputSection,\r
+ OUT UINT32 *OutputBufferSize,\r
+ OUT UINT32 *ScratchBufferSize,\r
+ OUT UINT16 *SectionAttribute\r
+ );\r
+\r
+/**\r
+ Decompress a LZAM compressed GUIDed section into a caller allocated output buffer.\r
+ \r
+ Decodes the GUIDed section specified by InputSection. \r
+ If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned. \r
+ If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned.\r
+ If the GUID of InputSection does match the GUID that this handler supports, then InputSection\r
+ is decoded into the buffer specified by OutputBuffer and the authentication status of this\r
+ decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the\r
+ data in InputSection, then OutputBuffer is set to point at the data in InputSection. Otherwise,\r
+ the decoded data will be placed in caller allocated buffer specified by OutputBuffer.\r
+ \r
+ If InputSection is NULL, then ASSERT().\r
+ If OutputBuffer is NULL, then ASSERT().\r
+ If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().\r
+ If AuthenticationStatus is NULL, then ASSERT().\r
+\r
+\r
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.\r
+ @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation. \r
+ @param[out] ScratchBuffer A caller allocated buffer that may be required by this function\r
+ as a scratch buffer to perform the decode operation. \r
+ @param[out] AuthenticationStatus \r
+ A pointer to the authentication status of the decoded output buffer.\r
+ See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI\r
+ section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must\r
+ never be set by this handler.\r
+\r
+ @retval RETURN_SUCCESS The buffer specified by InputSection was decoded.\r
+ @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.\r
+ @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+LzmaGuidedSectionExtraction (\r
+ IN CONST VOID *InputSection,\r
+ OUT VOID **OutputBuffer,\r
+ OUT VOID *ScratchBuffer, OPTIONAL\r
+ OUT UINT32 *AuthenticationStatus\r
+ );\r
+ \r
+#endif // __LZMADECOMPRESS_H__\r
+\r
--- /dev/null
+#------------------------------------------------------------------------------ \r
+#\r
+# ARM EB Entry point. Reset vector in FV header will brach to\r
+# _ModuleEntryPoint. \r
+#\r
+# We use crazy macros, like LoadConstantToReg, since Xcode assembler \r
+# does not support = assembly syntax for ldr.\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmEb/ArmEb.h>\r
+\r
+.text\r
+.align 3\r
+\r
+.globl ASM_PFX(CEntryPoint)\r
+.globl ASM_PFX(_ModuleEntryPoint)\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+ \r
+ // Turn off remapping NOR to 0. We can now use DRAM in low memory\r
+ // CAN'T DO THIS HERE -- BRANCH FROM RESET VECTOR IS RELATIVE AND REMAINS IN REMAPPED NOR\r
+ //MmioOr32 (EB_SP810_CTRL_BASE ,BIT8) \r
+\r
+ // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ mov r0, #0x40000000 // Set EN bit in FPEXC\r
+ mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly\r
+ \r
+ // Set CPU vectors to 0 (which is currently flash)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r
+ mcr p15, 0, r0, c12, c0, 0\r
+ isb // Sync changes to control registers\r
+\r
+ //\r
+ // Set stack based on PCD values. Need to do it this way to make C code work \r
+ // when it runs from FLASH. \r
+ // \r
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2 \r
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3 \r
+ add r4, r2, r3\r
+ mov r13, r4\r
+\r
+ // Call C entry point\r
+ LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1 \r
+ LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory size arg0 \r
+ blx ASM_PFX(CEntryPoint) \r
+\r
+ShouldNeverGetHere:\r
+ // _CEntryPoint should never return \r
+ b ShouldNeverGetHere\r
+\r
+ \r
--- /dev/null
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmEb/ArmEb.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ IMPORT CEntryPoint\r
+ EXPORT _ModuleEntryPoint\r
+ \r
+ PRESERVE8\r
+ AREA ModuleEntryPoint, CODE, READONLY\r
+ \r
+\r
+StartupAddr DCD CEntryPoint\r
+\r
+_ModuleEntryPoint\r
+ \r
+ // Turn off remapping NOR to 0. We can now use DRAM in low memory\r
+ // CAN'T DO THIS HERE -- BRANCH FROM RESET VECTOR IS RELATIVE AND REMAINS IN REMAPPED NOR\r
+ //MmioOr32 (0x10001000 ,BIT8) //EB_SP810_CTRL_BASE\r
+\r
+ // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ orr r0, r0, #0x00f00000 // Enable VFP access (V* instructions)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ mov r0, #0x40000000 // Set EN bit in FPEXC\r
+ mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly\r
+ \r
+ // Set CPU vectors to 0 (which is currently flash)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r
+ mcr p15, 0, r0, c12, c0, 0\r
+ isb // Sync changes to control registers\r
+\r
+ //\r
+ // Set stack based on PCD values. Need to do it this way to make C code work \r
+ // when it runs from FLASH. \r
+ // \r
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2 \r
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3 \r
+ add r4, r2, r3\r
+ mov r13, r4\r
+ \r
+ LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1 \r
+ LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory size arg0 \r
+\r
+ // move sec startup address into a data register\r
+ // ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r4, StartupAddr\r
+\r
+ // jump to SEC C code\r
+ blx r4\r
+ \r
+ // Call C entry point\r
+ // THIS DOESN'T WORK, WE NEED A LONG JUMP\r
+ \r
+ // blx CEntryPoint \r
+\r
+ShouldNeverGetHere\r
+ // _CEntryPoint should never return \r
+ b ShouldNeverGetHere\r
+ \r
+ END\r
+\r
+\r
--- /dev/null
+/** @file\r
+ C Entry point for the SEC. First C code after the reset vector.\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/PrePiLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/DebugAgentLib.h>\r
+\r
+#include <Ppi/GuidedSectionExtraction.h>\r
+#include <Guid/LzmaDecompress.h>\r
+\r
+#include <ArmEb/ArmEb.h>\r
+\r
+#include "LzmaDecompress.h"\r
+\r
+VOID\r
+EFIAPI \r
+_ModuleEntryPoint(\r
+ VOID\r
+ );\r
+\r
+CHAR8 *\r
+DeCygwinPathIfNeeded (\r
+ IN CHAR8 *Name\r
+ );\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+SerialPortInitialize (\r
+ VOID\r
+ );\r
+ \r
+ \r
+VOID\r
+UartInit (\r
+ VOID\r
+ )\r
+{\r
+ // SEC phase needs to run library constructors by hand.\r
+ // This assumes we are linked agains the SerialLib\r
+ // In non SEC modules the init call is in autogenerated code.\r
+ SerialPortInitialize ();\r
+}\r
+\r
+VOID\r
+TimerInit (\r
+ VOID\r
+ )\r
+{\r
+ // configure SP810 to use 1MHz clock and disable\r
+ MmioAndThenOr32 (EB_SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r
+ // Enable\r
+ MmioOr32 (EB_SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER2_EN);\r
+\r
+ // configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled\r
+ MmioOr32 (EB_SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);\r
+\r
+ // preload the timer count register\r
+ MmioWrite32 (EB_SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1);\r
+\r
+ // enable the timer\r
+ MmioOr32 (EB_SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);\r
+}\r
+\r
+\r
+VOID\r
+InitCache (\r
+ IN UINT32 MemoryBase,\r
+ IN UINT32 MemoryLength\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ExtractGuidedSectionLibConstructor (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+LzmaDecompressLibConstructor (\r
+ VOID\r
+ );\r
+\r
+\r
+VOID\r
+CEntryPoint (\r
+ IN VOID *MemoryBase,\r
+ IN UINTN MemorySize,\r
+ IN VOID *StackBase,\r
+ IN UINTN StackSize\r
+ )\r
+{\r
+ VOID *HobBase;\r
+\r
+ // HOB list is at bottom of stack area\r
+ // Stack grows from top-to-bottom towards HOB list\r
+ HobBase = (VOID *)StackBase;\r
+ CreateHobList (MemoryBase, MemorySize, HobBase, StackBase);\r
+\r
+ // Turn off remapping NOR to 0. We can will now see DRAM in low memory\r
+ MmioOr32 (0x10001000 ,BIT8); //EB_SP810_CTRL_BASE\r
+\r
+ // Enable program flow prediction, if supported.\r
+ ArmEnableBranchPrediction ();\r
+\r
+ // Initialize CPU cache\r
+ InitCache ((UINT32)MemoryBase, (UINT32)MemorySize);\r
+\r
+ // Add memory allocation hob for relocated FD\r
+ BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r
+\r
+ // Add the FVs to the hob list\r
+ BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r
+\r
+ // Start talking\r
+ UartInit ();\r
+\r
+ InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);\r
+ SaveAndSetDebugTimerInterrupt (TRUE);\r
+\r
+ DEBUG ((EFI_D_ERROR, "UART Enabled\n"));\r
+\r
+ // Start up a free running timer so that the timer lib will work\r
+ TimerInit ();\r
+\r
+ // SEC phase needs to run library constructors by hand.\r
+ ExtractGuidedSectionLibConstructor ();\r
+ LzmaDecompressLibConstructor ();\r
+\r
+ // Build HOBs to pass up our version of stuff the DXE Core needs to save space\r
+ BuildPeCoffLoaderHob ();\r
+ BuildExtractSectionHob (\r
+ &gLzmaCustomDecompressGuid,\r
+ LzmaGuidedSectionGetInfo,\r
+ LzmaGuidedSectionExtraction\r
+ );\r
+\r
+ // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r
+ DecompressFirstFv ();\r
+\r
+ // Load the DXE Core and transfer control to it\r
+ LoadDxeCoreFromFv (NULL, 0);\r
+ \r
+ // DXE Core should always load and never return\r
+ ASSERT (FALSE);\r
+}\r
+\r
--- /dev/null
+
+#/** @file
+# SEC - Reset vector code that jumps to C and loads DXE core
+#
+# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmEBSec
+ FILE_GUID = d959e387-7b91-452c-90e0-a1dbac90ddb8
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+
+
+[Sources.ARM]
+ ModuleEntryPoint.S | GCC
+ ModuleEntryPoint.asm | RVCT
+
+[Sources.ARM]
+ Sec.c
+ Cache.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dec
+
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ ArmLib
+ IoLib
+ ExtractGuidedSectionLib
+ LzmaDecompressLib
+ PeCoffGetEntryPointLib
+ DebugAgentLib
+
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
+ gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
+ gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+ gEmbeddedTokenSpaceGuid.PcdPrePiStackSize
+ gEmbeddedTokenSpaceGuid.PcdPrePiStackBase
+ gEmbeddedTokenSpaceGuid.PcdMemoryBase
+ gEmbeddedTokenSpaceGuid.PcdMemorySize
+
+
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
+
+
--- /dev/null
+@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+@REM This program and the accompanying materials\r
+@REM are licensed and made available under the terms and conditions of the BSD License\r
+@REM which accompanies this distribution. The full text of the license may be found at\r
+@REM http://opensource.org/licenses/bsd-license.php\r
+@REM\r
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+@REM\r
+\r
+@REM Example usage of this script. default is a DEBUG build\r
+@REM b\r
+@REM b clean\r
+@REM b release \r
+@REM b release clean\r
+@REM b -v -y build.log\r
+\r
+ECHO OFF\r
+@REM Setup Build environment. Sets WORKSPACE and puts build in path\r
+CALL ..\edksetup.bat\r
+\r
+@REM Set for tools chain. Currently RVCT31\r
+SET TARGET_TOOLS=RVCT31\r
+SET TARGET=DEBUG\r
+\r
+@if /I "%1"=="RELEASE" (\r
+ @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it \r
+ SET TARGET=RELEASE\r
+ shift /1\r
+)\r
+\r
+SET BUILD_ROOT=%WORKSPACE%\Build\ArmRealViewEb\%TARGET%_%TARGET_TOOLS%\r
+\r
+@REM Build the ARM RealView EB firmware and creat an FD (FLASH Device) Image.\r
+CALL build -p ArmRealViewEbPkg\ArmRealViewEbPkg.dsc -a ARM -t RVCT31 -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8\r
+@if ERRORLEVEL 1 goto Exit\r
+\r
+@if /I "%1"=="CLEAN" goto Clean\r
+\r
+:Exit\r
+EXIT /B\r
+\r
+:Clean\r
--- /dev/null
+@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+@REM This program and the accompanying materials
+@REM are licensed and made available under the terms and conditions of the BSD License
+@REM which accompanies this distribution. The full text of the license may be found at
+@REM http://opensource.org/licenses/bsd-license.php
+@REM
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+@REM
+
+@REM Example usage of this script. default is a DEBUG build
+@REM b
+@REM b clean
+@REM b release
+@REM b release clean
+@REM b -v -y build.log
+
+ECHO OFF
+@REM Setup Build environment. Sets WORKSPACE and puts build in path
+CALL ..\edksetup.bat
+
+@REM Set for tools chain. Currently ARMGCC
+SET TARGET_TOOLS=ARMGCC
+SET TARGET=DEBUG
+
+
+@if /I "%1"=="RELEASE" (
+
+ @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it
+
+ SET TARGET=RELEASE
+
+ shift /1
+
+)
+
+
+SET BUILD_ROOT=%WORKSPACE%\Build\ArmRealViewEb\%TARGET%_%TARGET_TOOLS%
+
+@REM Build the ARM RealView EB firmware and creat an FD (FLASH Device) Image.
+CALL build -p ArmRealViewEbPkg\ArmRealViewEbPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8
+@if ERRORLEVEL 1 goto Exit
+
+@if /I "%1"=="CLEAN" goto Clean
+
+
+ECHO Patching ..\Debugger_scripts ...
+SET DEBUGGER_SCRIPT=Debugger_scripts
+@for /f %%a IN ('dir /b %DEBUGGER_SCRIPT%\*.inc %DEBUGGER_SCRIPT%\*.cmm') do (
+ @CALL replace %DEBUGGER_SCRIPT%\%%a %BUILD_ROOT%\%%a ZZZZZZ %BUILD_ROOT% WWWWWW %WORKSPACE%
+)
+
+:Exit
+EXIT /B
+
+:Clean
--- /dev/null
+#!/bin/bash
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+set -e
+shopt -s nocasematch
+
+function process_debug_scripts {
+ if [[ -d $1 ]]; then
+ for filename in `ls $1`
+ do
+ sed -e "s@ZZZZZZ@$BUILD_ROOT@g" -e "s@WWWWWW@$WORKSPACE@g" \
+ "$1/$filename" \
+ > "$BUILD_ROOT/$filename"
+
+ #For ARMCYGWIN, we have to change /cygdrive/c to c:
+ if [[ $TARGET_TOOLS == RVCT31CYGWIN ]]
+ then
+ mv "$BUILD_ROOT/$filename" "$BUILD_ROOT/$filename"_temp
+ sed -e "s@/cygdrive/\(.\)@\1:@g" \
+ "$BUILD_ROOT/$filename"_temp \
+ > "$BUILD_ROOT/$filename"
+ rm -f "$BUILD_ROOT/$filename"_temp
+ fi
+ done
+ fi
+}
+
+
+#
+# Setup workspace if it is not set
+#
+if [ -z "$WORKSPACE" ]
+then
+ echo Initializing workspace
+ cd ..
+ export EDK_TOOLS_PATH=`pwd`/BaseTools
+ source edksetup.sh BaseTools
+else
+ echo Building from: $WORKSPACE
+fi
+
+#
+# Pick a default tool type for a given OS
+#
+case `uname` in
+ CYGWIN*)
+ TARGET_TOOLS=RVCT31CYGWIN
+ ;;
+ Linux*)
+ # Not tested
+ TARGET_TOOLS=ARMGCC
+ ;;
+ Darwin*)
+ Major=$(uname -r | cut -f 1 -d '.')
+ if [[ $Major == 9 ]]
+ then
+ # Not supported by this open source project
+ TARGET_TOOLS=XCODE31
+ else
+ TARGET_TOOLS=XCODE32
+ fi
+ ;;
+esac
+
+TARGET=DEBUG
+for arg in "$@"
+do
+ if [[ $arg == RELEASE ]];
+ then
+ TARGET=RELEASE
+ fi
+done
+
+BUILD_ROOT=$WORKSPACE/Build/ArmRealViewEb/"$TARGET"_"$TARGET_TOOLS"
+
+if [[ ! -e $EDK_TOOLS_PATH/Source/C/bin ]];
+then
+ # build the tools if they don't yet exist
+ echo Building tools: $EDK_TOOLS_PATH
+ make -C $EDK_TOOLS_PATH
+else
+ echo using prebuilt tools
+fi
+
+#
+# Build the edk2 ArmEb code
+#
+if [[ $TARGET == RELEASE ]]; then
+ build -p $WORKSPACE/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dsc -a ARM -t $TARGET_TOOLS -b $TARGET -D DEBUG_TARGET=RELEASE $2 $3 $4 $5 $6 $7 $8
+else
+ build -p $WORKSPACE/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEbPkg.dsc -a ARM -t $TARGET_TOOLS -b $TARGET $1 $2 $3 $4 $5 $6 $7 $8
+fi
+
+
+for arg in "$@"
+do
+ if [[ $arg == clean ]]; then
+ # no need to post process if we are doing a clean
+ exit
+ elif [[ $arg == cleanall ]]; then
+ make -C $EDK_TOOLS_PATH clean
+ exit
+
+ fi
+done
+
+
+echo Creating debugger scripts
+process_debug_scripts $WORKSPACE/ArmPlatformPkg/ArmRealViewEbPkg/Debugger_scripts
+
--- /dev/null
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmVExpressPkg-CTA9x4
+ PLATFORM_GUID = eb2bd5ff-2379-4a06-9c12-db905cdee9ea
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+!if $(EDK2_ARMVE_STANDALONE) == 1
+ OUTPUT_DIRECTORY = Build/ArmVExpress-CTA9x4-Standalone
+!else
+ OUTPUT_DIRECTORY = Build/ArmVExpress-CTA9x4
+!endif
+ SUPPORTED_ARCHITECTURES = ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf
+
+[LibraryClasses.common]
+!if $(BUILD_TARGETS) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+# UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+!endif
+
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
+ ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
+ ArmMPCoreMailBoxLib|ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBoxLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+
+ EfiResetSystemLib|ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+
+ EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf
+ EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+# PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+# PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+
+ RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+
+ # ARM PL341 DMC Driver
+ PL341DmcLib|ArmPkg/Drivers/PL34xDmc/PL341Dmc.inf
+ # ARM PL301 Axi Driver
+ PL301AxiLib|ArmPkg/Drivers/PL301Axi/PL301Axi.inf
+
+#
+# Assume everything is fixed at build
+#
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
+
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+ EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
+
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+ TimerLib|ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+
+ BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
+
+ # 1/123 faster than Stm or Vstm version
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+ # Uncomment to turn on GDB stub in SEC.
+ #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+
+ # ARM PL354 SMC Driver
+ PL354SmcSecLib|ArmPkg/Drivers/PL35xSmc/PL354SmcSec.inf
+ # ARM PL310 L2 Cache Driver
+ L2X0CacheLib|ArmPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf
+ # ARM PL390 General Interrupt Driver in Secure and Non-secure
+ PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
+ PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+
+[LibraryClasses.common.PEI_CORE]
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ # note: this won't actually work since globals in PEI are not writeable
+ # need to generate an ARM PEI services table pointer implementation
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.PEIM]
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ # note: this won't actually work since globals in PEI are not writeable
+ # need to generate an ARM PEI services table pointer implementation
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+# PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[BuildOptions]
+ RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A9 --thumb -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+ RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A9 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+
+ ARMGCC:*_*_ARM_ARCHCC_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+ ARMGCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ #
+ # Control what commands are supported from the UI
+ # Turn these on and off to add features or save size
+ #
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+!if $(EDK2_ARMVE_STANDALONE) == 1
+ gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE
+!endif
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE
+!endif
+
+[PcdsFixedAtBuild.common]
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress %a"
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+# DEBUG_ASSERT_ENABLED 0x01
+# DEBUG_PRINT_ENABLED 0x02
+# DEBUG_CODE_ENABLED 0x04
+# CLEAR_MEMORY_ENABLED 0x08
+# ASSERT_BREAKPOINT_ENABLED 0x10
+# ASSERT_DEADLOOP_ENABLED 0x20
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+
+# DEBUG_INIT 0x00000001 // Initialization
+# DEBUG_WARN 0x00000002 // Warnings
+# DEBUG_LOAD 0x00000004 // Load events
+# DEBUG_FS 0x00000008 // EFI File system
+# DEBUG_POOL 0x00000010 // Alloc & Free's
+# DEBUG_PAGE 0x00000020 // Alloc & Free's
+# DEBUG_INFO 0x00000040 // Verbose
+# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+# DEBUG_VARIABLE 0x00000100 // Variable
+# DEBUG_BM 0x00000400 // Boot Manager
+# DEBUG_BLKIO 0x00001000 // BlkIo Driver
+# DEBUG_NET 0x00004000 // SNI Driver
+# DEBUG_UNDI 0x00010000 // UNDI Driver
+# DEBUG_LOADFILE 0x00020000 // UNDI Driver
+# DEBUG_EVENT 0x00080000 // Event messages
+# DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+#
+# Optional feature to help prevent EFI memory map fragments
+# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+# Values are in EFI Pages (4K). DXE Core will make sure that
+# at least this much of each type of memory can be allocated
+# from a single memory range. This way you only end up with
+# maximum of two fragements for each type in the memory map
+# (the memory used, and the free memory that was prereserved
+# but not used).
+#
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+ # Stacks for MPCores in Secure World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x49E00000 # Top of SEC Stack for Secure World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Stack for each of the 4 CPU cores
+
+ # Stacks for MPCores in Monitor Mode
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x49D00000 # Top of SEC Stack for Monitor World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x2000 # Stack for each of the 4 CPU cores
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x00020000 # Stack for each of the 4 CPU cores
+ gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # pei services ptr just above stack. Overlapped with the stack of CoreId 1
+
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+
+ #
+ # ARM Pcds
+ #
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+ #
+ # ARM PrimeCell
+ #
+ gArmTokenSpaceGuid.PcdPL180SysMciRegAddress|0x10000048
+ gArmTokenSpaceGuid.PcdPL180MciBaseAddress|0x10005000
+
+ #
+ # ARM PL390 General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x1e001000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x1e000100
+
+ #
+ # ARM OS Loader
+ #
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+ gArmTokenSpaceGuid.PcdArmMachineType|2272
+ gArmTokenSpaceGuid.PcdLinuxKernelDP|L"VenHw(02118005-9DA7-443a-92D5-781F022AEDBB)/MemoryMapped(0,0x46000000,0x46400000)"
+ gArmTokenSpaceGuid.PcdLinuxAtag|"rdinit=/bin/ash debug earlyprintk console=ttyAMA0,38400 mem=1G"
+ gArmTokenSpaceGuid.PcdFdtDP|L""
+
+ #
+ # ARM PL111 Colour LCD Controller
+ #
+ gArmVExpressTokenSpaceGuid.PcdPL111RegistersBaseMotherboard|0x1001F000
+ gArmVExpressTokenSpaceGuid.PcdPL111RegistersBaseDaughterboard|0x10020000
+ gArmVExpressTokenSpaceGuid.PcdPL111VRamBaseMotherboard|0x4C000000
+ gArmVExpressTokenSpaceGuid.PcdPL111VRamBaseDaughterboard|0x64000000
+ gArmVExpressTokenSpaceGuid.PcdPL111VRamSize|0x800000
+
+ #
+ # ARM L2x0 PCDs
+ #
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1E00A000
+
+ #
+ # ARM VE MP Core Mailbox
+ #
+ gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0x10000030
+ gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0x10000030
+ gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0x10000034
+ gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0xFFFFFFFF
+
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+#
+# SEC
+#
+ ArmPlatformPkg/Sec/Sec.inf
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+
+#
+# PEI Phase modules
+#
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPei.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ Nt32Pkg/BootModePei/BootModePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+#
+# DXE
+#
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
+ ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashDxe.inf
+ ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ ArmPkg/Universal/MmcDxe/MmcDxe.inf
+ ArmPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Application
+ #
+ EmbeddedPkg/Ebl/Ebl.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ ArmPlatformPkg/Bds/Bds.inf
--- /dev/null
+# FLASH layout file for ARM VE.
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.Sec_ArmVExpress_EFI]
+BaseAddress = 0x44000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress #The base address of the Secure FLASH Device.
+Size = 0x00200000|gArmTokenSpaceGuid.PcdSecureFdSize #The size in bytes of the Secure FLASH Device
+ErasePolarity = 1
+BlockSize = 0x00001000
+NumBlocks = 0x200
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize
+FV = FVMAIN_SEC
+
+
+[FD.ArmVExpress_EFI]
+!if $(EDK2_ARMVE_STANDALONE) == 1
+BaseAddress = 0x45000000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress # The base address of the Firmware in NOR Flash.
+!else
+BaseAddress = 0x80000000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress # The base address of the Firmware in remapped DRAM.
+!endif
+Size = 0x00200000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x200
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+
+[FD.NVVariableStore]
+BaseAddress = 0x47FC0000
+Size = 0x00030000
+ErasePolarity = 1
+BlockSize = 0x00010000
+NumBlocks = 0x3
+
+0x00000000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x30000
+ 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ #Signature "_FVH" #Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x34, 0x09, 0x00, 0x00, 0x00, 0x02,
+ #Blockmap[0]: 3 Blocks * 0x10000 Bytes / Block
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ #Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ ## This is the VARIABLE_STORE_HEADER
+ #Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ #Size: 0x10000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER: HeaderLength) = 0xFFB8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x00, 0x00,
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00010000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#FTW_SPARE_STORE - See EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER
+DATA = {
+ #Signature: gEfiSystemNvDataFvGuid =
+ # { 0xfff12b8d, 0x7696, 0x4c8b, { 0xa9, 0x85, 0x27, 0x47, 0x07, 0x5b, 0x4f, 0x50 } }
+ 0x8d, 0x2b, 0xf1, 0xff, 0x96, 0x32, 0x8b, 0x4c,
+ 0xa9, 0x85, 0x27, 0x47, 0x07, 0x5b, 0x4f, 0x50,
+ #FIXME: 32bit CRC caculated for this header.
+ 0x00, 0x00, 0x00, 0x00,
+ # Working block valid bit
+ 0x00,
+ # Total size of the following write queue range. (64bit)
+ 0xB8, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ # Write Queue data: EFI_FAULT_TOLERANT_WRITE_HEADER
+ # State
+ 0x00,
+ # CallerId: Guid
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # NumberOfWrites, PrivateDataSize
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00020000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+DATA = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
+ INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+ INF ArmPlatformPkg/ArmVExpressPkg/NorFlashDxe/NorFlashDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ INF ArmPkg/Universal/MmcDxe/MmcDxe.inf
+ INF ArmPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF EmbeddedPkg/Ebl/Ebl.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF ArmPlatformPkg/Bds/Bds.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional |.depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 |.efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 8 |.efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE |.efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ TE TE |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 |.efi
+ }
--- /dev/null
+#/** @file
+# Arm Versatile Express package.
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = ArmVExpressPkg
+ PACKAGE_GUID = 9c0aaed4-74c5-4043-b417-a3223814ce76
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
+[Guids.common]
+ gArmVExpressTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
+
+[PcdsFeatureFlag.common]
+
+[PcdsFixedAtBuild.common]
--- /dev/null
+/** @file\r
+* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#ifndef __ARM_VEXPRESS_H__\r
+#define __ARM_VEXPRESS_H__\r
+\r
+/*******************************************\r
+// Platform Memory Map\r
+*******************************************/\r
+\r
+// Can be NOR0, NOR1, DRAM\r
+#define ARM_VE_REMAP_BASE 0x00000000\r
+#define ARM_VE_REMAP_SZ 0x04000000\r
+\r
+// Motherboard Peripheral and On-chip peripheral\r
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ 0x10000000 /* 256 MB */\r
+#define ARM_VE_BOARD_PERIPH_BASE 0x10000000\r
+#define ARM_VE_CHIP_PERIPH_BASE 0x10020000\r
+\r
+// SMC\r
+#define ARM_VE_SMC_BASE 0x40000000\r
+#define ARM_VE_SMC_SZ 0x1C000000\r
+\r
+// NOR Flash 1\r
+#define ARM_VE_SMB_NOR0_BASE 0x40000000\r
+#define ARM_VE_SMB_NOR0_SZ 0x04000000 /* 64 MB */\r
+// NOR Flash 2\r
+#define ARM_VE_SMB_NOR1_BASE 0x44000000\r
+#define ARM_VE_SMB_NOR1_SZ 0x04000000 /* 64 MB */\r
+// SRAM\r
+#define ARM_VE_SMB_SRAM_BASE 0x48000000\r
+#define ARM_VE_SMB_SRAM_SZ 0x02000000 /* 32 MB */\r
+// USB, Ethernet, VRAM\r
+#define ARM_VE_SMB_PERIPH_BASE 0x4C000000\r
+#define ARM_VE_SMB_PERIPH_VRAM 0x4C000000\r
+#define ARM_VE_SMB_PERIPH_SZ 0x04000000 /* 32 MB */\r
+\r
+// DRAM\r
+#define ARM_VE_DRAM_BASE 0x60000000\r
+#define ARM_VE_DRAM_SZ 0x40000000\r
+\r
+// External AXI between daughterboards (Logic Tile)\r
+#define ARM_VE_EXT_AXI_BASE 0xE0000000\r
+#define ARM_VE_EXT_AXI_SZ 0x20000000\r
+\r
+/*******************************************\r
+// Motherboard peripherals\r
+*******************************************/\r
+\r
+// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r
+#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r
+#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r
+#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r
+#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r
+#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r
+#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r
+#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r
+\r
+// SP810 Controller\r
+#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r
+\r
+// Uart0\r
+#define PL011_CONSOLE_UART_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x09000)\r
+#define PL011_CONSOLE_UART_SPEED 38400\r
+\r
+// SP804 Timer Bases\r
+#define SP804_TIMER0_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11000)\r
+#define SP804_TIMER1_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11020)\r
+#define SP804_TIMER2_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12000)\r
+#define SP804_TIMER3_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12020)\r
+\r
+// Dynamic Memory Controller Base\r
+#define ARM_VE_DMC_BASE 0x100E0000\r
+\r
+// Static Memory Controller Base\r
+#define ARM_VE_SMC_CTRL_BASE 0x100E1000\r
+\r
+// System Configuration Controller register Base addresses\r
+//#define ARM_VE_SYS_CFG_CTRL_BASE 0x100E2000\r
+#define ARM_VE_SYS_CFGRW0_REG 0x100E2000\r
+#define ARM_VE_SYS_CFGRW1_REG 0x100E2004\r
+#define ARM_VE_SYS_CFGRW2_REG 0x100E2008\r
+\r
+#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK 0x2000\r
+#define ARM_VE_CFGRW1_REMAP_NOR0 0\r
+#define ARM_VE_CFGRW1_REMAP_NOR1 (1 << 28)\r
+#define ARM_VE_CFGRW1_REMAP_EXT_AXI (1 << 29)\r
+#define ARM_VE_CFGRW1_REMAP_DRAM (1 << 30)\r
+\r
+// TZPC Base Address\r
+#define ARM_VE_TZPC_BASE 0x100E6000\r
+\r
+// PL301 Fast AXI Base Address\r
+#define ARM_VE_FAXI_BASE 0x100E9000\r
+\r
+// TZASC Defintions\r
+#define ARM_VE_TZASC_BASE 0x100EC000\r
+#define ARM_VE_DECPROT_BIT_TZPC (1 << 6)\r
+#define ARM_VE_DECPROT_BIT_DMC_TZASC (1 << 11)\r
+#define ARM_VE_DECPROT_BIT_NMC_TZASC (1 << 12)\r
+#define ARM_VE_DECPROT_BIT_SMC_TZASC (1 << 13)\r
+#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ (1)\r
+#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK (1 << 3)\r
+#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)\r
+#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)\r
+\r
+// L2x0 Cache Controller Base Address\r
+//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000\r
+\r
+\r
+/*******************************************\r
+// Interrupt Map\r
+*******************************************/\r
+\r
+// Timer Interrupts\r
+#define TIMER01_INTERRUPT_NUM 34\r
+#define TIMER23_INTERRUPT_NUM 35\r
+\r
+\r
+/*******************************************\r
+// EFI Memory Map in Permanent Memory (DRAM)\r
+*******************************************/\r
+\r
+// This region is allocated at the bottom of the DRAM. It will be used\r
+// for fixed address allocations such as Vector Table\r
+#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB\r
+\r
+// This region is the memory declared to PEI as permanent memory for PEI\r
+// and DXE. EFI stacks and heaps will be declared in this region.\r
+#define ARM_VE_EFI_MEMORY_REGION_SZ 0x1000000\r
+\r
+\r
+#endif \r
--- /dev/null
+#/* @file
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CTA9x4ArmVExpressLib
+ FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ ArmTrustZoneLib
+ MemoryAllocationLib
+ PL341DmcLib
+ PL301AxiLib
+
+[Sources.common]
+ CTA9x4.c
+ CTA9x4Mem.c
+
+[Protocols]
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdStandalone
+
+[FixedPcd]
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = CTA9x4ArmVExpressLib\r
+ FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmPlatformLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ ArmLib\r
+ ArmTrustZoneLib\r
+ PL354SmcSecLib\r
+ PL341DmcLib\r
+ PL301AxiLib\r
+\r
+[Sources.common]\r
+ CTA9x4.c\r
+ CTA9x4Helper.asm | RVCT\r
+ CTA9x4Helper.S | GCC\r
+\r
+[Protocols]\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
+[FixedPcd]\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
--- /dev/null
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmTrustZoneLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Drivers/PL341Dmc.h>
+
+// DDR2 timings
+struct pl341_dmc_config ddr_timings = {
+ .base = ARM_VE_DMC_BASE,
+ .has_qos = 1,
+ .refresh_prd = 0x3D0,
+ .cas_latency = 0x8,
+ .write_latency = 0x3,
+ .t_mrd = 0x2,
+ .t_ras = 0xA,
+ .t_rc = 0xE,
+ .t_rcd = 0x104,
+ .t_rfc = 0x2f32,
+ .t_rp = 0x14,
+ .t_rrd = 0x2,
+ .t_wr = 0x4,
+ .t_wtr = 0x2,
+ .t_xp = 0x2,
+ .t_xsr = 0xC8,
+ .t_esr = 0x14,
+ .memory_cfg = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
+ DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
+ .memory_cfg2 = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
+ DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
+ .memory_cfg3 = 0x00000001,
+ .chip_cfg0 = 0x00010000,
+ .t_faw = 0x00000A0D,
+};
+
+/**
+ Return if Trustzone is supported by your platform
+
+ A non-zero value must be returned if you want to support a Secure World on your platform.
+ ArmVExpressTrustzoneInit() will later set up the secure regions.
+ This function can return 0 even if Trustzone is supported by your processor. In this case,
+ the platform will continue to run in Secure World.
+
+ @return A non-zero value if Trustzone supported.
+
+**/
+UINTN ArmPlatformTrustzoneSupported(VOID) {
+ return (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK);
+}
+
+/**
+ Initialize the Secure peripherals and memory regions
+
+ If Trustzone is supported by your platform then this function makes the required initialization
+ of the secure peripherals and memory regions.
+
+**/
+VOID ArmPlatformTrustzoneInit(VOID) {
+ //
+ // Setup TZ Protection Controller
+ //
+
+ // Set Non Secure access for all devices
+ TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0, 0xFFFFFFFF);
+ TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_1, 0xFFFFFFFF);
+ TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2, 0xFFFFFFFF);
+
+ // Remove Non secure access to secure devices
+ TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0,
+ ARM_VE_DECPROT_BIT_TZPC | ARM_VE_DECPROT_BIT_DMC_TZASC | ARM_VE_DECPROT_BIT_NMC_TZASC | ARM_VE_DECPROT_BIT_SMC_TZASC);
+
+ TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2,
+ ARM_VE_DECPROT_BIT_EXT_MAST_TZ | ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK);
+
+
+ //
+ // Setup TZ Address Space Controller for the SMC. Create 5 Non Secure regions (NOR0, NOR1, SRAM, SMC Peripheral regions)
+ //
+
+ // NOR Flash 0 non secure (BootMon)
+ TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED,
+ ARM_VE_SMB_NOR0_BASE,0,
+ TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
+
+ // NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin)
+#if EDK2_ARMVE_SECURE_SYSTEM
+ //Note: Your OS Kernel must be aware of the secure regions before to enable this region
+ TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,
+ ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0,
+ TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);
+#else
+ TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,
+ ARM_VE_SMB_NOR1_BASE,0,
+ TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
+#endif
+
+ // Base of SRAM. Only half of SRAM in Non Secure world
+ // First half non secure (16MB) + Second Half secure (16MB) = 32MB of SRAM
+#if EDK2_ARMVE_SECURE_SYSTEM
+ //Note: Your OS Kernel must be aware of the secure regions before to enable this region
+ TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,
+ ARM_VE_SMB_SRAM_BASE,0,
+ TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW);
+#else
+ TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,
+ ARM_VE_SMB_SRAM_BASE,0,
+ TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);
+#endif
+
+ // Memory Mapped Peripherals. All in non secure world
+ TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED,
+ ARM_VE_SMB_PERIPH_BASE,0,
+ TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
+
+ // MotherBoard Peripherals and On-chip peripherals.
+ TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED,
+ ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0,
+ TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW);
+}
+
+/**
+ Remap the memory at 0x0
+
+ Some platform requires or gives the ability to remap the memory at the address 0x0.
+ This function can do nothing if this feature is not relevant to your platform.
+
+**/
+VOID ArmPlatformBootRemapping(VOID) {
+ UINT32 val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
+ // we remap the DRAM to 0x0
+ MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (val32 & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
+}
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID ArmPlatformInitializeSystemMemory(VOID) {
+ PL341DmcInit(&ddr_timings);
+ PL301AxiInit(ARM_VE_FAXI_BASE);
+}
--- /dev/null
+#------------------------------------------------------------------------------ \r
+#\r
+# ARM VE Entry point. Reset vector in FV header will brach to\r
+# _ModuleEntryPoint. \r
+#\r
+# We use crazy macros, like LoadConstantToReg, since Xcode assembler \r
+# does not support = assembly syntax for ldr.\r
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <AutoGen.h>\r
+\r
+#Start of Code section\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)\r
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)\r
+.extern ASM_PFX(InitializeSMC)\r
+\r
+/**\r
+ Called at the early stage of the Boot phase to know if the memory has already been initialized\r
+\r
+ Running the code from the reset vector does not mean we start from cold boot. In some case, we\r
+ can go through this code with the memory already initialized.\r
+ Because this function is called at the early stage, the implementation must not use the stack.\r
+ Its implementation must probably done in assembly to ensure this requirement.\r
+\r
+ @return Return the condition value into the 'Z' flag\r
+\r
+**/\r
+ASM_PFX(ArmPlatformIsMemoryInitialized):\r
+ // Check if the memory has been already mapped, if so skipped the memory initialization\r
+ LoadConstantToReg (ARM_VE_SYS_CFGRW1_REG ,r0)\r
+ ldr r0, [r0, #0]\r
+ \r
+ // 0x40000000 = Value of Physical Configuration Switch SW[0]\r
+ and r0, r0, #0x40000000\r
+ tst r0, #0x40000000\r
+ bx lr\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ASM_PFX(ArmPlatformInitializeBootMemory):\r
+ mov r5, lr\r
+ // Initialize PL354 SMC\r
+ LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
+ LoadConstantToReg (ARM_VE_SMB_PERIPH_VRAM, r2)\r
+ blx ASM_PFX(InitializeSMC)\r
+ bx r5\r
+\r
+.end\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ EXPORT ArmPlatformIsMemoryInitialized\r
+ EXPORT ArmPlatformInitializeBootMemory\r
+ IMPORT InitializeSMC\r
+ \r
+ PRESERVE8\r
+ AREA CTA9x4Helper, CODE, READONLY\r
+\r
+/**\r
+ Called at the early stage of the Boot phase to know if the memory has already been initialized\r
+\r
+ Running the code from the reset vector does not mean we start from cold boot. In some case, we\r
+ can go through this code with the memory already initialized.\r
+ Because this function is called at the early stage, the implementation must not use the stack.\r
+ Its implementation must probably done in assembly to ensure this requirement.\r
+\r
+ @return Return the condition value into the 'Z' flag\r
+\r
+**/\r
+ArmPlatformIsMemoryInitialized\r
+ // Check if the memory has been already mapped, if so skipped the memory initialization\r
+ LoadConstantToReg (ARM_VE_SYS_CFGRW1_REG ,r0)\r
+ ldr r0, [r0, #0]\r
+ \r
+ // 0x40000000 = Value of Physical Configuration Switch SW[0]\r
+ and r0, r0, #0x40000000\r
+ tst r0, #0x40000000\r
+ bx lr\r
+ \r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ArmPlatformInitializeBootMemory\r
+ mov r5, lr\r
+ // Initialize PL354 SMC\r
+ LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
+ LoadConstantToReg (ARM_VE_SMB_PERIPH_VRAM, r2)\r
+ blx InitializeSMC\r
+ bx r5\r
+ \r
+ END\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+#define DDR_ATTRIBUTES_SECURE_CACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_SECURE_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED\r
+\r
+/**\r
+ Return the information about the memory region in permanent memory used by PEI\r
+\r
+ One of the PEI Module must install the permament memory used by PEI. This function returns the\r
+ information about this region for your platform to this PEIM module.\r
+\r
+ @param[out] PeiMemoryBase Base of the memory region used by PEI core and modules\r
+ @param[out] PeiMemorySize Size of the memory region used by PEI core and modules\r
+\r
+**/\r
+VOID ArmPlatformGetPeiMemory (\r
+ OUT UINTN* PeiMemoryBase,\r
+ OUT UINTN* PeiMemorySize\r
+ ) {\r
+ ASSERT((PeiMemoryBase != NULL) && (PeiMemorySize != NULL));\r
+ \r
+ *PeiMemoryBase = ARM_VE_DRAM_BASE + ARM_VE_EFI_FIX_ADDRESS_REGION_SZ;\r
+ *PeiMemorySize = ARM_VE_EFI_MEMORY_REGION_SZ;\r
+}\r
+\r
+/**\r
+ Return the Virtual Memory Map of your platform\r
+\r
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
+\r
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
+ Virtual Memory mapping. This array must be ended by a zero-filled\r
+ entry\r
+\r
+**/\r
+VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {\r
+ UINT32 val32;\r
+ UINT32 CacheAttributes;\r
+ BOOLEAN bTrustzoneSupport;\r
+ UINTN Index = 0;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+\r
+ ASSERT(VirtualMemoryMap != NULL);\r
+\r
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9);\r
+ if (VirtualMemoryTable == NULL) {\r
+ return;\r
+ }\r
+\r
+ // Check if SMC TZASC is enabled. If Trustzone not enabled then all the entries remain in Secure World.\r
+ // As this value can be changed in the Board Configuration file, the UEFI firmware needs to work for both case\r
+ val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG);\r
+ if (ARM_VE_CFGRW1_TZASC_EN_BIT_MASK & val32) {\r
+ bTrustzoneSupport = TRUE;\r
+ } else {\r
+ bTrustzoneSupport = FALSE;\r
+ }\r
+\r
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);\r
+ } else {\r
+ CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);\r
+ }\r
+\r
+ // ReMap (Either NOR Flash or DRAM)\r
+ VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // DDR\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // SMC CS7\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ // SMB CS0-CS1 - NOR Flash 1 & 2\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ // SMB CS2 - SRAM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // SMB CS3-CS6 - Motherboard Peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
+ if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+ }\r
+\r
+ // End of Table\r
+ VirtualMemoryTable[++Index].PhysicalBase = 0;\r
+ VirtualMemoryTable[Index].VirtualBase = 0;\r
+ VirtualMemoryTable[Index].Length = 0;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
+}\r
+\r
+/**\r
+ Return the EFI Memory Map of your platform\r
+\r
+ This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource\r
+ Descriptor HOBs used by DXE core.\r
+\r
+ @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an\r
+ EFI Memory region. This array must be ended by a zero-filled entry\r
+\r
+**/\r
+VOID ArmPlatformGetEfiMemoryMap (\r
+ OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
+) {\r
+ EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;\r
+ UINT64 MemoryBase;\r
+ UINTN Index = 0;\r
+ ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR *EfiMemoryTable;\r
+\r
+ ASSERT(EfiMemoryMap != NULL);\r
+\r
+ EfiMemoryTable = (ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR) * 6);\r
+\r
+ Attributes =\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED\r
+ );\r
+ MemoryBase = ARM_VE_DRAM_BASE;\r
+ \r
+ // Memory Reserved for fixed address allocations (such as Exception Vector Table)\r
+ EfiMemoryTable[Index].ResourceAttribute = Attributes;\r
+ EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = ARM_VE_EFI_FIX_ADDRESS_REGION_SZ;\r
+ \r
+ MemoryBase += ARM_VE_EFI_FIX_ADDRESS_REGION_SZ;\r
+\r
+ // Memory declared to PEI as permanent memory for PEI and DXE\r
+ EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
+ EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = ARM_VE_EFI_MEMORY_REGION_SZ;\r
+\r
+ MemoryBase += ARM_VE_EFI_MEMORY_REGION_SZ;\r
+\r
+ // We must reserve the memory used by the Firmware Volume copied in DRAM at 0x80000000\r
+ if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
+ // Chunk between the EFI Memory region and the firmware\r
+ EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
+ EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdBaseAddress) - MemoryBase;\r
+\r
+ // Chunk reserved by the firmware in DRAM\r
+ EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_PRESENT);\r
+ EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdEmbeddedFdBaseAddress);\r
+ EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdSize);\r
+\r
+ MemoryBase = PcdGet32(PcdEmbeddedFdBaseAddress) + PcdGet32(PcdEmbeddedFdSize);\r
+ }\r
+ \r
+ // We allocate all the remain memory as untested system memory\r
+ EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_TESTED);\r
+ EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = ARM_VE_DRAM_SZ - (MemoryBase-ARM_VE_DRAM_BASE);\r
+\r
+ EfiMemoryTable[++Index].ResourceAttribute = 0;\r
+ EfiMemoryTable[Index].PhysicalStart = 0;\r
+ EfiMemoryTable[Index].NumberOfBytes = 0;\r
+\r
+ *EfiMemoryMap = EfiMemoryTable;\r
+}\r
--- /dev/null
+/** @file
+ Template library implementation to support ResetSystem Runtime call.
+
+ Fill in the templates with what ever makes you system reset.
+
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/EfiResetSystemLib.h>
+
+#include <ArmPlatform.h>
+
+/**
+ Resets the entire platform.
+
+ @param ResetType The type of reset to perform.
+ @param ResetStatus The status code for the reset.
+ @param DataSize The size, in bytes, of WatchdogData.
+ @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or
+ EfiResetShutdown the data buffer starts with a Null-terminated
+ Unicode string, optionally followed by additional binary data.
+
+**/
+EFI_STATUS
+EFIAPI
+LibResetSystem (
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN CHAR16 *ResetData OPTIONAL
+ )
+{
+ if (ResetData != NULL) {
+ DEBUG ((EFI_D_ERROR, "%s", ResetData));
+ }
+
+ switch (ResetType) {
+ case EfiResetWarm:
+ // Map a warm reset into a cold reset
+ case EfiResetCold:
+ case EfiResetShutdown:
+ default:
+ CpuDeadLoop ();
+ break;
+ }
+
+ // If the reset didn't work, return an error.
+ ASSERT (FALSE);
+ return EFI_DEVICE_ERROR;
+}
+
+/**
+ Initialize any infrastructure required for LibResetSystem () to function.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+LibInitializeResetSystem (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ return EFI_SUCCESS;
+}
--- /dev/null
+#/** @file
+# Reset System lib to make it easy to port new platforms
+#
+# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmVeResetSystemLib
+ FILE_GUID = 36885202-0854-4373-bfd2-95d229b44d44
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = EfiResetSystemLib
+
+[Sources.common]
+ ResetSystemLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ BaseLib
--- /dev/null
+/** @file NorFlashBlockIoDxe.c
+
+ Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "NorFlashDxe.h"
+
+EFI_STATUS
+EFIAPI
+NorFlashBlkIoInitialize (
+ IN NOR_FLASH_INSTANCE* Instance
+ ) {
+ UINT32 Reply;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ DEBUG((DEBUG_BLKIO,"NorFlashBlkIoInitialize()\n"));
+
+ //
+ // Verify that there is a physical hardware device where we expect it to be.
+ //
+
+ // Read a specific CFI query that returns back "QRY"
+ // This ensures that there is really a device present there
+ SEND_NOR_COMMAND( Instance->BaseAddress, 0, P30_CMD_READ_CFI_QUERY );
+
+ // Read CFI 'QRY' data
+ Status = NorFlashReadCfiData( Instance->BaseAddress,
+ P30_CFI_ADDR_QUERY_UNIQUE_QRY,
+ 3,
+ &Reply
+ );
+ if (EFI_ERROR(Status)) {
+ goto EXIT;
+ }
+
+ if ( Reply != CFI_QRY ) {
+ DEBUG((EFI_D_ERROR, "NorFlashBlkIoInitialize: CFI QRY=0x%x (expected 0x595251)\n", Reply));
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+EXIT:
+ // Reset the device
+ Status = NorFlashBlockIoReset( &Instance->BlockIoProtocol, FALSE );
+ if (EFI_ERROR(Status)) {
+ goto EXIT;
+ }
+
+ Instance->Initialized = TRUE;
+ return EFI_SUCCESS;
+}
+
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ )
+{
+ EFI_STATUS Status;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReset(MediaId=0x%x)\n", This->Media->MediaId));
+
+ Status = NorFlashReset(Instance);
+
+ return Status;
+
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+ return NorFlashReadBlocks(Instance,Lba,BufferSizeInBytes,Buffer);
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoWriteBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+ return NorFlashWriteBlocks(Instance,Lba,BufferSizeInBytes,Buffer);
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+ )
+{
+ // No Flush required for the NOR Flash driver
+ // because cache operations are not permitted.
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoFlushBlocks: Function NOT IMPLEMENTED (not required).\n"));
+
+ // Nothing to do so just return without error
+ return EFI_SUCCESS;
+}
--- /dev/null
+/** @file NorFlashDxe.c
+
+ Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "NorFlashDxe.h"
+
+
+//
+// Global variable declarations
+//
+
+#define NOR_FLASH_LAST_DEVICE 4
+
+NOR_FLASH_DESCRIPTION mNorFlashDescription[NOR_FLASH_LAST_DEVICE] = {
+ { // BootMon
+ ARM_VE_SMB_NOR0_BASE,
+ SIZE_256KB * 255,
+ SIZE_256KB,
+ FALSE,
+ {0xE7223039, 0x5836, 0x41E1, 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59}
+ },
+ { // BootMon non-volatile storage
+ ARM_VE_SMB_NOR0_BASE + SIZE_256KB * 255,
+ SIZE_64KB * 4,
+ SIZE_64KB,
+ FALSE,
+ {0x02118005, 0x9DA7, 0x443A, 0x92, 0xD5, 0x78, 0x1F, 0x02, 0x2A, 0xED, 0xBB}
+ },
+ { // UEFI
+ ARM_VE_SMB_NOR1_BASE,
+ SIZE_256KB * 255,
+ SIZE_256KB,
+ FALSE,
+ {0x1F15DA3C, 0x37FF, 0x4070, 0xB4, 0x71, 0xBB, 0x4A, 0xF1, 0x2A, 0x72, 0x4A}
+ },
+ { // UEFI Variable Services non-volatile storage
+ ARM_VE_SMB_NOR1_BASE + SIZE_256KB * 255,
+ SIZE_64KB * 3, //FIXME: Set 3 blocks because I did not succeed to copy 4 blocks into the ARM Versastile Express NOR Falsh in the last NOR Flash. It should be 4 blocks
+ SIZE_64KB,
+ TRUE,
+ {0xCC2CBF29, 0x1498, 0x4CDD, 0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, 0x09, 0x09}
+ }
+};
+
+NOR_FLASH_INSTANCE *mNorFlashInstances[ NOR_FLASH_LAST_DEVICE ];
+
+NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
+ NOR_FLASH_SIGNATURE, // Signature
+ NULL, // Handle ... NEED TO BE FILLED
+
+ FALSE, // Initialized
+ NULL, // Initialize
+
+ 0, // BaseAddress ... NEED TO BE FILLED
+ 0, // Size ... NEED TO BE FILLED
+
+ {\r
+ EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision\r
+ NULL, // Media ... NEED TO BE FILLED\r
+ NorFlashBlockIoReset, // Reset;\r
+ NorFlashBlockIoReadBlocks, // ReadBlocks
+ NorFlashBlockIoWriteBlocks, // WriteBlocks
+ NorFlashBlockIoFlushBlocks // FlushBlocks\r
+ }, // BlockIoProtocol
+
+ {\r
+ 0, // MediaId ... NEED TO BE FILLED\r
+ FALSE, // RemovableMedia\r
+ TRUE, // MediaPresent\r
+ FALSE, // LogicalPartition\r
+ FALSE, // ReadOnly\r
+ FALSE, // WriteCaching;\r
+ 0, // BlockSize ... NEED TO BE FILLED\r
+ 4, // IoAlign\r
+ 0, // LastBlock ... NEED TO BE FILLED\r
+ 0, // LowestAlignedLba\r
+ 1, // LogicalBlocksPerPhysicalBlock\r
+ }, //Media;
+
+ FALSE, // SupportFvb ... NEED TO BE FILLED
+ {\r
+ FvbGetAttributes, // GetAttributes
+ FvbSetAttributes, // SetAttributes
+ FvbGetPhysicalAddress, // GetPhysicalAddress
+ FvbGetBlockSize, // GetBlockSize
+ FvbRead, // Read
+ FvbWrite, // Write
+ FvbEraseBlocks, // EraseBlocks\r
+ NULL, //ParentHandle\r
+ }, // FvbProtoccol;
+
+ {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ (UINT8)( sizeof(VENDOR_DEVICE_PATH) ),
+ (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8),
+ },
+ { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, // GUID ... NEED TO BE FILLED
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ sizeof (EFI_DEVICE_PATH_PROTOCOL),
+ 0
+ }
+ } // DevicePath
+};
+
+EFI_STATUS NorFlashCreateInstance(
+ IN UINTN NorFlashBase,
+ IN UINTN NorFlashSize,
+ IN UINT32 MediaId,
+ IN UINT32 BlockSize,
+ IN BOOLEAN SupportFvb,
+ IN CONST GUID *NorFlashGuid,
+ OUT NOR_FLASH_INSTANCE** NorFlashInstance
+ ) {
+ EFI_STATUS Status;
+ NOR_FLASH_INSTANCE* Instance;
+
+ ASSERT(NorFlashInstance != NULL);
+
+ Instance = AllocateCopyPool (sizeof(NOR_FLASH_INSTANCE),&mNorFlashInstanceTemplate);
+ if (Instance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Instance->BaseAddress = NorFlashBase;
+ Instance->Size = NorFlashSize;
+
+ Instance->BlockIoProtocol.Media = &Instance->Media;
+ Instance->Media.MediaId = MediaId;
+ Instance->Media.BlockSize = BlockSize;
+ Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1;
+\r
+ CopyGuid (&Instance->DevicePath.Vendor.Guid,NorFlashGuid);\r
+
+ if (SupportFvb) {
+ Instance->SupportFvb = TRUE;
+ Instance->Initialize = NorFlashFvbInitialize;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+ //&gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
+ &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol,
+ NULL
+ );
+ if (EFI_ERROR(Status)) {
+ FreePool(Instance);
+ return Status;
+ }
+ } else {
+ Instance->Initialize = NorFlashBlkIoInitialize;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+ &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
+ NULL
+ );
+ if (EFI_ERROR(Status)) {
+ FreePool(Instance);
+ return Status;
+ }
+ }
+\r
+ *NorFlashInstance = Instance;\r
+ return Status;\r
+}
+
+EFI_STATUS
+NorFlashReadCfiData (
+ IN UINTN BaseAddress,
+ IN UINTN CFI_Offset,
+ IN UINT32 NumberOfBytes,
+ OUT UINT32 *Data
+)
+{
+ UINT32 CurrentByte;
+ volatile UINTN *ReadAddress;
+ UINT32 ReadData;
+ UINT32 Byte1;
+ UINT32 Byte2;
+ UINT32 CombinedData = 0;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+
+ if( NumberOfBytes > 4 ) {
+ // Using 32 bit variable so can only read 4 bytes
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // First combine the base address with the offset address
+ // to create an absolute read address.
+ // However, because we are in little endian, read from the last address down to the first
+ ReadAddress = CREATE_NOR_ADDRESS( BaseAddress, CFI_Offset ) + NumberOfBytes - 1;
+
+ // Although each read returns 32 bits, because of the NOR Flash structure,
+ // each 16 bits (16 MSB and 16 LSB) come from two different chips.
+ // When in CFI mode, each chip read returns valid data in only the 8 LSBits;
+ // the 8 MSBits are invalid and can be ignored.
+ // Therefore, each read address returns one byte from each chip.
+ //
+ // Also note: As we are in little endian notation and we are reading
+ // bytes from incremental addresses, we should assemble them in little endian order.
+ for( CurrentByte=0; CurrentByte<NumberOfBytes; CurrentByte++ ) {
+
+ // Read the bytes from the two chips
+ ReadData = *ReadAddress;
+
+ // Check the data validity:
+ // The 'Dual Data' function means that
+ // each chip should return identical data.
+ // If that is not the case then we have a problem.
+ Byte1 = GET_LOW_BYTE ( ReadData );
+ Byte2 = GET_HIGH_BYTE( ReadData );
+
+ if( Byte1 != Byte2 ) {
+ // The two bytes should have been identical
+ return EFI_DEVICE_ERROR;
+ } else {
+
+ // Each successive iteration of the 'for' loop reads a lower address.
+ // As we read lower addresses and as we use little endian,
+ // we read lower significance bytes. So combine them in the correct order.
+ CombinedData = (CombinedData << 8) | Byte1;
+
+ // Decrement down to the next address
+ ReadAddress--;
+ }
+ }
+
+ *Data = CombinedData;
+
+ return Status;
+}
+
+EFI_STATUS
+NorFlashReadStatusRegister(
+ IN UINTN SR_Address
+ )
+{
+ volatile UINT32 *pStatusRegister;
+ UINT32 StatusRegister;
+ UINT32 ErrorMask;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ // Prepare the read address
+ pStatusRegister = (UINT32 *) SR_Address;
+
+ do {
+ // Prepare to read the status register
+ SEND_NOR_COMMAND( SR_Address, 0, P30_CMD_READ_STATUS_REGISTER );
+ // Snapshot the status register
+ StatusRegister = *pStatusRegister;
+ }
+ // The chip is busy while the WRITE bit is not asserted
+ while ( (StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE );
+
+
+ // Perform a full status check:
+ // Mask the relevant bits of Status Register.
+ // Everything should be zero, if not, we have a problem
+
+ // Prepare the Error Mask by setting bits 5, 4, 3, 1
+ ErrorMask = P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM | P30_SR_BIT_VPP | P30_SR_BIT_BLOCK_LOCKED ;
+
+ if ( (StatusRegister & ErrorMask) != 0 ) {
+ if ( (StatusRegister & P30_SR_BIT_VPP) != 0 ) {
+ DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: VPP Range Error\n"));
+ } else if ( (StatusRegister & (P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM) ) != 0 ) {
+ DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: Command Sequence Error\n"));
+ } else if ( (StatusRegister & P30_SR_BIT_PROGRAM) != 0 ) {
+ DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: Program Error\n"));
+ } else if ( (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) != 0 ) {
+ DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: Device Protect Error\n"));
+ } else {\r
+ DEBUG((EFI_D_ERROR,"NorFlashReadStatusRegister: Error (0x%X)\n",Status));\r
+ }
+
+ // If an error is detected we must clear the Status Register
+ SEND_NOR_COMMAND( SR_Address, 0, P30_CMD_CLEAR_STATUS_REGISTER );
+ Status = EFI_DEVICE_ERROR;
+ }
+
+ SEND_NOR_COMMAND( SR_Address, 0, P30_CMD_READ_ARRAY );
+
+ return Status;
+}
+
+
+BOOLEAN
+NorFlashBlockIsLocked(
+ IN UINTN BlockAddress
+ )
+{
+ volatile UINT32 *pReadData;
+ UINT32 LockStatus;
+ BOOLEAN BlockIsLocked = TRUE;
+
+ // Prepare the read address
+ pReadData = (UINT32 *) CREATE_NOR_ADDRESS( BlockAddress, 2 );
+
+ // Send command for reading device id
+ SEND_NOR_COMMAND( BlockAddress, 2, P30_CMD_READ_DEVICE_ID );
+
+ // Read block lock status
+ LockStatus = *pReadData;
+
+ // Decode block lock status
+ LockStatus = FOLD_32BIT_INTO_16BIT(LockStatus);
+
+ if( (LockStatus & 0x2) != 0 ) {
+ DEBUG((EFI_D_ERROR, "UnlockSingleBlock: WARNING: Block LOCKED DOWN\n"));
+ }
+
+ if( (LockStatus & 0x1) == 0 ) {
+ // This means the block is unlocked
+ DEBUG((DEBUG_BLKIO, "UnlockSingleBlock: Block 0x%08x unlocked\n", BlockAddress ));
+ BlockIsLocked = FALSE;
+ }
+
+ return BlockIsLocked;
+}
+
+
+EFI_STATUS
+NorFlashUnlockSingleBlock(
+ IN UINTN BlockAddress
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ // Raise the Task Priority Level to TPL_NOTIFY to serialise all its operations
+ // and to protect shared data structures.
+
+ //while( NorFlashBlockIsLocked( BlockAddress ) )
+ {
+ // Request a lock setup
+ SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_LOCK_BLOCK_SETUP );
+
+ // Request an unlock
+ SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_UNLOCK_BLOCK );
+ }
+
+ // Put device back into Read Array mode
+ SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_READ_ARRAY );
+
+ DEBUG((DEBUG_BLKIO, "UnlockSingleBlock: BlockAddress=0x%08x, Exit Status = \"%r\".\n", BlockAddress, Status));
+
+ return Status;
+}
+
+
+EFI_STATUS
+NorFlashUnlockSingleBlockIfNecessary(
+ IN UINTN BlockAddress
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ if ( NorFlashBlockIsLocked( BlockAddress ) == TRUE ) {
+ Status = NorFlashUnlockSingleBlock( BlockAddress );
+ }
+
+ return Status;
+}
+
+
+/**
+ * The following function presumes that the block has already been unlocked.
+ **/
+EFI_STATUS
+NorFlashEraseSingleBlock(
+ IN UINTN BlockAddress
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ // Request a block erase and then confirm it
+ SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_BLOCK_ERASE_SETUP );
+ SEND_NOR_COMMAND( BlockAddress, 0, P30_CMD_BLOCK_ERASE_CONFIRM );
+ // Wait until the status register gives us the all clear
+ Status = NorFlashReadStatusRegister( BlockAddress );
+
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_BLKIO, "EraseSingleBlock(BlockAddress=0x%08x) = '%r'\n", BlockAddress, Status));
+ }
+ return Status;
+}
+
+/**
+ * The following function presumes that the block has already been unlocked.
+ **/
+EFI_STATUS
+NorFlashUnlockAndEraseSingleBlock(
+ IN UINTN BlockAddress
+ )
+{
+ EFI_STATUS Status;
+
+ // Unlock the block if we have to
+ Status = NorFlashUnlockSingleBlockIfNecessary( BlockAddress );
+ if (!EFI_ERROR(Status)) {
+ Status = NorFlashEraseSingleBlock( BlockAddress );
+ }
+
+ return Status;
+}
+
+
+EFI_STATUS
+NorFlashWriteSingleWord (
+ IN UINTN WordAddress,
+ IN UINT32 WriteData
+ )
+{
+ EFI_STATUS Status;
+ volatile UINT32 *Data;
+
+ // Prepare the read address
+ Data = (UINT32 *)WordAddress;
+
+ // Request a write single word command
+ SEND_NOR_COMMAND( WordAddress, 0, P30_CMD_WORD_PROGRAM_SETUP );
+
+ // Store the word into NOR Flash;
+ *Data = WriteData;
+
+ // Wait for the write to complete and then check for any errors; i.e. check the Status Register
+ Status = NorFlashReadStatusRegister( WordAddress );
+
+ return Status;
+}
+
+/*
+ * Writes data to the NOR Flash using the Buffered Programming method.
+ *
+ * The maximum size of the on-chip buffer is 32-words, because of hardware restrictions.
+ * Therefore this function will only handle buffers up to 32 words or 128 bytes.
+ * To deal with larger buffers, call this function again.
+ *
+ * This function presumes that both the TargetAddress and the TargetAddress+BufferSize
+ * exist entirely within the NOR Flash. Therefore these conditions will not be checked here.
+ *
+ * In buffered programming, if the target address not at the beginning of a 32-bit word boundary,
+ * then programming time is doubled and power consumption is increased.
+ * Therefore, it is a requirement to align buffer writes to 32-bit word boundaries.
+ * i.e. the last 4 bits of the target start address must be zero: 0x......00
+ */
+EFI_STATUS
+NorFlashWriteBuffer (
+ IN UINTN TargetAddress,
+ IN UINTN BufferSizeInBytes,
+ IN UINT32 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSizeInWords;
+ UINTN Count;
+ volatile UINT32 *Data;
+ UINTN WaitForBuffer = MAX_BUFFERED_PROG_ITERATIONS;
+ BOOLEAN BufferAvailable = FALSE;
+
+
+ // Check that the target address does not cross a 32-word boundary.
+ if ( (TargetAddress & BOUNDARY_OF_32_WORDS) != 0 ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Check there are some data to program
+ if ( BufferSizeInBytes == 0 ) {
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ // Check that the buffer size does not exceed the maximum hardware buffer size on chip.
+ if ( BufferSizeInBytes > P30_MAX_BUFFER_SIZE_IN_BYTES ) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // Check that the buffer size is a multiple of 32-bit words
+ if ( (BufferSizeInBytes % 4) != 0 ) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // Pre-programming conditions checked, now start the algorithm.
+
+ // Prepare the data destination address
+ Data = (UINT32 *)TargetAddress;
+
+ // Check the availability of the buffer
+ do {
+ // Issue the Buffered Program Setup command
+ SEND_NOR_COMMAND( TargetAddress, 0, P30_CMD_BUFFERED_PROGRAM_SETUP );
+
+ // Read back the status register bit#7 from the same address
+ if ( ((*Data) & P30_SR_BIT_WRITE) == P30_SR_BIT_WRITE ) {
+ BufferAvailable = TRUE;
+ }
+
+ // Update the loop counter
+ WaitForBuffer--;
+
+ } while (( WaitForBuffer > 0 ) && ( BufferAvailable == FALSE ));
+
+ // The buffer was not available for writing
+ if ( WaitForBuffer == 0 ) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ // From now on we work in 32-bit words
+ BufferSizeInWords = BufferSizeInBytes / (UINTN)4;
+
+ // Write the word count, which is (buffer_size_in_words - 1),
+ // because word count 0 means one word.
+ SEND_NOR_COMMAND( TargetAddress, 0, (BufferSizeInWords - 1) );
+
+ // Write the data to the NOR Flash, advancing each address by 4 bytes
+ for( Count=0; Count<BufferSizeInWords; Count++, Data++, Buffer++ ) {
+ *Data = *Buffer;
+ }
+
+ // Issue the Buffered Program Confirm command, to start the programming operation
+ SEND_NOR_COMMAND( TargetAddress, 0, P30_CMD_BUFFERED_PROGRAM_CONFIRM );
+
+ // Wait for the write to complete and then check for any errors; i.e. check the Status Register
+ Status = NorFlashReadStatusRegister( TargetAddress );
+
+ return Status;
+}
+
+EFI_STATUS
+NorFlashWriteSingleBlock (
+ IN UINTN DeviceBaseAddress,
+ IN EFI_LBA Lba,
+ IN UINT32 *DataBuffer,
+ IN UINT32 BlockSizeInWords
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINTN WordAddress;
+ UINT32 WordIndex;
+ UINTN BufferIndex;
+ UINTN BlockAddress;
+ UINTN BuffersInBlock;
+ UINTN RemainingWords;
+
+ // Get the physical address of the block
+ BlockAddress = GET_NOR_BLOCK_ADDRESS(DeviceBaseAddress, Lba, BlockSizeInWords * 4);
+
+ Status = NorFlashUnlockAndEraseSingleBlock( BlockAddress );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n", BlockAddress));
+ return Status;
+ }
+
+ // To speed up the programming operation, NOR Flash is programmed using the Buffered Programming method.
+
+ // Start writing from the first address at the start of the block
+ WordAddress = BlockAddress;
+
+ // Check that the address starts at a 32-word boundary, i.e. last 7 bits must be zero
+ if ( (WordAddress & BOUNDARY_OF_32_WORDS) == 0x00 ) {
+
+ // First, break the entire block into buffer-sized chunks.
+ BuffersInBlock = (UINTN)BlockSizeInWords / P30_MAX_BUFFER_SIZE_IN_BYTES;
+
+ // Then feed each buffer chunk to the NOR Flash
+ for( BufferIndex=0;
+ BufferIndex < BuffersInBlock;
+ BufferIndex++, WordAddress += P30_MAX_BUFFER_SIZE_IN_BYTES, DataBuffer += P30_MAX_BUFFER_SIZE_IN_WORDS
+ ) {
+ Status = NorFlashWriteBuffer ( WordAddress, P30_MAX_BUFFER_SIZE_IN_BYTES, DataBuffer );
+ if (EFI_ERROR(Status)) {
+ goto EXIT;
+ }
+ }
+
+ // Finally, finish off any remaining words that are less than the maximum size of the buffer
+ RemainingWords = BlockSizeInWords % P30_MAX_BUFFER_SIZE_IN_WORDS;
+
+ if( RemainingWords != 0) {
+ Status = NorFlashWriteBuffer ( WordAddress, (RemainingWords * 4), DataBuffer );
+ if (EFI_ERROR(Status)) {
+ goto EXIT;
+ }
+ }
+
+ } else {
+ // For now, use the single word programming algorithm
+ // It is unlikely that the NOR Flash will exist in an address which falls within a 32 word boundary range,
+ // i.e. which ends in the range 0x......01 - 0x......7F.
+ for( WordIndex=0; WordIndex<BlockSizeInWords; WordIndex++, DataBuffer++, WordAddress = WordAddress + 4 ) {
+ Status = NorFlashWriteSingleWord( WordAddress, *DataBuffer );
+ if (EFI_ERROR(Status)) {
+ goto EXIT;
+ }
+ }
+ }
+
+ EXIT:
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = \"%r\".\n", WordAddress, Status));
+ }
+ return Status;
+}
+
+
+EFI_STATUS
+NorFlashWriteBlocks (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+ )
+{
+ UINT32 *pWriteBuffer;
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_LBA CurrentBlock;
+ UINT32 BlockSizeInWords;
+ UINT32 NumBlocks;
+ UINT32 BlockCount;
+ volatile UINT32 *VersatileExpress_SYS_FLASH;
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if( Instance->Media.ReadOnly == TRUE ) {
+ return EFI_WRITE_PROTECTED;
+ }
+
+ // We must have some bytes to read
+ DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: BufferSizeInBytes=0x%x\n", BufferSizeInBytes));
+ if( BufferSizeInBytes == 0 ) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // The size of the buffer must be a multiple of the block size
+ DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: BlockSize in bytes =0x%x\n", Instance->Media.BlockSize ));
+ if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // All blocks must be within the device
+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
+
+ DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: NumBlocks=%d, LastBlock=%ld, Lba=%ld.\n", NumBlocks, Instance->Media.LastBlock, Lba));
+
+ if ( ( Lba + NumBlocks ) > ( Instance->Media.LastBlock + 1 ) ) {
+ DEBUG((EFI_D_ERROR, "NorFlashWriteBlocks: ERROR - Write will exceed last block.\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Everything seems ok so far, so now we need to disable the platform-specific
+ // flash write protection for Versatile Express
+ VersatileExpress_SYS_FLASH = (UINT32 *)VE_REGISTER_SYS_FLASH_ADDR;
+ if( (*VersatileExpress_SYS_FLASH & 0x1) == 0 ) {
+ // Writing to NOR FLASH is disabled, so enable it
+ *VersatileExpress_SYS_FLASH = 0x1;
+ DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: informational - Had to enable HSYS_FLASH flag.\n" ));
+ }
+
+ BlockSizeInWords = Instance->Media.BlockSize / 4;
+
+ // Because the target *Buffer is a pointer to VOID, we must put all the data into a pointer
+ // to a proper data type, so use *ReadBuffer
+ pWriteBuffer = (UINT32 *)Buffer;
+
+ CurrentBlock = Lba;
+ for( BlockCount=0; BlockCount<NumBlocks; BlockCount++, CurrentBlock++, pWriteBuffer = pWriteBuffer + BlockSizeInWords ) {
+
+ DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: Writing block #%d\n", (UINTN)CurrentBlock ));
+
+ Status = NorFlashWriteSingleBlock( Instance->BaseAddress, CurrentBlock, pWriteBuffer, BlockSizeInWords );
+
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+
+ }
+
+ DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: Exit Status = \"%r\".\n", Status));
+ return Status;
+}
+
+
+EFI_STATUS
+NorFlashReadBlocks (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ )
+{
+ UINT32 NumBlocks;
+ UINTN StartAddress;
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // We must have some bytes to read
+ DEBUG((DEBUG_BLKIO, "NorFlashReadBlocks: BufferSize=0x%x bytes.\n", BufferSizeInBytes));
+ if( BufferSizeInBytes == 0 ) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // The size of the buffer must be a multiple of the block size
+ DEBUG((DEBUG_BLKIO, "NorFlashReadBlocks: BlockSize=0x%x bytes.\n", Instance->Media.BlockSize ));
+ if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // All blocks must be within the device
+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
+
+ DEBUG((DEBUG_BLKIO, "NorFlashReadBlocks: NumBlocks=%d, LastBlock=%ld, Lba=%ld\n", NumBlocks, Instance->Media.LastBlock, Lba));
+
+ if ( ( Lba + NumBlocks ) > (Instance->Media.LastBlock + 1) ) {
+ DEBUG((EFI_D_ERROR, "NorFlashReadBlocks: ERROR - Read will exceed last block\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Get the address to start reading from
+ StartAddress = GET_NOR_BLOCK_ADDRESS( Instance->BaseAddress,
+ Lba,
+ Instance->Media.BlockSize
+ );
+
+ // Put the device into Read Array mode
+ SEND_NOR_COMMAND( Instance->BaseAddress, 0, P30_CMD_READ_ARRAY );
+
+ // Readout the data
+ CopyMem(Buffer, (UINTN *)StartAddress, BufferSizeInBytes);
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+NorFlashReset (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ DEBUG((DEBUG_BLKIO, "NorFlashReset(BaseAddress=0x%08x)\n", Instance->BaseAddress));
+
+ // As there is no specific RESET to perform, ensure that the devices is in the default Read Array mode
+ SEND_NOR_COMMAND( Instance->BaseAddress, 0, P30_CMD_READ_ARRAY );
+
+ return EFI_SUCCESS;
+}
+
+
+
+EFI_STATUS
+EFIAPI
+NorFlashInitialise (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 Index;
+
+ for (Index = 0; Index < NOR_FLASH_LAST_DEVICE; Index++) {
+ Status = NorFlashCreateInstance(
+ mNorFlashDescription[Index].BaseAddress,
+ mNorFlashDescription[Index].Size,
+ Index,
+ mNorFlashDescription[Index].BlockSize,
+ mNorFlashDescription[Index].SupportFvb,
+ &mNorFlashDescription[Index].Guid,
+ &mNorFlashInstances[Index]
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR,"NorFlashInitialise: Fail to create instance for NorFlash[%d]\n",Index));
+ }
+ }
+
+ return Status;
+}
--- /dev/null
+/** @file NorFlashDxe.h
+
+ Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NOR_FLASH_DXE_H__
+#define __NOR_FLASH_DXE_H__
+
+
+#include <Base.h>
+#include <PiDxe.h>
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+#include <ArmPlatform.h>
+
+#define HIGH_16_BITS 0xFFFF0000
+#define LOW_16_BITS 0x0000FFFF
+#define LOW_8_BITS 0x000000FF
+
+// Hardware addresses
+
+#define VE_SYSTEM_REGISTERS_OFFSET 0x00000000
+#define SYSTEM_REGISTER_SYS_FLASH 0x0000004C
+
+#define VE_REGISTER_SYS_FLASH_ADDR ( ARM_VE_BOARD_PERIPH_BASE + VE_SYSTEM_REGISTERS_OFFSET + SYSTEM_REGISTER_SYS_FLASH )
+
+// Device access macros
+// These are necessary because we use 2 x 16bit parts to make up 32bit data
+
+#define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value & LOW_16_BITS ) )
+
+#define GET_LOW_BYTE(value) ( value & LOW_8_BITS )
+#define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) )
+
+// Each command must be sent simultaneously to both chips,
+// i.e. at the lower 16 bits AND at the higher 16 bits
+#define CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) ( (volatile UINTN *)((BaseAddr) + ((OffsetAddr) << 2)) )
+#define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( Cmd & LOW_16_BITS) )
+#define SEND_NOR_COMMAND(BaseAddr,OffsetAddr,Cmd) ( *CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) = CREATE_DUAL_CMD(Cmd) )
+#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)(Lba * LbaSize) )
+
+// Status Register Bits
+#define P30_SR_BIT_WRITE 0x00800080 /* Bit 7 */
+#define P30_SR_BIT_ERASE_SUSPEND 0x00400040 /* Bit 6 */
+#define P30_SR_BIT_ERASE 0x00200020 /* Bit 5 */
+#define P30_SR_BIT_PROGRAM 0x00100010 /* Bit 4 */
+#define P30_SR_BIT_VPP 0x00080008 /* Bit 3 */
+#define P30_SR_BIT_PROGRAM_SUSPEND 0x00040004 /* Bit 2 */
+#define P30_SR_BIT_BLOCK_LOCKED 0x00020002 /* Bit 1 */
+#define P30_SR_BIT_BEFP 0x00010001 /* Bit 0 */
+
+// Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family
+
+// On chip buffer size for buffered programming operations
+// There are 2 chips, each chip can buffer up to 32 (16-bit)words, and each word is 2 bytes.
+// Therefore the total size of the buffer is 2 x 32 x 2 = 128 bytes
+#define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128)
+#define P30_MAX_BUFFER_SIZE_IN_WORDS (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINTN)4))
+#define MAX_BUFFERED_PROG_ITERATIONS 10000000
+#define BOUNDARY_OF_32_WORDS 0x7F
+
+// CFI Addresses
+#define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10
+#define P30_CFI_ADDR_VENDOR_ID 0x13
+
+// CFI Data
+#define CFI_QRY 0x00595251
+
+// READ Commands
+#define P30_CMD_READ_DEVICE_ID 0x0090
+#define P30_CMD_READ_STATUS_REGISTER 0x0070
+#define P30_CMD_CLEAR_STATUS_REGISTER 0x0050
+#define P30_CMD_READ_ARRAY 0x00FF
+#define P30_CMD_READ_CFI_QUERY 0x0098
+
+// WRITE Commands
+#define P30_CMD_WORD_PROGRAM_SETUP 0x0040
+#define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010
+#define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8
+#define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0
+#define P30_CMD_BEFP_SETUP 0x0080
+#define P30_CMD_BEFP_CONFIRM 0x00D0
+
+// ERASE Commands
+#define P30_CMD_BLOCK_ERASE_SETUP 0x0020
+#define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0
+
+// SUSPEND Commands
+#define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0
+#define P30_CMD_SUSPEND_RESUME 0x00D0
+
+// BLOCK LOCKING / UNLOCKING Commands
+#define P30_CMD_LOCK_BLOCK_SETUP 0x0060
+#define P30_CMD_LOCK_BLOCK 0x0001
+#define P30_CMD_UNLOCK_BLOCK 0x00D0
+#define P30_CMD_LOCK_DOWN_BLOCK 0x002F
+
+// PROTECTION Commands
+#define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0
+
+// CONFIGURATION Commands
+#define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060
+#define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003
+
+#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')
+#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
+#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
+
+typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
+
+typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
+
+typedef struct {
+ UINTN BaseAddress;
+ UINTN Size;
+ UINTN BlockSize;
+ BOOLEAN SupportFvb;
+ EFI_GUID Guid;
+} NOR_FLASH_DESCRIPTION;
+
+typedef struct {
+ VENDOR_DEVICE_PATH Vendor;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} NOR_FLASH_DEVICE_PATH;
+
+struct _NOR_FLASH_INSTANCE {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+
+ BOOLEAN Initialized;
+ NOR_FLASH_INITIALIZE Initialize;
+
+ UINTN BaseAddress;
+ UINTN Size;
+
+ EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
+ EFI_BLOCK_IO_MEDIA Media;
+
+ BOOLEAN SupportFvb;
+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
+
+ NOR_FLASH_DEVICE_PATH DevicePath;
+};
+
+EFI_STATUS
+EFIAPI
+NorFlashBlkIoInitialize (
+ IN NOR_FLASH_INSTANCE* Instance
+ );
+
+EFI_STATUS
+NorFlashReadCfiData (
+ IN UINTN BaseAddress,
+ IN UINTN CFI_Offset,
+ IN UINT32 NumberOfBytes,
+ OUT UINT32 *Data
+);
+
+EFI_STATUS
+NorFlashWriteBuffer (
+ IN UINTN TargetAddress,
+ IN UINTN BufferSizeInBytes,
+ IN UINT32 *Buffer
+);
+
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ );
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+);
+
+
+//
+// NorFlashFvbDxe.c
+//
+
+EFI_STATUS
+EFIAPI
+NorFlashFvbInitialize (
+ IN NOR_FLASH_INSTANCE* Instance
+);
+
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+);
+
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+);
+
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+);
+
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+);
+
+EFI_STATUS
+EFIAPI
+FvbRead(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+);
+
+EFI_STATUS
+EFIAPI
+FvbWrite(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+);
+
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+);
+
+//
+// NorFlashDxe.c
+//
+
+EFI_STATUS
+NorFlashUnlockAndEraseSingleBlock(
+ IN UINTN BlockAddress
+);
+
+EFI_STATUS
+NorFlashWriteSingleBlock (
+ IN UINTN DeviceBaseAddress,
+ IN EFI_LBA Lba,
+ IN UINT32 *pDataBuffer,
+ IN UINT32 BlockSizeInWords
+);
+
+EFI_STATUS
+NorFlashWriteBlocks (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+);
+
+EFI_STATUS
+NorFlashReadBlocks (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+);
+
+EFI_STATUS
+NorFlashReset (
+ IN NOR_FLASH_INSTANCE *Instance
+);
+
+#endif /* __NOR_FLASH_DXE_H__ */
--- /dev/null
+#/** @file
+#
+# Component discription file for NorFlashDxe module
+#
+# Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmVeNorFlashDxe
+ FILE_GUID = 93E34C7E-B50E-11DF-9223-2443DFD72085
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = NorFlashInitialise
+
+[Sources.common]
+ NorFlashDxe.c
+ NorFlashFvbDxe.c
+ NorFlashBlockIoDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
+
+[LibraryClasses]
+ IoLib
+ BaseLib
+ UefiLib
+ DebugLib
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+
+[Guids]
+ gEfiSystemNvDataFvGuid
+ gEfiVariableGuid
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEfiFirmwareVolumeBlockProtocolGuid
+
+[FixedPcd.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+
+[Pcd.common]
+
+
+[Depex]
+TRUE
--- /dev/null
+/*++ @file NorFlashFvbDxe.c
+
+ Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ --*/
+
+#include <PiDxe.h>
+
+#include <Library/PcdLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Guid/VariableFormat.h>
+#include <Guid/SystemNvDataGuid.h>
+
+#include "NorFlashDxe.h"
+
+
+///
+/// The Firmware Volume Block Protocol is the low-level interface
+/// to a firmware volume. File-level access to a firmware volume
+/// should not be done using the Firmware Volume Block Protocol.
+/// Normal access to a firmware volume must use the Firmware
+/// Volume Protocol. Typically, only the file system driver that
+/// produces the Firmware Volume Protocol will bind to the
+/// Firmware Volume Block Protocol.
+///
+
+/**
+ Initialises the FV Header and Variable Store Header
+ to support variable operations.
+
+ @param[in] Ptr - Location to initialise the headers
+
+**/
+EFI_STATUS
+InitializeFvAndVariableStoreHeaders (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+ VOID* Headers;
+ UINTN HeadersLength;
+ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+
+ if (!Instance->Initialized) {
+ Instance->Initialize(Instance);
+ }
+
+ HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY) + sizeof(VARIABLE_STORE_HEADER);
+ Headers = AllocatePool(HeadersLength);
+ ZeroMem (&Headers,HeadersLength);
+
+ //
+ // EFI_FIRMWARE_VOLUME_HEADER
+ //
+ FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
+ FirmwareVolumeHeader->FvLength = Instance->Media.BlockSize * (Instance->Media.LastBlock + 1);
+ FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
+ FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) (
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY | // After erasure all bits take this value (i.e. '1')
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled
+ );
+ FirmwareVolumeHeader->HeaderLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY);
+ FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
+ FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1;
+ FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize;
+ FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
+ FirmwareVolumeHeader->BlockMap[1].Length = 0;
+ FirmwareVolumeHeader->Checksum = CalculateCheckSum16 (FirmwareVolumeHeader,FirmwareVolumeHeader->HeaderLength);
+
+ //
+ // VARIABLE_STORE_HEADER
+ //
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINT32)Headers + FirmwareVolumeHeader->HeaderLength);
+ CopyGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid);
+ VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength;
+ VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
+ VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
+
+ // Install the combined super-header in the NorFlash
+ Status = FvbWrite(&Instance->FvbProtocol, 0, 0, &FirmwareVolumeHeader, Headers );
+
+ FreePool(Headers);
+ return Status;
+}
+
+/**
+ Check the integrity of firmware volume header.
+
+ @param[in] FwVolHeader - A pointer to a firmware volume header
+
+ @retval EFI_SUCCESS - The firmware volume is consistent
+ @retval EFI_NOT_FOUND - The firmware volume has been corrupted.
+
+**/
+EFI_STATUS
+ValidateFvHeader (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ UINT16 Checksum;
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+ UINTN VariableStoreLength;
+
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->BaseAddress;
+
+ //
+ // Verify the header revision, header signature, length
+ // Length of FvBlock cannot be 2**64-1
+ // HeaderLength cannot be an odd number
+ //
+ if ( ( FwVolHeader->Revision != EFI_FVH_REVISION )
+ || ( FwVolHeader->Signature != EFI_FVH_SIGNATURE )
+ || ( FwVolHeader->FvLength != Instance->Media.BlockSize * (Instance->Media.LastBlock + 1) )
+ ) {
+ return EFI_NOT_FOUND;
+ }
+
+ // Check the Firmware Volume Guid
+ if( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE ) {
+ DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Firmware Volume Guid non-compatible\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ // Verify the header checksum
+ /*Checksum = CalculateSum16((VOID*) FwVolHeader, FwVolHeader->HeaderLength);
+ if (Checksum != 0) {
+ DEBUG ((EFI_D_ERROR, "ValidateFvHeader: FV checksum is invalid (Checksum:0x%X)\n",Checksum));
+ return EFI_NOT_FOUND;
+ }*/
+
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINT32)FwVolHeader + FwVolHeader->HeaderLength);
+
+ // Check the Variable Store Guid
+ if( CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) == FALSE ) {
+ DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Variable Store Guid non-compatible\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength;
+ if (VariableStoreHeader->Size != VariableStoreLength) {
+ DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Variable Store Length does not match\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
+ current settings are returned.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2) (
+
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY // After erasure all bits take this value (i.e. '1')
+
+ );
+
+ // Check if it is write protected
+ if (Instance->Media.ReadOnly != TRUE) {
+
+ FlashFvbAttributes = FlashFvbAttributes |
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be enabled
+ }
+
+ *Attributes = FlashFvbAttributes;
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The SetAttributes() function sets configurable firmware volume attributes
+ and returns the new settings of the firmware volume.
+
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes On input, Attributes is a pointer to EFI_FVB_ATTRIBUTES_2
+ that contains the desired firmware volume settings.
+ On successful return, it contains the new settings of
+ the firmware volume.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with the capabilities
+ as declared in the firmware volume header.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",*Attributes));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ The GetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address Pointer to a caller-allocated
+ EFI_PHYSICAL_ADDRESS that, on successful
+ return from GetPhysicalAddress(), contains the
+ base address of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetPhysicalAddress(BaseAddress=0x%08x)\n", Instance->BaseAddress));
+
+ ASSERT(Address != NULL);
+
+ *Address = Instance->BaseAddress;
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The GetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba Indicates the block for which to return the size.
+
+ @param BlockSize Pointer to a caller-allocated UINTN in which
+ the size of the block is returned.
+
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+ which the number of consecutive blocks,
+ starting with Lba, is returned. All
+ blocks in this range have a size of
+ BlockSize.
+
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ )
+{
+ EFI_STATUS Status;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n", Lba, Instance->Media.BlockSize, Instance->Media.LastBlock));
+
+ if (Lba > Instance->Media.LastBlock) {
+ DEBUG ((EFI_D_ERROR, "FvbGetBlockSize: ERROR - Parameter LBA %ld is beyond the last Lba (%ld).\n", Lba, Instance->Media.LastBlock));
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ // This is easy because in this platform each NorFlash device has equal sized blocks.
+ *BlockSize = (UINTN) Instance->Media.BlockSize;
+ *NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1);
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize: *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n", *BlockSize, *NumberOfBlocks));
+
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The Read() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the Read() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The Read() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index from which to read.
+
+ @param Offset Offset into the block at which to begin reading.
+
+ @param NumBytes Pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the buffer.
+ At exit, *NumBytes contains the total number of bytes read.
+
+ @param Buffer Pointer to a caller-allocated buffer that will be used
+ to hold the data that is read.
+
+ @retval EFI_SUCCESS The firmware volume was read successfully, and contents are
+ in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
+ On output, NumBytes contains the total number of bytes
+ returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be read.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbRead(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ EFI_STATUS TempStatus;
+ UINTN BlockSize;
+ UINT8 *BlockBuffer;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", Lba, Offset, *NumBytes, Buffer));
+
+ if (!Instance->Initialized) {
+ Instance->Initialize(Instance);
+ }
+
+ Status = EFI_SUCCESS;
+ TempStatus = Status;
+
+ if (FALSE) {
+ DEBUG ((EFI_D_ERROR, "FvbRead: Can not read: Device is in ReadDisabled state.\n"));
+ // It is in ReadDisabled state, return an error right away
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+
+ // The read must not span block boundaries.
+ // We need to check each variable individually because adding two large values together overflows.
+ if ( ( Offset >= BlockSize ) ||
+ ( *NumBytes > BlockSize ) ||
+ ( (Offset + *NumBytes) > BlockSize ) ) {
+ DEBUG ((EFI_D_ERROR, "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // We must have some bytes to read
+ if (*NumBytes == 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // FixMe: Allow an arbitrary number of bytes to be read out, not just a multiple of block size.
+
+ // Allocate runtime memory to read in the NOR Flash data. Variable Services are runtime.
+ BlockBuffer = AllocateRuntimePool(BlockSize);
+
+ // Check if the memory allocation was successful
+ if( BlockBuffer == NULL ) {
+ DEBUG ((EFI_D_ERROR, "FvbRead: ERROR - Could not allocate BlockBuffer @ 0x%08x.\n", BlockBuffer));
+ return EFI_DEVICE_ERROR;
+ }
+
+ // Read NOR Flash data into shadow buffer
+ TempStatus = NorFlashReadBlocks(Instance, Lba, BlockSize, BlockBuffer);
+ if (EFI_ERROR (TempStatus)) {
+ // Return one of the pre-approved error statuses
+ Status = EFI_DEVICE_ERROR;
+ goto FREE_MEMORY;
+ }
+
+ // Put the data at the appropriate location inside the buffer area
+ DEBUG ((DEBUG_BLKIO, "FvbRead: CopyMem( Dst=0x%08x, Src=0x%08x, Size=0x%x ).\n", Buffer, BlockBuffer + Offset, *NumBytes));
+
+ CopyMem(Buffer, BlockBuffer + Offset, *NumBytes);
+
+FREE_MEMORY:
+ FreePool(BlockBuffer);
+
+ DEBUG ((DEBUG_BLKIO, "FvbRead - end\n"));
+ return Status;
+}
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The Write() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the Write()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again. Before calling the
+ Write() function, it is recommended for the caller to first call
+ the EraseBlocks() function to erase the specified block to
+ write. A block erase cycle will transition bits from the
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the Write() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The Write() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the Write() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index to write to.
+
+ @param Offset Offset into the block at which to begin writing.
+
+ @param NumBytes The pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the buffer.
+ At exit, *NumBytes contains the total number of bytes actually written.
+
+ @param Buffer The pointer to a caller-allocated buffer that contains the source for the write.
+
+ @retval EFI_SUCCESS The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary.
+ On output, NumBytes contains the total number of bytes
+ actually written.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be written.
+
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbWrite(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ EFI_STATUS TempStatus;
+ UINTN BlockSize;
+ UINT8 *BlockBuffer;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ if (!Instance->Initialized) {
+ Instance->Initialize(Instance);
+ }
+
+ DEBUG ((DEBUG_BLKIO, "FvbWrite(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", Lba, Offset, *NumBytes, Buffer));
+
+ Status = EFI_SUCCESS;
+ TempStatus = Status;
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE) {
+ DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - Can not write: Device is in WriteDisabled state.\n"));
+ // It is in WriteDisabled state, return an error right away
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ // The write must not span block boundaries.
+ // We need to check each variable individually because adding two large values together overflows.
+ if ( ( Offset >= BlockSize ) ||
+ ( *NumBytes > BlockSize ) ||
+ ( (Offset + *NumBytes) > BlockSize ) ) {
+ DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // We must have some bytes to write
+ if (*NumBytes == 0) {
+ DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // Allocate runtime memory to read in the NOR Flash data.
+ // Since the intention is to use this with Variable Services and since these are runtime,
+ // allocate the memory from the runtime pool.
+ BlockBuffer = AllocateRuntimePool(BlockSize);
+
+ // Check we did get some memory
+ if( BlockBuffer == NULL ) {
+ DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - Can not allocate BlockBuffer @ 0x%08x.\n", BlockBuffer));
+ return EFI_DEVICE_ERROR;
+ }
+
+ // Read NOR Flash data into shadow buffer
+ TempStatus = NorFlashReadBlocks(Instance, Lba, BlockSize, BlockBuffer);
+ if (EFI_ERROR (TempStatus)) {
+ // Return one of the pre-approved error statuses
+ Status = EFI_DEVICE_ERROR;
+ goto FREE_MEMORY;
+ }
+
+ // Put the data at the appropriate location inside the buffer area
+ CopyMem((BlockBuffer + Offset), Buffer, *NumBytes);
+
+ // Write the modified buffer back to the NorFlash
+ Status = NorFlashWriteBlocks(Instance, Lba, BlockSize, BlockBuffer);
+ if (EFI_ERROR (TempStatus)) {
+ // Return one of the pre-approved error statuses
+ Status = EFI_DEVICE_ERROR;
+ goto FREE_MEMORY;
+ }
+
+FREE_MEMORY:
+ FreePool(BlockBuffer);
+ return Status;
+}
+
+/**
+ Erases and initialises a firmware volume block.
+
+ The EraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the EraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the EraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to EraseBlocks() must be fully
+ flushed to the hardware before the EraseBlocks() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ... The variable argument list is a list of tuples.
+ Each tuple describes a range of LBAs to erase
+ and consists of the following:
+ - An EFI_LBA that indicates the starting LBA
+ - A UINTN that indicates the number of blocks to erase.
+
+ The list is terminated with an EFI_LBA_LIST_TERMINATOR.
+ For example, the following indicates that two ranges of blocks
+ (5-7 and 10-11) are to be erased:
+ EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
+
+ @retval EFI_SUCCESS The erase request successfully completed.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be written.
+ The firmware device may have been partially erased.
+
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable argument list do
+ not exist in the firmware volume.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ )
+{
+ EFI_STATUS Status;
+ VA_LIST args;
+ UINTN BlockAddress; // Physical address of Lba to erase
+ EFI_LBA StartingLba; // Lba from which we start erasing
+ UINTN NumOfLba; // Number of Lba blocks to erase
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n"));
+
+ Status = EFI_SUCCESS;
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE) {
+ // Firmware volume is in WriteDisabled state
+ DEBUG ((EFI_D_ERROR, "FvbEraseBlocks: ERROR - Device is in WriteDisabled state.\n"));
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Before erasing, check the entire list of parameters to ensure all specified blocks are valid
+
+ VA_START (args, This);
+
+ do {
+
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ //Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (args, UINT32);
+
+ // All blocks must be within range
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Check if: ( StartingLba=%ld + NumOfLba=%d - 1 ) > LastBlock=%ld.\n", StartingLba, NumOfLba, Instance->Media.LastBlock));
+ if ((NumOfLba == 0) || ((StartingLba + NumOfLba - 1) > Instance->Media.LastBlock)) {
+ VA_END (args);
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Check if: ( StartingLba=%ld + NumOfLba=%d - 1 ) > LastBlock=%ld.\n", StartingLba, NumOfLba, Instance->Media.LastBlock));
+ DEBUG ((EFI_D_ERROR, "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+
+ } while (TRUE);
+
+ VA_END (args);
+
+ // To get here, all must be ok, so start erasing
+
+ VA_START (args, This);
+
+ do {
+
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ // Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (args, UINT32);
+
+ // Go through each one and erase it
+ while (NumOfLba > 0) {
+
+ // Get the physical address of Lba to erase
+ BlockAddress = GET_NOR_BLOCK_ADDRESS(
+ Instance->BaseAddress,
+ StartingLba,
+ Instance->Media.BlockSize
+ );
+
+ // Erase it
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n", StartingLba, BlockAddress));
+ Status = NorFlashUnlockAndEraseSingleBlock(BlockAddress);
+ if (EFI_ERROR(Status)) {
+ VA_END (args);
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+ // Move to the next Lba
+ StartingLba++;
+ NumOfLba--;
+ }
+
+ } while (TRUE);
+
+ VA_END (args);
+
+EXIT:
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+NorFlashFvbInitialize (
+ IN NOR_FLASH_INSTANCE* Instance
+ ) {
+ EFI_STATUS Status;
+
+ DEBUG((DEBUG_BLKIO,"NorFlashFvbInitialize\n"));
+
+ Status = NorFlashBlkIoInitialize(Instance);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR,"NorFlashFvbInitialize: ERROR - Failed to initialize FVB\n"));
+ return Status;
+ }
+ Instance->Initialized = TRUE;
+
+ // Determine if there is a valid header at the beginning of the NorFlash
+ Status = ValidateFvHeader (Instance);
+ if (EFI_ERROR(Status)) {
+ // There is no valid header, so time to install one.
+ DEBUG((EFI_D_ERROR,"NorFlashFvbInitialize: ERROR - The FVB Header is not valid. Install a correct one for this volume.\n"));
+
+ // Erase all the NorFlash that is reserved for variable storage
+ Status = FvbEraseBlocks ( &Instance->FvbProtocol, (EFI_LBA)0, (UINT32)(Instance->Media.LastBlock + 1), EFI_LBA_LIST_TERMINATOR );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Install all appropriate headers
+ InitializeFvAndVariableStoreHeaders ( Instance );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ }
+
+ return Status;
+}
--- /dev/null
+#/** @file
+#
+# Component discription file for NorFlashDxe module
+#
+# Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmPlatformBds
+ FILE_GUID = 5a50aa81-c3ae-4608-a0e3-41a2e69baf94
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = BdsInitialize
+
+[Sources.common]
+ BdsEntry.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ BdsLib
+ TimerLib
+ PerformanceLib
+ UefiBootServicesTableLib
+ DebugLib
+
+[Guids]
+
+[Protocols]
+ gEfiBdsArchProtocolGuid
+ gEfiSimpleTextInProtocolGuid
+ gEfiDevicePathToTextProtocolGuid
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdLinuxKernelDP
+ gArmTokenSpaceGuid.PcdLinuxAtag
+ gArmTokenSpaceGuid.PcdFdtDP
+
+[Depex]
+ TRUE
--- /dev/null
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/BdsLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PerformanceLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/PcdLib.h>
+
+#include <Protocol/Bds.h>
+#include <Protocol/DevicePathToText.h>
+
+#include <Guid/GlobalVariable.h>
+
+#define MAX_CMD_LINE 256
+
+VOID
+EFIAPI
+BdsEntry (
+ IN EFI_BDS_ARCH_PROTOCOL *This
+ );
+
+EFI_HANDLE mBdsImageHandle = NULL;
+EFI_BDS_ARCH_PROTOCOL gBdsProtocol = {
+ BdsEntry,
+};
+
+EFI_STATUS GetEnvironmentVariable (
+ IN CONST CHAR16* VariableName,
+ IN VOID* DefaultValue,
+ IN UINTN DefaultSize,
+ OUT VOID** Value)
+{
+ EFI_STATUS Status;
+ UINTN Size;
+
+ // Try to get the variable size.
+ *Value = NULL;
+ Size = 0;
+ Status = gRT->GetVariable ((CHAR16 *) VariableName, &gEfiGlobalVariableGuid, NULL, &Size, *Value);
+ if (Status == EFI_NOT_FOUND) {
+ // If the environment variable does not exist yet then set it with the default value
+ Status = gRT->SetVariable (
+ (CHAR16*)VariableName,
+ &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ DefaultSize,
+ DefaultValue
+ );
+ *Value = DefaultValue;
+ } else if (Status == EFI_BUFFER_TOO_SMALL) {
+ // Get the environment variable value
+ *Value = AllocatePool (Size);
+ if (*Value == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status = gRT->GetVariable ((CHAR16 *)VariableName, &gEfiGlobalVariableGuid, NULL, &Size, *Value);
+ if (EFI_ERROR (Status)) {
+ FreePool(*Value);
+ return EFI_INVALID_PARAMETER;
+ }
+ } else {
+ *Value = DefaultValue;
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+VOID InitializeConsole (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN NoHandles;
+ EFI_HANDLE *Buffer;
+
+ //
+ // Now we need to setup the EFI System Table with information about the console devices.
+ // This code is normally in the console spliter driver on platforms that support multiple
+ // consoles at the same time
+ //
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextOutProtocolGuid, NULL, &NoHandles, &Buffer);
+ if (!EFI_ERROR (Status)) {
+ // Use the first SimpleTextOut we find and update the EFI System Table
+ gST->ConsoleOutHandle = Buffer[0];
+ gST->StandardErrorHandle = Buffer[0];
+ Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextOutProtocolGuid, (VOID **)&gST->ConOut);
+ ASSERT_EFI_ERROR (Status);
+
+ gST->StdErr = gST->ConOut;
+
+ FreePool (Buffer);
+ }
+
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextInProtocolGuid, NULL, &NoHandles, &Buffer);
+ if (!EFI_ERROR (Status)) {
+ // Use the first SimpleTextIn we find and update the EFI System Table
+ gST->ConsoleInHandle = Buffer[0];
+ Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextInProtocolGuid, (VOID **)&gST->ConIn);
+ ASSERT_EFI_ERROR (Status);
+
+ FreePool (Buffer);
+ }
+}
+
+EFI_STATUS
+GetHIInputAscii (
+ CHAR8 *CmdLine,
+ UINTN MaxCmdLine
+) {
+ UINTN CmdLineIndex;
+ UINTN WaitIndex;
+ CHAR8 Char;
+ EFI_INPUT_KEY Key;
+ EFI_STATUS Status;
+
+ CmdLine[0] = '\0';
+
+ for (CmdLineIndex = 0; CmdLineIndex < MaxCmdLine; ) {
+ Status = gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &WaitIndex);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
+ ASSERT_EFI_ERROR (Status);
+
+ Char = (CHAR8)Key.UnicodeChar;
+ if ((Char == '\n') || (Char == '\r') || (Char == 0x7f)) {
+ CmdLine[CmdLineIndex] = '\0';
+ AsciiPrint ("\n");
+ return EFI_SUCCESS;
+ } else if ((Char == '\b') || (Key.ScanCode == SCAN_LEFT) || (Key.ScanCode == SCAN_DELETE)){
+ if (CmdLineIndex != 0) {
+ CmdLineIndex--;
+ AsciiPrint ("\b \b");
+ }
+ } else {
+ CmdLine[CmdLineIndex++] = Char;
+ AsciiPrint ("%c", Char);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+VOID
+ListDevicePaths (
+ IN BOOLEAN AllDrivers
+) {
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ EFI_DEVICE_PATH_PROTOCOL* DevicePathProtocol;
+ CHAR16* String;
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* EfiDevicePathToTextProtocol;
+
+ if (AllDrivers) {
+ BdsConnectAllDrivers();
+ }
+
+ Status = gBS->LocateProtocol(&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&EfiDevicePathToTextProtocol);
+ if (EFI_ERROR (Status)) {
+ AsciiPrint ("Did not find the DevicePathToTextProtocol.\n");
+ return;
+ }
+
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiDevicePathProtocolGuid, NULL, &HandleCount, &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ AsciiPrint ("No device path found\n");
+ return;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathProtocol);
+ String = EfiDevicePathToTextProtocol->ConvertDevicePathToText(DevicePathProtocol,TRUE,TRUE);
+ Print (L"\t- [%d] %s\n",Index, String);
+ }
+}
+
+INTN BdsComparefile (
+ IN CHAR16 *DeviceFilePath1,
+ IN CHAR16 *DeviceFilePath2,
+ VOID **FileImage1,VOID **FileImage2,UINTN* FileSize
+ );
+
+/**
+ This function uses policy data from the platform to determine what operating
+ system or system utility should be loaded and invoked. This function call
+ also optionally make the use of user input to determine the operating system
+ or system utility to be loaded and invoked. When the DXE Core has dispatched
+ all the drivers on the dispatch queue, this function is called. This
+ function will attempt to connect the boot devices required to load and invoke
+ the selected operating system or system utility. During this process,
+ additional firmware volumes may be discovered that may contain addition DXE
+ drivers that can be dispatched by the DXE Core. If a boot device cannot be
+ fully connected, this function calls the DXE Service Dispatch() to allow the
+ DXE drivers from any newly discovered firmware volumes to be dispatched.
+ Then the boot device connection can be attempted again. If the same boot
+ device connection operation fails twice in a row, then that boot device has
+ failed, and should be skipped. This function should never return.
+
+ @param This The EFI_BDS_ARCH_PROTOCOL instance.
+
+ @return None.
+
+**/
+VOID
+EFIAPI
+BdsEntry (
+ IN EFI_BDS_ARCH_PROTOCOL *This
+ )
+{
+ EFI_STATUS Status;
+ CHAR8 CmdLine[MAX_CMD_LINE];
+ VOID* DefaultVariableValue;
+ UINTN DefaultVariableSize;
+ CHAR16 *LinuxKernelDP;
+ CHAR8 *LinuxAtag;
+ CHAR16 *FdtDP;
+
+ PERF_END (NULL, "DXE", NULL, 0);
+ PERF_START (NULL, "BDS", NULL, 0);
+
+ InitializeConsole();
+
+ while (1) {
+ // Get the Linux Kernel Device Path from Environment Variable
+ DefaultVariableValue = (VOID*)PcdGetPtr(PcdLinuxKernelDP);
+ DefaultVariableSize = StrSize((CHAR16*)DefaultVariableValue);
+ GetEnvironmentVariable(L"LinuxKernelDP",DefaultVariableValue,DefaultVariableSize,(VOID**)&LinuxKernelDP);
+
+ // Get the Linux ATAG from Environment Variable
+ DefaultVariableValue = (VOID*)PcdGetPtr(PcdLinuxAtag);
+ DefaultVariableSize = AsciiStrSize((CHAR8*)DefaultVariableValue);
+ GetEnvironmentVariable(L"LinuxAtag",DefaultVariableValue,DefaultVariableSize,(VOID**)&LinuxAtag);
+
+ // Get the FDT Device Path from Environment Variable
+ DefaultVariableValue = (VOID*)PcdGetPtr(PcdFdtDP);
+ DefaultVariableSize = StrSize((CHAR16*)DefaultVariableValue);
+ GetEnvironmentVariable(L"FdtDP",DefaultVariableValue,DefaultVariableSize,(VOID**)&FdtDP);
+
+ AsciiPrint ("1. Start EBL\n\r");
+ AsciiPrint ("2. List Device Paths of all the drivers\n");
+ AsciiPrint ("3. Start Linux\n");
+ Print (L"\t- Kernel: %s\n", LinuxKernelDP);
+ AsciiPrint ("\t- Atag: %a\n", LinuxAtag);
+ Print (L"\t- Fdt: %s\n", FdtDP);
+ AsciiPrint ("Choice: ");
+
+ Status = GetHIInputAscii(CmdLine,MAX_CMD_LINE);
+ ASSERT_EFI_ERROR (Status);
+ if (AsciiStrCmp(CmdLine,"1") == 0) {
+ // Start EBL
+ Status = BdsLoadApplication(L"Ebl");
+ if (Status == EFI_NOT_FOUND) {
+ AsciiPrint ("Error: EFI Application not found.\n");
+ } else {
+ AsciiPrint ("Error: Status Code: 0x%X\n",(UINT32)Status);
+ }
+ } else if (AsciiStrCmp(CmdLine,"2") == 0) {
+ ListDevicePaths (TRUE);
+ } else if (AsciiStrCmp(CmdLine,"3") == 0) {
+ // Start Linux Kernel
+ Status = BdsBootLinux(LinuxKernelDP,LinuxAtag,FdtDP);
+ if (EFI_ERROR(Status)) {
+ AsciiPrint ("Error: Fail to start Linux (0x%X)\n",(UINT32)Status);
+ }
+ } else {
+ AsciiPrint ("Error: Invalid choice.\n");
+ }
+ }
+}
+
+EFI_STATUS
+EFIAPI
+BdsInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ mBdsImageHandle = ImageHandle;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mBdsImageHandle,
+ &gEfiBdsArchProtocolGuid, &gBdsProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
--- /dev/null
+Porting UEFI to a ARM platform\r
+------------------------------\r
+1. Create the new platform directory under ArmPlatformPkg\r
+\r
+2. Create its DSC and FDF files into this new directory. These files can be copied from ArmVExpress-CTA9x4.dsc and ArmVExpress-CTA9x4.fdf; and adapted following the requirement of your platform. \r
+\r
+3. Set up the PCDs required by ArmPlatformPkg in your FDF or DSC files \r
+\r
+PCD Description\r
+gArmTokenSpaceGuid.PcdSecureFdBaseAddress : Base address of your Secure Firmware \r
+gArmTokenSpaceGuid.PcdSecureFdSize : Size in byte of your Secure Firmware gEmbeddedTokenSpaceGuid.\r
+PcdEmbeddedFdBaseAddress : Base Address of your Non-Secure Firmware gEmbeddedTokenSpaceGuid.\r
+PcdEmbeddedFdSize : Size in bytes of your Non-Secure Firmware \r
+gArmTokenSpaceGuid.PcdL2x0ControllerBase : Base Address of your L2x0 controller \r
+gArmTokenSpaceGuid.PcdGicDistributorBase : Base address of the Distributor of your General Interrupt Controller gArmTokenSpaceGuid.\r
+PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller gArmVExpressTokenSpaceGuid.\r
+PcdCPUCoresSecStackBase : Top of Secure Stack for Secure World gArmVExpressTokenSpaceGuid.\r
+PcdCPUCoreSecStackSize : Size of the stack for each of the 4 CPU cores gArmVExpressTokenSpaceGuid.\r
+PcdCPUCoresSecMonStackBase : Top of Stack for Monitor World gArmVExpressTokenSpaceGuid.\r
+PcdCPUCoreSecMonStackSize : Size of the stack for each of the 4 CPU cores gArmVExpressTokenSpaceGuid.\r
+PcdCPUCoresNonSecStackBase : Top of SEC Stack for Normal World gArmVExpressTokenSpaceGuid.\r
+PcdCPUCoresNonSecStackSize : Size of the stack for each of the 4 CPU Cores gArmVExpressTokenSpaceGuid.\r
+PcdPeiServicePtrAddr : Cached value of PeiServicesTable \r
+\r
+4. Implement 'ArmPlatformLib' for your platform following the interface defined by ArmPlatformPkg\Include\Library\ArmPlatformLib.h.\r
+\r
+Functions to implement:\r
+\r
+VOID ArmPlatformIsMemoryInitialized(VOID);\r
+VOID ArmPlatformInitializeBootMemory(VOID);\r
+VOID ArmPlatformInitializeSystemMemory(VOID);\r
+VOID ArmPlatformBootRemapping(VOID);\r
+UINTN ArmPlatformTrustzoneSupported(VOID);\r
+VOID ArmPlatformTrustzoneInit(VOID);\r
+VOID ArmPlatformGetPeiMemory (\r
+ OUT UINTN* PeiMemoryBase,\r
+ OUT UINTN* PeiMemorySize);\r
+VOID ArmPlatformGetVirtualMemoryMap (\r
+ OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap);\r
+VOID ArmPlatformGetEfiMemoryMap (\r
+ OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap)\r
--- /dev/null
+==============================================\r
+= ARM RealView Emulation Board Documentation =\r
+==============================================\r
+\r
+\r
+Howto build UEFI RealView EB for RealTime System Model\r
+------------------------------------------------------\r
+\r
+1. Set up the environment. And build the EDK2\92s tools\r
+export EDK_TOOLS_PATH=`pwd`/BaseTools\r
+. edksetup.sh `pwd`/BaseTools/\r
+make -C $EDK_TOOLS_PATH\r
+\r
+2. Build the ARM RealView EB UEFI Firmware\r
+build -a ARM -p ArmPlatformPkg/ArmRealViewEBPkg/ArmRealViewEb-RTSM-A8.dsc -t RVCT\r
+\r
+\r
+Howto test UEFI RealView EB on RealTime System Model - Example Cortex A8\r
+------------------------------------------------------------------------\r
+\r
+ 1. Build 'ArmRealViewEb-RTSM-A8.dsc'\r
+\r
+ 2. To Run ArmRealViewEbPkg on the RTSM\r
+ 1. Start RealView Debugger\r
+ 2. Target > "Connect to Target"\r
+ 3. Add RTSM\r
+ 4. Configure this new RTSM.\r
+ 5. Choose CortexA8\r
+ 6. Setup the 'fname' of baseboard.flashldr_0 with your FD file (eg: c:\dev\edk2\Build\ArmRealViewEb-RTSM-A8\DEBUG_RVCT\FV\ARMREALVIEWEB_EFI.fd)\r
+ 7. Turn use_s8 to TRUE in baseboard.sp810_sysctrl\r
+ 8. Turn uart_enable to TRUE in baseboard.uart_0 \r
+ 4. Connect a telnet client to the port 5000 of your localhost\r
+ 5. Launch the program
\ No newline at end of file
--- /dev/null
+=======================================\r
+= ARM Versatile Express Documentation =\r
+=======================================\r
+\r
+Status\r
+------\r
+Build and Run on EDK2 Subversion revision 11251\r
+Requirements \r
+- RVCTv3 (untested) or RVCTv4 or ARMGCC (Code Sourcery q201009)\r
+- Using Ubuntu: gcc, make, uuid-dev \r
+- Using Cygwin: gcc, make, e2fsprogs (needed for uuid.h) \r
+\r
+Serial Terminal settings \r
+- Baud Rates: 38400\r
+- Data: 8 bit\r
+- Parity: None\r
+- Flow Control: None \r
+\r
+\r
+Use ICE debugger with Versatile Express \r
+---------------------------------------\r
+Prior to use ICE debugger with Versatile Express, you will need to update the version of the ICE's firmware.\r
+If you have not installed RealView 4.0 SP3, do it.\r
+Open "RealView ICE Update" and "Install Firmware Update ...". Install "[ARM_INSTALL_PATH]\RVI\Firmware\3.4\11\ARM-RVI-3.4.0-25-base.rvi" and "[ARM_INSTALL_PATH]\RVI\Firmware\3.4\22\ARM-RVI-3.4.59-59-patch.rvi". \r
+\r
+\r
+Howto build UEFI Versatile Express\r
+----------------------------------\r
+For Cygwin\r
+----------\r
+\r
+For the first time \r
+******************\r
+1. Get EDK2 from Tianocore Subversion repository\r
+svn co https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2 edk2 --username guest\r
+ \r
+2. Get FatPkg from EDK2 SVN repository: \r
+cd edk2\r
+svn co https://edk2-fatdriver2.svn.sourceforge.net/svnroot/edk2-fatdriver2/trunk/FatPkg FatPkg --username guest\r
+\r
+3. Set up the environment. And build the EDK2\92s tools\r
+export EDK_TOOLS_PATH=`pwd`/BaseTools\r
+. edksetup.sh `pwd`/BaseTools/\r
+make -C $EDK_TOOLS_PATH\r
+\r
+4. Build the ARM Versatile Express UEFI Firmware\r
+build -a ARM -p ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc -t RVCTCYGWIN\r
+\r
+5. Edit the ARM Versatile Express configuration file config.txt to declare the location of the UEFI firmware in NOR Flash\r
+TOTALIMAGES: 5 ;Number of Images (Max : 32)\r
+NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE\r
+NOR0ADDRESS: BOOT ;Image Flash Address\r
+NOR0FILE: \SOFTWARE\bm_v209.axf ;Image File Name\r
+NOR1UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE\r
+NOR1ADDRESS: 44000000 ;Image Flash Address\r
+NOR1FILE: \SOFTWARE\sec_uefi.bin ;Image File Name\r
+NOR1LOAD: 0 ;Image Load Address\r
+NOR1ENTRY: 0 ;Image Entry Point\r
+NOR2UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE\r
+NOR2ADDRESS: 45000000 ;Image Flash Address\r
+NOR2FILE: \SOFTWARE\uefi.bin ;Image File Name\r
+NOR2LOAD: 45000000 ;Image Load Address\r
+NOR2ENTRY: 45000000 ;Image Entry Point\r
+NOR3UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE\r
+NOR3ADDRESS: 46000000 ;Image Flash Address\r
+NOR3FILE: \SOFTWARE\kernel.bin ;Image File Name\r
+NOR3LOAD: 46000000 ;Image Load Address\r
+NOR3ENTRY: 46000000 ;Image Entry Point\r
+NOR4UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE\r
+NOR4ADDRESS: 40000000 ;Image Flash Address\r
+NOR4NAME: BOOTSCRIPT ;Image Name\r
+NOR4FILE: \SOFTWARE\bootscr.txt ;Image File Name\r
+\r
+6. To select second NOR Flash as a booting device, replace in the ARM Versatile Express file \SITE1\HBI0191B\board.txt:\r
+SCC: 0x004 0x00001F09\r
+By:\r
+SCC: 0x004 0x10001F09\r
+\r
+7. Copy Build/ArmVExpress-CTA9x4/DEBUG_RVCTCYGWIN/FV/SEC_ARMVEXPRESS_EFI.fd to the ARM Versatile Express mass storage (available when the board is connected through USB to your host machine) under the folder SOTWARE and name sec_uefi.bin. Example for cygwin:\r
+cp Build/ArmVExpress-CTA9x4/DEBUG_RVCTCYGWIN/FV/SEC_ARMVEXPRESS_EFI.fd /cygdrive/e/SOFTWARE/sec_uefi.bin\r
+\r
+8. Start the ARM Versatile Express board. You should read \93Waiting for firmware at 0x80000000 ...\94 on the serial port. \r
+\r
+9. Copy ARMVEXPRESS_EFI.fd at 0x80000000 with RealView Debugger\r
+readfile,raw,nowarn "[EDK2_PATH]\Build\ArmVExpress-CTA9x4\DEBUG_RVCTCYGWIN\FV\ARMVEXPRESS_EFI.fd"=0x80000000\r
+\r
+10. Resume the execution from RealView Debugger\r
+\r
+For all subsequent times\r
+************************\r
+1. Build ARM Versatile Express UEFI Firmware\r
+build -a ARM -p ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc -t RVCTCYGWIN\r
+\r
+2. Start the ARM Versatile Express board. You should read \93Waiting for firmware at 0x80000000 ...\94 on the serial port. \r
+\r
+3. Copy ARMVEXPRESS_EFI.fd at 0x80000000 with RealView Debugger\r
+readfile,raw,nowarn "[EDK2_PATH]\Build\ArmVExpress-CTA9x4\DEBUG_RVCTCYGWIN\FV\ARMVEXPRESS_EFI.fd"=0x80000000\r
+\r
+4. Resume the execution \r
+\r
+\r
+For RealView Compiler Toolchain on Windows\r
+------------------------------------------\r
+The command line window needs to be the one from Visual Studio to get the environment variables required to get some development tools (the windows compiler for BaseTools and `nmake`).\r
+The EDK2 toolchain name for ARM RealView Compiler Toolchain under a Windows environment is `RVCT`. The EDK2 build system will automatically pick up the RVCT toolchain defined in your PATH. If you want to use a specific version, set the environment variable 'RVCT_TOOLS_PATH': \r
+set RVCT_TOOLS_PATH=[YOUR_TOOLCHAIN_PATH]\r
+\r
+\r
+For RealView Compiler Toolchain on Linux\r
+----------------------------------------\r
+The EDK2 toolchain name for ARM RealView under a Linux environment is `RVCTLINUX`. The EDK2 build system will automatically pick up the RVCT toolchain defined in your PATH. If you want to use a specific version, set the environment variable 'RVCT_TOOLS_PATH': \r
+export RVCT_TOOLS_PATH=[YOUR_TOOLCHAIN_PATH]\r
+\r
+\r
+For ARM GNU GCC on Linux\r
+------------------------\r
+The EDK2 toolchain name for ARM RealView under a Linux environment is `ARMGCC`. EDK2 requires Bash Shell to be built on Linux.\r
+The ARMGCC toolchain is expected to be found in your PATH. ARM Edk2 has been tested with 'CodeSourcery G++ Lite 2010.09-51 - EABI Version'.\r
+If you decide to use a specific version, set the environment variable 'ARMGCC_TOOLS_PATH': \r
+export ARMGCC_TOOLS_PATH=[YOUR_CODESOURCERY_TOOLCHAIN_PATH]\r
+Example:\r
+export ARMGCC_TOOLS_PATH=/Work/arm-2010.09/bin/\r
+Compiling UEFI ArmVE as a standalone firmware \r
+The full ArmVe UEFI firmware can be written into NOR Flash to allow the entire boot sequence to be done after a cold boot.\r
+\r
+\r
+To support the standalone mode:\r
+-------------------------------\r
+build -a ARM -p ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc -t RVCTCYGWIN -D EDK2_ARMVE_STANDALONE=1\r
+ARMVEXPRESS_EFI.fd is required to be copied into the ARM Versatile Express board:\r
+cp Build/ArmVExpress-CTA9x4-Standalone/DEBUG_RVCTCYGWIN/FV/SEC_ARMVEXPRESS_EFI.fd /cygdrive/e/SOFTWARE/sec_uefi.bin\r
+cp Build/ArmVExpress-CTA9x4-Standalone/DEBUG_RVCTCYGWIN/FV/ARMVEXPRESS_EFI.fd /cygdrive/e/SOFTWARE/uefi.bin\r
+\r
+\r
+Trustzone Support\r
+-----------------\r
+ArmVE's UEFI supports booting Trustzone (two worlds: Secure and Normal Worlds) and No Trustzone (one world: the CPU remains in Secure World) supports. Trustzone support is enabled by Enabling SMC TZASC in the Test Chip SCC Register 1. This register can only be changed by editing the configuration file of your Versatile Express board: E:\SITE1\HBI0191B\board.txt Changing: \r
+SCC: 0x004 0x10001F09\r
+For: \r
+SCC: 0x004 0x10003F09\r
+\r
+\r
+Booting Linux\r
+-------------\r
+ArmVe's BDS expects a Linux kernel at 0x46000000 (2nd NOR Flash). This location is also defined in the config.txt file of the motherboard (same file as the one that defines UEFI firmwares location). The Linux kernel at this location is a copy of \SOFTWARE\kernel.bin as refered in config.txt.\r
+To boot on a different kernel, you will need to edit [EDK2_ROOT]\ArmVePkg\Bds\BdsEntry.c \r
+#define LINUX_KERNEL L"VenHw(02118005-9DA7-443a-92D5-781F022AEDBB)/MemoryMapped(0,0x46000000,0x462F0000)"\r
+#define FDT 0\r
+#define LINUX_ATAG "rdinit=/bin/ash debug earlyprintk console=ttyAMA0,38400 mem=1G"\r
+The macros LINUX_KERNEL and FDT expect a UEFI Device Path. \r
+\r
+Example of UEFI Device Path: \r
+\r
+// Load FDT binary from the Firmware Volume (mapped at 0x80000000)\r
+#define LINUX_KERNEL L"MemoryMapped(11,0x80000000,0x6FEFFFFF)\\zImage.fdt"\r
+\r
+// Linux Kernel from a SD Card\r
+#define LINUX_KERNEL L"VenHw(621B6FA5-4DC1-476F-B9D8-52C557D81070)/HD(1,MBR,0x00000000,0xF9,0x3C8907)\\boot\\zImage.fdt"\r
+\r
+// Kernel from SATA HD - Partition 2\r
+#define LINUX_KERNEL L"Acpi(PNP0A03,0)/Pci(0|0)/Pci(0|0)/Pci(5|0)/Pci(0|0)/Sata(0,0,0)/HD(2,MBR,0x00076730,0x1F21BF,0x1F21BF)\\boot\\zImage.fdt"\r
+\r
+// Kernel from NOR Flash\r
+#define LINUX_KERNEL L"VenHw(02118005-9DA7-443a-92D5-781F022AEDBB)/MemoryMapped(0,0x46000000,0x462F0000)"\r
+\r
+\r
+UEFI Memory Maps for ARM Versatile Express \r
+------------------------------------------\r
+Figure 1: EFI Memory Map in the Temporary Memory\r
+See ArmVExpressMemoryMaps_TemporaryMemoryMap.png\r
+\r
+Figure 2: CPU Core stack in the Temporary Memory \r
+See ArmVExpressMemoryMaps_TemporaryStack.png\r
+\r
+Figure 3: EFI Memory Map in the Permanent Memory\r
+See ArmVExpressMemoryMaps_PermanentMemoryMap.png\r
--- /dev/null
+/** @file
+ Template for Timer Architecture Protocol driver of the ARM flavor
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+
+#include <Protocol/Timer.h>
+#include <Protocol/HardwareInterrupt.h>
+
+#include <Drivers/SP804Timer.h>
+#include <ArmPlatform.h>
+
+// The notification function to call on every timer interrupt.
+volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+// The current period of the timer interrupt
+volatile UINT64 mTimerPeriod = 0;
+
+// Cached copy of the Hardware Interrupt protocol instance
+EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
+
+// Cached interrupt vector
+UINTN gVector;
+
+UINT32 mLastTickCount;
+
+/**
+
+ C Interrupt Handler called in the interrupt context when Source interrupt is active.
+
+
+ @param Source Source of the interrupt. Hardware routing off a specific platform defines
+ what source means.
+
+ @param SystemContext Pointer to system register context. Mostly used by debuggers and will
+ update the system context after the return from the interrupt if
+ modified. Don't change these values unless you know what you are doing
+
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ EFI_TPL OriginalTPL;
+
+ //
+ // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
+ // that raise to TPL_HIGH and then restore back to current level. Thus we need
+ // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
+ //
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+ // clear the periodic interrupt
+
+ MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_INT_CLR_REG, 0);
+
+ // signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
+ gInterrupt->EndOfInterrupt (gInterrupt, Source);
+
+ if (mTimerNotifyFunction) {
+ mTimerNotifyFunction (mTimerPeriod);
+ }
+
+ gBS->RestoreTPL (OriginalTPL);
+}
+
+/**
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+ register a handler for the timer interrupt, so it can know
+ how much time has passed. This information is used to
+ signal timer based events. NULL will unregister the handler.
+ @retval EFI_SUCCESS The timer handler was registered.
+ @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+ registered.
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+ previously registered.
+ @retval EFI_DEVICE_ERROR The timer handler could not be registered.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverRegisterHandler (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_TIMER_NOTIFY NotifyFunction
+ )
+{
+ if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ mTimerNotifyFunction = NotifyFunction;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Make sure all ArrmVe Timers are disabled
+**/
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ // Disable timer 0 if enabled
+ if (MmioRead32(SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ MmioAnd32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, 0);
+ }
+
+ // Disable timer 1 if enabled
+ if (MmioRead32(SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ MmioAnd32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, 0);
+ }
+
+ // Disable timer 2 if enabled
+ if (MmioRead32(SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ MmioAnd32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, 0);
+ }
+
+ // Disable timer 3 if enabled
+ if (MmioRead32(SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ MmioAnd32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, 0);
+ }
+}
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverSetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod
+ )
+{
+ EFI_STATUS Status;
+ UINT64 TimerTicks;
+
+ // always disable the timer
+ MmioAnd32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, ~SP804_TIMER_CTRL_ENABLE);
+
+ if (TimerPeriod == 0) {
+ // leave timer disabled from above, and...
+
+ // disable timer 0/1 interrupt for a TimerPeriod of 0
+ Status = gInterrupt->DisableInterruptSource (gInterrupt, gVector);
+ } else {
+ // Convert TimerPeriod into 1MHz clock counts (us units = 100ns units / 10)
+ TimerTicks = DivU64x32 (TimerPeriod, 10);
+
+ // if it's larger than 32-bits, pin to highest value
+ if (TimerTicks > 0xffffffff) {
+
+ TimerTicks = 0xffffffff;
+
+ }
+
+ // Program the SP804 timer with the new count value
+ MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_LOAD_REG, TimerTicks);
+
+ // enable the timer
+ MmioOr32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
+
+ // enable timer 0/1 interrupts
+ Status = gInterrupt->EnableInterruptSource (gInterrupt, gVector);
+ }
+
+ // Save the new timer period
+ mTimerPeriod = TimerPeriod;
+ return Status;
+}
+
+/**
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ if (TimerPeriod == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *TimerPeriod = mTimerPeriod;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function generates a soft timer interrupt. If the platform does not support soft
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+ enabled when this service is called, then the registered handler will be invoked. The
+ registered handler should not be able to distinguish a hardware-generated timer
+ interrupt from a software-generated timer interrupt.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+ @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGenerateSoftInterrupt (
+ IN EFI_TIMER_ARCH_PROTOCOL *This
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Interface structure for the Timer Architectural Protocol.
+
+ @par Protocol Description:
+ This protocol provides the services to initialize a periodic timer
+ interrupt, and to register a handler that is called each time the timer
+ interrupt fires. It may also provide a service to adjust the rate of the
+ periodic timer interrupt. When a timer interrupt occurs, the handler is
+ passed the amount of time that has passed since the previous timer
+ interrupt.
+
+ @param RegisterHandler
+ Registers a handler that will be called each time the
+ timer interrupt fires. TimerPeriod defines the minimum
+ time between timer interrupts, so TimerPeriod will also
+ be the minimum time between calls to the registered
+ handler.
+
+ @param SetTimerPeriod
+ Sets the period of the timer interrupt in 100 nS units.
+ This function is optional, and may return EFI_UNSUPPORTED.
+ If this function is supported, then the timer period will
+ be rounded up to the nearest supported timer period.
+
+
+ @param GetTimerPeriod
+ Retrieves the period of the timer interrupt in 100 nS units.
+
+ @param GenerateSoftInterrupt
+ Generates a soft timer interrupt that simulates the firing of
+ the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
+ a period of time.
+
+**/
+EFI_TIMER_ARCH_PROTOCOL gTimer = {
+ TimerDriverRegisterHandler,
+ TimerDriverSetTimerPeriod,
+ TimerDriverGetTimerPeriod,
+ TimerDriverGenerateSoftInterrupt
+};
+
+
+/**
+ Initialize the state information for the Timer Architectural Protocol and
+ the Timer Debug support protocol that allows the debugger to break into a
+ running program.
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+EFIAPI
+TimerInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_HANDLE Handle = NULL;
+ EFI_STATUS Status;
+
+ // Find the interrupt controller protocol. ASSERT if not found.
+ Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
+ ASSERT_EFI_ERROR (Status);
+
+ // Configure 1MHz clock
+ MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
+
+ // configure timer 1 for free running operation, 32 bits, no prescaler, interrupt disabled
+ MmioWrite32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
+
+ // enable the free running timer
+ MmioOr32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
+
+ // record free running tick value (should be close to 0xffffffff)
+ mLastTickCount = MmioRead32 (SP804_TIMER1_BASE + SP804_TIMER_CURRENT_REG);
+
+ // Disable the timer
+ Status = TimerDriverSetTimerPeriod (&gTimer, 0);
+ ASSERT_EFI_ERROR (Status);
+
+ // Install interrupt handler
+ gVector = TIMER01_INTERRUPT_NUM;
+ Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+
+ // configure periodic timer (TIMER0) for 1MHz operation
+ MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
+
+ // configure timer 0 for periodic operation, 32 bits, no prescaler, and interrupt enabled
+ MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_PERIODIC | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1 | SP804_TIMER_CTRL_INT_ENABLE);
+
+ // Set up default timer
+ Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
+ ASSERT_EFI_ERROR (Status);
+
+ // Install the Timer Architectural Protocol onto a new handle
+ Status = gBS->InstallMultipleProtocolInterfaces(
+ &Handle,
+ &gEfiTimerArchProtocolGuid, &gTimer,
+ NULL
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
--- /dev/null
+#/** @file
+#
+# Component discription file for Timer module
+#
+# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmVeTimerDxe
+ FILE_GUID = a73d663d-a491-4278-9a69-9521be3379f2
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = TimerInitialize
+
+[Sources.common]
+ SP804Timer.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ UefiRuntimeServicesTableLib
+ UefiLib
+ UefiBootServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ UefiDriverEntryPoint
+ IoLib
+
+[Guids]
+
+[Protocols]
+ gEfiTimerArchProtocolGuid
+ gHardwareInterruptProtocolGuid
+
+[Pcd.common]
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod
+
+[Depex]
+ gHardwareInterruptProtocolGuid
--- /dev/null
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PL011_UART_H__
+#define __PL011_UART_H__
+
+#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
+
+// PL011 Registers
+#define UARTDR 0x000
+#define UARTRSR 0x004
+#define UARTECR 0x004
+#define UARTFR 0x018
+#define UARTILPR 0x020
+#define UARTIBRD 0x024
+#define UARTFBRD 0x028
+#define UARTLCR_H 0x02C
+#define UARTCR 0x030
+#define UARTIFLS 0x034
+#define UARTIMSC 0x038
+#define UARTRIS 0x03C
+#define UARTMIS 0x040
+#define UARTICR 0x044
+#define UARTDMACR 0x048
+
+#define UART_115200_IDIV 13 // Integer Part
+#define UART_115200_FDIV 1 // Fractional Part
+#define UART_38400_IDIV 39
+#define UART_38400_FDIV 5
+#define UART_19200_IDIV 12
+#define UART_19200_FDIV 37
+
+// data status bits
+#define UART_DATA_ERROR_MASK 0x0F00
+
+// status reg bits
+#define UART_STATUS_ERROR_MASK 0x0F
+
+// flag reg bits
+#define UART_TX_EMPTY_FLAG_MASK 0x80
+#define UART_RX_FULL_FLAG_MASK 0x40
+#define UART_TX_FULL_FLAG_MASK 0x20
+#define UART_RX_EMPTY_FLAG_MASK 0x10
+#define UART_BUSY_FLAG_MASK 0x08
+
+// control reg bits
+#define UART_CTSEN_CONTROL_MASK 0x8000
+#define UART_RTSEN_CONTROL_MASK 0x4000
+#define UART_RTS_CONTROL_MASK 0x0800
+#define UART_DTR_CONTROL_MASK 0x0400
+
+#endif
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+\r
+#ifndef _SP804_TIMER_H__\r
+#define _SP804_TIMER_H__\r
+\r
+// SP804 Timer constants\r
+#define SP804_TIMER_LOAD_REG 0x00\r
+#define SP804_TIMER_CURRENT_REG 0x04\r
+#define SP804_TIMER_CONTROL_REG 0x08\r
+#define SP804_TIMER_INT_CLR_REG 0x0C\r
+#define SP804_TIMER_RAW_INT_STS_REG 0x10\r
+#define SP804_TIMER_MSK_INT_STS_REG 0x14\r
+#define SP804_TIMER_BG_LOAD_REG 0x18\r
+\r
+// Timer control register bit definitions\r
+#define SP804_TIMER_CTRL_ONESHOT BIT0\r
+#define SP804_TIMER_CTRL_32BIT BIT1\r
+#define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2)\r
+#define SP804_PRESCALE_DIV_1 0\r
+#define SP804_PRESCALE_DIV_16 BIT2\r
+#define SP804_PRESCALE_DIV_256 BIT3\r
+#define SP804_TIMER_CTRL_INT_ENABLE BIT5\r
+#define SP804_TIMER_CTRL_PERIODIC BIT6\r
+#define SP804_TIMER_CTRL_ENABLE BIT7\r
+\r
+// SP810 System Controller constants\r
+#define SP810_SYS_CTRL_REG 0x00\r
+#define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK\r
+#define SP810_SYS_CTRL_TIMER0_EN BIT16\r
+#define SP810_SYS_CTRL_TIMER1_TIMCLK BIT17 // 0=REFCLK, 1=TIMCLK\r
+#define SP810_SYS_CTRL_TIMER1_EN BIT18\r
+#define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK\r
+#define SP810_SYS_CTRL_TIMER2_EN BIT20\r
+#define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK\r
+#define SP810_SYS_CTRL_TIMER3_EN BIT22\r
+\r
+#endif\r
--- /dev/null
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _ARMPLATFORMLIB_H_
+#define _ARMPLATFORMLIB_H_
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include <Ppi/MasterBootMode.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Guid/MemoryTypeInformation.h>
+
+#include <Library/ArmLib.h>
+#include <ArmPlatform.h>
+
+/**
+ This structure is used by ArmVExpressGetEfiMemoryMap to describes a region of the EFI memory map
+
+ Every EFI regions of the system memory described by their physical start address and their size
+ can have different attributes. Some regions can be tested and other untested.
+
+**/
+typedef struct {
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
+ EFI_PHYSICAL_ADDRESS PhysicalStart;
+ UINT64 NumberOfBytes;
+} ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR;
+
+/**
+ Called at the early stage of the Boot phase to know if the memory has already been initialized
+
+ Running the code from the reset vector does not mean we start from cold boot. In some case, we
+ can go through this code with the memory already initialized.
+ Because this function is called at the early stage, the implementation must not use the stack.
+ Its implementation must probably done in assembly to ensure this requirement.
+
+ @return Return the condition value into the 'Z' flag
+
+**/
+VOID ArmPlatformIsMemoryInitialized(VOID);
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+VOID ArmPlatformInitializeBootMemory(VOID);
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID ArmPlatformInitializeSystemMemory(VOID);
+
+/**
+ Remap the memory at 0x0
+
+ Some platform requires or gives the ability to remap the memory at the address 0x0.
+ This function can do nothing if this feature is not relevant to your platform.
+
+**/
+VOID ArmPlatformBootRemapping(VOID);
+
+/**
+ Return if Trustzone is supported by your platform
+
+ A non-zero value must be returned if you want to support a Secure World on your platform.
+ ArmPlatformTrustzoneInit() will later set up the secure regions.
+ This function can return 0 even if Trustzone is supported by your processor. In this case,
+ the platform will continue to run in Secure World.
+
+ @return A non-zero value if Trustzone supported.
+
+**/
+UINTN ArmPlatformTrustzoneSupported(VOID);
+
+/**
+ Initialize the Secure peripherals and memory regions
+
+ If Trustzone is supported by your platform then this function makes the required initialization
+ of the secure peripherals and memory regions.
+
+**/
+VOID ArmPlatformTrustzoneInit(VOID);
+
+/**
+ Return the information about the memory region in permanent memory used by PEI
+
+ One of the PEI Module must install the permament memory used by PEI. This function returns the
+ information about this region for your platform to this PEIM module.
+
+ @param[out] PeiMemoryBase Base of the memory region used by PEI core and modules
+ @param[out] PeiMemorySize Size of the memory region used by PEI core and modules
+
+**/
+VOID ArmPlatformGetPeiMemory (
+ OUT UINTN* PeiMemoryBase,
+ OUT UINTN* PeiMemorySize
+ );
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID ArmPlatformGetVirtualMemoryMap (
+ OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+);
+
+/**
+ Return the EFI Memory Map of your platform
+
+ This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
+ Descriptor HOBs used by DXE core.
+
+ @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
+ EFI Memory region. This array must be ended by a zero-filled entry
+
+**/
+VOID ArmPlatformGetEfiMemoryMap (
+ OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
+);
+
+#endif
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/EblCmdLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/EfiFileLib.h>\r
+#include <Library/ArmDisassemblerLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/PerformanceLib.h>\r
+#include <Library/TimerLib.h>\r
+\r
+#include <Guid/DebugImageInfoTable.h>\r
+\r
+#include <Protocol/DebugSupport.h>\r
+#include <Protocol/LoadedImage.h>\r
+\r
+EFI_STATUS\r
+EblDumpMmu (\r
+ IN UINTN Argc,\r
+ IN CHAR8 **Argv\r
+ );\r
+\r
+/**\r
+ Simple arm disassembler via a library\r
+\r
+ Argv[0] - symboltable\r
+ Argv[1] - Optional qoted format string \r
+ Argv[2] - Optional flag\r
+\r
+ @param Argc Number of command arguments in Argv\r
+ @param Argv Array of strings that represent the parsed command line. \r
+ Argv[0] is the comamnd name\r
+\r
+ @return EFI_SUCCESS\r
+\r
+**/\r
+EFI_STATUS\r
+EblSymbolTable (\r
+ IN UINTN Argc,\r
+ IN CHAR8 **Argv\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugImageTableHeader = NULL;\r
+ EFI_DEBUG_IMAGE_INFO *DebugTable;\r
+ UINTN Entry;\r
+ CHAR8 *Format;\r
+ CHAR8 *Pdb;\r
+ UINT32 PeCoffSizeOfHeaders;\r
+ UINT32 ImageBase;\r
+ BOOLEAN Elf;\r
+ \r
+ // Need to add lots of error checking on the passed in string\r
+ // Default string is for RealView debugger\r
+ Format = (Argc > 1) ? Argv[1] : "load /a /ni /np %a &0x%x";\r
+ Elf = (Argc > 2) ? FALSE : TRUE;\r
+ \r
+ Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&DebugImageTableHeader);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ \r
+ DebugTable = DebugImageTableHeader->EfiDebugImageInfoTable;\r
+ if (DebugTable == NULL) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ for (Entry = 0; Entry < DebugImageTableHeader->TableSize; Entry++, DebugTable++) {\r
+ if (DebugTable->NormalImage != NULL) {\r
+ if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) && (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {\r
+ ImageBase = (UINT32)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;\r
+ PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)ImageBase);\r
+ Pdb = PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);\r
+ if (Pdb != NULL) {\r
+ if (Elf) {\r
+ // ELF and Mach-O images don't include the header so the linked address does not include header\r
+ ImageBase += PeCoffSizeOfHeaders;\r
+ } \r
+ AsciiPrint (Format, Pdb, ImageBase);\r
+ AsciiPrint ("\n");\r
+ } else {\r
+ }\r
+ }\r
+ } \r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Simple arm disassembler via a library\r
+\r
+ Argv[0] - disasm\r
+ Argv[1] - Address to start disassembling from\r
+ ARgv[2] - Number of instructions to disassembly (optional)\r
+\r
+ @param Argc Number of command arguments in Argv\r
+ @param Argv Array of strings that represent the parsed command line. \r
+ Argv[0] is the comamnd name\r
+\r
+ @return EFI_SUCCESS\r
+\r
+**/\r
+EFI_STATUS\r
+EblDisassembler (\r
+ IN UINTN Argc,\r
+ IN CHAR8 **Argv\r
+ )\r
+{\r
+ UINT8 *Ptr, *CurrentAddress;\r
+ UINT32 Address;\r
+ UINT32 Count;\r
+ CHAR8 Buffer[80];\r
+ UINT32 ItBlock;\r
+ \r
+ if (Argc < 2) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ \r
+ Address = AsciiStrHexToUintn (Argv[1]);\r
+ Count = (Argc > 2) ? (UINT32)AsciiStrHexToUintn (Argv[2]) : 20;\r
+\r
+ Ptr = (UINT8 *)(UINTN)Address; \r
+ ItBlock = 0;\r
+ do {\r
+ CurrentAddress = Ptr;\r
+ DisassembleInstruction (&Ptr, TRUE, TRUE, &ItBlock, Buffer, sizeof (Buffer));\r
+ AsciiPrint ("0x%08x: %a\n", CurrentAddress, Buffer);\r
+ } while (Count-- > 0);\r
+ \r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+CHAR8 *\r
+ImageHandleToPdbFileName (\r
+ IN EFI_HANDLE Handle\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;\r
+ CHAR8 *Pdb;\r
+ CHAR8 *StripLeading;\r
+\r
+ Status = gBS->HandleProtocol (Handle, &gEfiLoadedImageProtocolGuid, (VOID **)&LoadedImage);\r
+ if (EFI_ERROR (Status)) {\r
+ return "";\r
+ }\r
+\r
+ Pdb = PeCoffLoaderGetPdbPointer (LoadedImage->ImageBase);\r
+ StripLeading = AsciiStrStr (Pdb, "\\ARM\\");\r
+ if (StripLeading == NULL) {\r
+ StripLeading = AsciiStrStr (Pdb, "/ARM/");\r
+ if (StripLeading == NULL) {\r
+ return Pdb;\r
+ }\r
+ }\r
+ // Hopefully we hacked off the unneeded part\r
+ return (StripLeading + 5);\r
+}\r
+\r
+\r
+CHAR8 *mTokenList[] = {\r
+ /*"SEC",*/\r
+ "PEI",\r
+ "DXE",\r
+ /*"BDS",*/\r
+ NULL\r
+};\r
+\r
+/**\r
+ Simple arm disassembler via a library\r
+\r
+ Argv[0] - disasm\r
+ Argv[1] - Address to start disassembling from\r
+ ARgv[2] - Number of instructions to disassembly (optional)\r
+\r
+ @param Argc Number of command arguments in Argv\r
+ @param Argv Array of strings that represent the parsed command line. \r
+ Argv[0] is the comamnd name\r
+\r
+ @return EFI_SUCCESS\r
+\r
+**/\r
+EFI_STATUS\r
+EblPerformance (\r
+ IN UINTN Argc,\r
+ IN CHAR8 **Argv\r
+ )\r
+{\r
+ UINTN Key;\r
+ CONST VOID *Handle;\r
+ CONST CHAR8 *Token, *Module;\r
+ UINT64 Start, Stop, TimeStamp;\r
+ UINT64 Delta, TicksPerSecond, Milliseconds, Microseconds;\r
+ UINTN Index;\r
+\r
+ TicksPerSecond = GetPerformanceCounterProperties (NULL, NULL);\r
+\r
+ Key = 0;\r
+ do {\r
+ Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop);\r
+ if (Key != 0) {\r
+ if (AsciiStriCmp ("StartImage:", Token) == 0) {\r
+ if (Stop == 0) {\r
+ // The entry for EBL is still running so the stop time will be zero. Skip it\r
+ AsciiPrint (" running %a\n", ImageHandleToPdbFileName ((EFI_HANDLE)Handle));\r
+ } else {\r
+ Delta = Start - Stop;\r
+ Microseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000000), TicksPerSecond, NULL);\r
+ AsciiPrint ("%10ld us %a\n", Microseconds, ImageHandleToPdbFileName ((EFI_HANDLE)Handle));\r
+ }\r
+ }\r
+ }\r
+ } while (Key != 0);\r
+\r
+ AsciiPrint ("\n");\r
+\r
+ TimeStamp = 0;\r
+ Key = 0;\r
+ do {\r
+ Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop);\r
+ if (Key != 0) {\r
+ for (Index = 0; mTokenList[Index] != NULL; Index++) {\r
+ if (AsciiStriCmp (mTokenList[Index], Token) == 0) {\r
+ Delta = Start - Stop;\r
+ TimeStamp += Delta;\r
+ Milliseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000), TicksPerSecond, NULL);\r
+ AsciiPrint ("%6a %6ld ms\n", Token, Milliseconds);\r
+ break;\r
+ }\r
+ } \r
+ }\r
+ } while (Key != 0);\r
+\r
+ AsciiPrint ("Total Time = %ld ms\n\n", DivU64x64Remainder (MultU64x32 (TimeStamp, 1000), TicksPerSecond, NULL));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+#define EFI_MEMORY_PORT_IO 0x4000000000000000ULL\r
+\r
+EFI_STATUS\r
+EblDumpGcd (\r
+ IN UINTN Argc,\r
+ IN CHAR8 **Argv\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN NumberOfDescriptors;\r
+ UINTN i;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
+ EFI_GCD_IO_SPACE_DESCRIPTOR *IoSpaceMap;\r
+\r
+ Status = gDS->GetMemorySpaceMap(&NumberOfDescriptors,&MemorySpaceMap);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ AsciiPrint (" Address Range Image Device Attributes\n");\r
+ AsciiPrint ("__________________________________________________________\n");\r
+ for (i=0; i < NumberOfDescriptors; i++) {\r
+ //AsciiPrint ("%016lx - %016lx",MemorySpaceMap[i].BaseAddress,MemorySpaceMap[i].BaseAddress+MemorySpaceMap[i].Length);\r
+ AsciiPrint ("MEM %08lx - %08lx",(UINT64)MemorySpaceMap[i].BaseAddress,MemorySpaceMap[i].BaseAddress+MemorySpaceMap[i].Length-1);\r
+ AsciiPrint (" %08x %08x",MemorySpaceMap[i].ImageHandle,MemorySpaceMap[i].DeviceHandle);\r
+\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_RUNTIME)\r
+ AsciiPrint (" RUNTIME");\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_PORT_IO)\r
+ AsciiPrint (" PORT_IO");\r
+\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_UC)\r
+ AsciiPrint (" MEM_UC");\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_WC)\r
+ AsciiPrint (" MEM_WC");\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_WT)\r
+ AsciiPrint (" MEM_WT");\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_WB)\r
+ AsciiPrint (" MEM_WB");\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_UCE)\r
+ AsciiPrint (" MEM_UCE");\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_WP)\r
+ AsciiPrint (" MEM_WP");\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_RP)\r
+ AsciiPrint (" MEM_RP");\r
+ if (MemorySpaceMap[i].Attributes & EFI_MEMORY_XP)\r
+ AsciiPrint (" MEM_XP");\r
+\r
+ if (MemorySpaceMap[i].GcdMemoryType & EfiGcdMemoryTypeNonExistent)\r
+ AsciiPrint (" TYPE_NONEXISTENT");\r
+ if (MemorySpaceMap[i].GcdMemoryType & EfiGcdMemoryTypeReserved)\r
+ AsciiPrint (" TYPE_RESERVED");\r
+ if (MemorySpaceMap[i].GcdMemoryType & EfiGcdMemoryTypeSystemMemory)\r
+ AsciiPrint (" TYPE_SYSMEM");\r
+ if (MemorySpaceMap[i].GcdMemoryType & EfiGcdMemoryTypeMemoryMappedIo)\r
+ AsciiPrint (" TYPE_MEMMAP");\r
+\r
+ AsciiPrint ("\n");\r
+ }\r
+\r
+ Status = gDS->GetIoSpaceMap(&NumberOfDescriptors,&IoSpaceMap);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ for (i=0; i < NumberOfDescriptors; i++) {\r
+ AsciiPrint ("IO %08lx - %08lx",IoSpaceMap[i].BaseAddress,IoSpaceMap[i].BaseAddress+IoSpaceMap[i].Length);\r
+ AsciiPrint ("\t%08x %08x",IoSpaceMap[i].ImageHandle,IoSpaceMap[i].DeviceHandle);\r
+\r
+ if (IoSpaceMap[i].GcdIoType & EfiGcdMemoryTypeNonExistent)\r
+ AsciiPrint (" TYPE_NONEXISTENT");\r
+ if (IoSpaceMap[i].GcdIoType & EfiGcdMemoryTypeReserved)\r
+ AsciiPrint (" TYPE_RESERVED");\r
+ if (IoSpaceMap[i].GcdIoType & EfiGcdIoTypeIo)\r
+ AsciiPrint (" TYPE_IO");\r
+\r
+ AsciiPrint ("\n");\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED const EBL_COMMAND_TABLE mLibCmdTemplate[] =\r
+{\r
+ {\r
+ "disasm address [count]",\r
+ " disassemble count instructions",\r
+ NULL,\r
+ EblDisassembler\r
+ },\r
+ {\r
+ "performance",\r
+ " Display boot performance info",\r
+ NULL,\r
+ EblPerformance\r
+ },\r
+ {\r
+ "symboltable [\"format string\"] [PECOFF]",\r
+ " show symbol table commands for debugger",\r
+ NULL,\r
+ EblSymbolTable\r
+ },\r
+ {\r
+ "dumpgcd",\r
+ " dump Global Coherency Domain",\r
+ NULL,\r
+ EblDumpGcd\r
+ },\r
+ {\r
+ "dumpmmu",\r
+ " dump MMU Table",\r
+ NULL,\r
+ EblDumpMmu\r
+ }\r
+};\r
+\r
+\r
+VOID\r
+EblInitializeExternalCmd (\r
+ VOID\r
+ )\r
+{\r
+ EblAddCommands (mLibCmdTemplate, sizeof (mLibCmdTemplate)/sizeof (EBL_COMMAND_TABLE));\r
+ return;\r
+}\r
--- /dev/null
+#/** @file\r
+# \r
+# Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmVeEblCmdLib\r
+ FILE_GUID = 6085e1ca-0d2d-4ba4-9872-c59b36ffd6ad\r
+ MODULE_TYPE = UEFI_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = EblCmdLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER \r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+ EblCmdLib.c\r
+ EblCmdMmu.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ ArmLib\r
+ DebugLib\r
+ ArmDisassemblerLib\r
+ PerformanceLib\r
+ TimerLib\r
+ \r
+[Protocols]\r
+ gEfiDebugSupportProtocolGuid\r
+ gEfiLoadedImageProtocolGuid\r
+ \r
+[Guids]\r
+ gEfiDebugImageInfoTableGuid\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Chipset/ArmV7.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/EblCmdLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#define GET_TT_ATTRIBUTES(TTEntry) ((TTEntry) & ~(TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK))\r
+#define GET_TT_PAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFF)\r
+#define GET_TT_LARGEPAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFFF)\r
+\r
+// Section\r
+#define TT_DESCRIPTOR_SECTION_STRONGLY_ORDER (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED)\r
+\r
+// Small Page\r
+#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)\r
+#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
+#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)\r
+#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)\r
+\r
+#define TT_DESCRIPTOR_PAGE_STRONGLY_ORDER (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED)\r
+\r
+// Large Page\r
+#define TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
+#define TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
+#define TT_DESCRIPTOR_LARGEPAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)\r
+#define TT_DESCRIPTOR_LARGEPAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
+\r
+\r
+typedef enum { Level0, Level1,Level2 } MMU_LEVEL;\r
+\r
+typedef struct {\r
+ MMU_LEVEL Level;\r
+ UINT32 Value;\r
+ UINT32 Index;\r
+ UINT32* Table;\r
+} MMU_ENTRY;\r
+\r
+MMU_ENTRY MmuEntryCreate(MMU_LEVEL Level,UINT32* Table,UINT32 Index) {\r
+ MMU_ENTRY Entry;\r
+ Entry.Level = Level;\r
+ Entry.Value = Table[Index];\r
+ Entry.Table = Table;\r
+ Entry.Index = Index;\r
+ return Entry;\r
+}\r
+\r
+UINT32 MmuEntryIsValidAddress(MMU_LEVEL Level, UINT32 Entry) {\r
+ if (Level == Level0) {\r
+ return 0;\r
+ } else if (Level == Level1) {\r
+ if ((Entry & 0x3) == 0) { // Ignored\r
+ return 0;\r
+ } else if ((Entry & 0x3) == 2) { // Section Type\r
+ return 1;\r
+ } else { // Page Type\r
+ return 0;\r
+ }\r
+ } else if (Level == Level2){\r
+ if ((Entry & 0x3) == 0) { // Ignored\r
+ return 0;\r
+ } else { // Page Type\r
+ return 1;\r
+ }\r
+ } else {\r
+ DEBUG((EFI_D_ERROR,"MmuEntryIsValidAddress: Level:%d Entry:0x%X\n",(UINT32)Level,(UINT32)Entry));\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+}\r
+\r
+UINT32 MmuEntryGetAddress(MMU_ENTRY Entry) {\r
+ if (Entry.Level == Level1) {\r
+ if ((Entry.Value & 0x3) == 0) {\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 2) { // Section Type\r
+ return Entry.Value & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;\r
+ } else if ((Entry.Value & 0x3) == 1) { // Level2 Table\r
+ MMU_ENTRY Entry = MmuEntryCreate(Level2,(UINT32*)(Entry.Value & 0xFFFFC000),0);\r
+ return MmuEntryGetAddress(Entry);\r
+ } else { // Page Type\r
+ return 0;\r
+ }\r
+ } else if (Entry.Level == Level2) {\r
+ if ((Entry.Value & 0x3) == 0) { // Ignored\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 1) { // Large Page\r
+ return Entry.Value & 0xFFFF0000;\r
+ } else if ((Entry.Value & 0x2) == 2) { // Small Page\r
+ return Entry.Value & 0xFFFFF000;\r
+ } else {\r
+ return 0;\r
+ }\r
+ } else {\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+}\r
+\r
+UINT32 MmuEntryGetSize(MMU_ENTRY Entry) {\r
+ if (Entry.Level == Level1) {\r
+ if ((Entry.Value & 0x3) == 0) {\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 2) {\r
+ if (Entry.Value & (1 << 18))\r
+ return 16*SIZE_1MB;\r
+ else\r
+ return SIZE_1MB;\r
+ } else if ((Entry.Value & 0x3) == 1) { // Level2 Table split 1MB section\r
+ return SIZE_1MB;\r
+ } else {\r
+ DEBUG((EFI_D_ERROR, "MmuEntryGetSize: Value:0x%X",Entry.Value));\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+ } else if (Entry.Level == Level2) {\r
+ if ((Entry.Value & 0x3) == 0) { // Ignored\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 1) { // Large Page\r
+ return SIZE_64KB;\r
+ } else if ((Entry.Value & 0x2) == 2) { // Small Page\r
+ return SIZE_4KB;\r
+ } else {\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+ } else {\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+}\r
+\r
+CONST CHAR8* MmuEntryGetAttributesName(MMU_ENTRY Entry) {\r
+ if (Entry.Level == Level1) {\r
+ if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_WRITE_BACK(0))\r
+ return "TT_DESCRIPTOR_SECTION_WRITE_BACK";\r
+ else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0))\r
+ return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH";\r
+ else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_DEVICE(0))\r
+ return "TT_DESCRIPTOR_SECTION_DEVICE";\r
+ else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_UNCACHED(0))\r
+ return "TT_DESCRIPTOR_SECTION_UNCACHED";\r
+ else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER)\r
+ return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED";\r
+ else {\r
+ return "SectionUnknown";\r
+ }\r
+ } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page\r
+ if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK)\r
+ return "TT_DESCRIPTOR_PAGE_WRITE_BACK";\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)\r
+ return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH";\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE)\r
+ return "TT_DESCRIPTOR_PAGE_DEVICE";\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)\r
+ return "TT_DESCRIPTOR_PAGE_UNCACHED";\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)\r
+ return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED";\r
+ else {\r
+ return "PageUnknown";\r
+ }\r
+ } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page\r
+ if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)\r
+ return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK";\r
+ else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)\r
+ return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH";\r
+ else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)\r
+ return "TT_DESCRIPTOR_LARGEPAGE_DEVICE";\r
+ else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)\r
+ return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED";\r
+ else {\r
+ return "LargePageUnknown";\r
+ }\r
+ } else {\r
+ ASSERT(0);\r
+ return "";\r
+ }\r
+}\r
+\r
+UINT32 MmuEntryGetAttributes(MMU_ENTRY Entry) {\r
+ if (Entry.Level == Level1) {\r
+ if ((Entry.Value & 0x3) == 0) {\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 2) {\r
+ return GET_TT_ATTRIBUTES(Entry.Value);\r
+ } else {\r
+ return 0;\r
+ }\r
+ } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page\r
+ if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK)\r
+ return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)\r
+ return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE)\r
+ return TT_DESCRIPTOR_SECTION_DEVICE(0);\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)\r
+ return TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)\r
+ return TT_DESCRIPTOR_SECTION_STRONGLY_ORDER;\r
+ else {\r
+ return 0;\r
+ }\r
+ } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page\r
+ if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)\r
+ return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+ else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)\r
+ return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
+ else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)\r
+ return TT_DESCRIPTOR_SECTION_DEVICE(0);\r
+ else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)\r
+ return TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
+ else {\r
+ return 0;\r
+ }\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+\r
+MMU_ENTRY DumpMmuLevel(MMU_LEVEL Level, UINT32* Table, MMU_ENTRY PreviousEntry) {\r
+ UINT32 Index = 0, Count;\r
+ MMU_ENTRY LastEntry, Entry;\r
+\r
+ ASSERT((Level == Level1) || (Level == Level2));\r
+\r
+ if (Level == Level1) Count = 4096;\r
+ else Count = 256;\r
+\r
+ // At Level1, we will get into this function because PreviousEntry is not valid\r
+ if (!MmuEntryIsValidAddress((MMU_LEVEL)(Level-1),PreviousEntry.Value)) {\r
+ // Find the first valid address\r
+ for (; (Index < Count) && (!MmuEntryIsValidAddress(Level,Table[Index])); Index++);\r
+\r
+ LastEntry = MmuEntryCreate(Level,Table,Index);\r
+ Index++;\r
+ } else {\r
+ LastEntry = PreviousEntry;\r
+ }\r
+\r
+ for (; Index < Count; Index++) {\r
+ Entry = MmuEntryCreate(Level,Table,Index);\r
+ if ((Level == Level1) && ((Entry.Value & 0x3) == 1)) { // We have got a Level2 table redirection\r
+ LastEntry = DumpMmuLevel(Level2,(UINT32*)(Entry.Value & 0xFFFFFC00),LastEntry);\r
+ } else if (!MmuEntryIsValidAddress(Level,Table[Index])) {\r
+ if (MmuEntryIsValidAddress(LastEntry.Level,LastEntry.Value)) {\r
+ AsciiPrint("0x%08X-0x%08X\t%a\n",\r
+ MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,\r
+ MmuEntryGetAttributesName(LastEntry));\r
+ }\r
+ LastEntry = Entry;\r
+ } else {\r
+ if (MmuEntryGetAttributes(LastEntry) != MmuEntryGetAttributes(Entry)) {\r
+ if (MmuEntryIsValidAddress(Level,LastEntry.Value)) {\r
+ AsciiPrint("0x%08X-0x%08X\t%a\n",\r
+ MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,\r
+ MmuEntryGetAttributesName(LastEntry));\r
+ }\r
+ LastEntry = Entry;\r
+ } else {\r
+ ASSERT(LastEntry.Value != 0);\r
+ }\r
+ }\r
+ PreviousEntry = Entry;\r
+ }\r
+\r
+ if ((Level == Level1) && (LastEntry.Index != Index) && MmuEntryIsValidAddress(Level,LastEntry.Value)) {\r
+ AsciiPrint("0x%08X-0x%08X\t%a\n",\r
+ MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,\r
+ MmuEntryGetAttributesName(LastEntry));\r
+ }\r
+\r
+ return LastEntry;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EblDumpMmu (\r
+ IN UINTN Argc,\r
+ IN CHAR8 **Argv\r
+ )\r
+{\r
+ UINT32 *TTEntry;\r
+ MMU_ENTRY NoEntry;\r
+\r
+ TTEntry = ArmGetTTBR0BaseAddress();\r
+\r
+ AsciiPrint ("\nTranslation Table:0x%X\n",TTEntry);\r
+ AsciiPrint ("Address Range\t\tAttributes\n");\r
+ AsciiPrint ("____________________________________________________\n");\r
+ \r
+ NoEntry.Level = (MMU_LEVEL)200;\r
+ DumpMmuLevel(Level1,TTEntry,NoEntry);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file
+ Serial I/O Port library functions with no library constructor/destructor
+
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Include/Uefi.h>
+#include <Library/SerialPortLib.h>
+#include <Library/IoLib.h>
+#include <Drivers/PL011Uart.h>
+#include <ArmPlatform.h>
+
+/*
+
+ Programmed hardware of Serial port.
+
+ @return Always return EFI_UNSUPPORTED.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ if (PL011_CONSOLE_UART_SPEED == 115200) {
+ // Initialize baud rate generator
+ MmioWrite32 (PL011_CONSOLE_UART_BASE + UARTIBRD, UART_115200_IDIV);
+ MmioWrite32 (PL011_CONSOLE_UART_BASE + UARTFBRD, UART_115200_FDIV);
+ } else if (PL011_CONSOLE_UART_SPEED == 38400) {
+ // Initialize baud rate generator
+ MmioWrite32 (PL011_CONSOLE_UART_BASE + UARTIBRD, UART_38400_IDIV);
+ MmioWrite32 (PL011_CONSOLE_UART_BASE + UARTFBRD, UART_38400_FDIV);
+ } else if (PL011_CONSOLE_UART_SPEED == 19200) {
+ // Initialize baud rate generator
+ MmioWrite32 (PL011_CONSOLE_UART_BASE + UARTIBRD, UART_19200_IDIV);
+ MmioWrite32 (PL011_CONSOLE_UART_BASE + UARTFBRD, UART_19200_FDIV);
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // No parity, 1 stop, no fifo, 8 data bits
+ MmioWrite32 (PL011_CONSOLE_UART_BASE + UARTLCR_H, 0x60);
+
+ // Clear any pending errors
+ MmioWrite32 (PL011_CONSOLE_UART_BASE + UARTECR, 0);
+
+ // enable tx, rx, and uart overall
+ MmioWrite32 (PL011_CONSOLE_UART_BASE + UARTCR, 0x301);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write data to serial device.
+
+ @param Buffer Point of data buffer which need to be writed.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Write data failed.
+ @retval !0 Actual number of bytes writed to serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN Count;
+
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
+ while ((MmioRead32 (PL011_CONSOLE_UART_BASE + UARTFR) & UART_TX_EMPTY_FLAG_MASK) == 0);
+ MmioWrite8 (PL011_CONSOLE_UART_BASE + UARTDR, *Buffer);
+ }
+
+ return NumberOfBytes;
+}
+
+/**
+ Read data from serial device and save the datas in buffer.
+
+ @param Buffer Point of data buffer which need to be writed.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Read data failed.
+ @retval !0 Aactual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN Count;
+
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
+ while ((MmioRead32 (PL011_CONSOLE_UART_BASE + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);
+ *Buffer = MmioRead8 (PL011_CONSOLE_UART_BASE + UARTDR);
+ }
+
+ return NumberOfBytes;
+}
+
+/**
+ Check to see if any data is avaiable to be read from the debug device.
+
+ @retval EFI_SUCCESS At least one byte of data is avaiable to be read
+ @retval EFI_NOT_READY No data is avaiable to be read
+ @retval EFI_DEVICE_ERROR The serial device is not functioning properly
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ return ((MmioRead32 (PL011_CONSOLE_UART_BASE + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
+}
--- /dev/null
+#/** @file
+#
+# Component discription file for NorFlashDxe module
+#
+# Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PL011SerialPortLib
+ FILE_GUID = 8ecefc8f-a2c4-4091-b80f-20f7aeb0567f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+[Sources.common]
+ PL011SerialPortLib.c
+
+[LibraryClasses]
+ IoLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
--- /dev/null
+/** @file\r
+ Implement EFI RealTimeClock runtime services via RTC Lib.\r
+ \r
+ Currently this driver does not support runtime virtual calling.\r
+\r
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+ \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/RealTimeClockLib.h>\r
+\r
+\r
+/**\r
+ Returns the current time and date information, and the time-keeping capabilities\r
+ of the hardware platform.\r
+\r
+ @param Time A pointer to storage to receive a snapshot of the current time.\r
+ @param Capabilities An optional pointer to a buffer to receive the real time clock\r
+ device's capabilities.\r
+\r
+ @retval EFI_SUCCESS The operation completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Time is NULL.\r
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibGetTime (\r
+ OUT EFI_TIME *Time,\r
+ OUT EFI_TIME_CAPABILITIES *Capabilities\r
+ )\r
+{\r
+ //\r
+ // Fill in Time and Capabilities via data from you RTC\r
+ //\r
+ return EFI_DEVICE_ERROR;\r
+}\r
+\r
+\r
+/**\r
+ Sets the current local time and date information.\r
+\r
+ @param Time A pointer to the current time.\r
+\r
+ @retval EFI_SUCCESS The operation completed successfully.\r
+ @retval EFI_INVALID_PARAMETER A time field is out of range.\r
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibSetTime (\r
+ IN EFI_TIME *Time\r
+ )\r
+{\r
+ //\r
+ // Use Time, to set the time in your RTC hardware\r
+ //\r
+ return EFI_DEVICE_ERROR;\r
+}\r
+\r
+\r
+/**\r
+ Returns the current wakeup alarm clock setting.\r
+\r
+ @param Enabled Indicates if the alarm is currently enabled or disabled.\r
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.\r
+ @param Time The current alarm setting.\r
+\r
+ @retval EFI_SUCCESS The alarm settings were returned.\r
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.\r
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibGetWakeupTime (\r
+ OUT BOOLEAN *Enabled,\r
+ OUT BOOLEAN *Pending,\r
+ OUT EFI_TIME *Time\r
+ )\r
+{\r
+ // Not a required feature\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+ Sets the system wakeup alarm clock time.\r
+\r
+ @param Enabled Enable or disable the wakeup alarm.\r
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.\r
+\r
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If\r
+ Enable is FALSE, then the wakeup alarm was disabled.\r
+ @retval EFI_INVALID_PARAMETER A time field is out of range.\r
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.\r
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibSetWakeupTime (\r
+ IN BOOLEAN Enabled,\r
+ OUT EFI_TIME *Time\r
+ )\r
+{\r
+ // Not a required feature\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+\r
+/**\r
+ This is the declaration of an EFI image entry point. This can be the entry point to an application\r
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.\r
+\r
+ @param ImageHandle Handle that identifies the loaded image.\r
+ @param SystemTable System Table for this image.\r
+\r
+ @retval EFI_SUCCESS The operation completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibRtcInitialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ //\r
+ // Do some initialization if reqruied to turn on the RTC\r
+ //\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Fixup internal data so that EFI can be call in virtual mode.\r
+ Call the passed in Child Notify event and convert any pointers in\r
+ lib to virtual mode.\r
+\r
+ @param[in] Event The Event that is being processed\r
+ @param[in] Context Event Context\r
+**/\r
+VOID\r
+EFIAPI\r
+LibRtcVirtualNotifyEvent (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ //\r
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.\r
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses \r
+ // to virtual address. After the OS transistions to calling in virtual mode, all future\r
+ // runtime calls will be made in virtual mode.\r
+ //\r
+ return;\r
+}\r
--- /dev/null
+#/** @file\r
+# Memory Status Code Library for UEFI drivers\r
+#\r
+# Lib to provide memory journal status code reporting Routines\r
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL031RealTimeClockLib\r
+ FILE_GUID = 470DFB96-E205-4515-A75E-2E60F853E79D\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = RealTimeClockLib\r
+\r
+[Sources.common]\r
+ PL031RealTimeClockLib.c\r
+\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ DebugLib\r
--- /dev/null
+/** @file\r
+ PEI Services Table Pointer Library.\r
+ \r
+ This library is used for PEIM which does executed from flash device directly but\r
+ executed in memory.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/PeiServicesTablePointerLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+/**\r
+ Caches a pointer PEI Services Table. \r
+ \r
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer \r
+ in a platform specific manner.\r
+ \r
+ If PeiServicesTablePointer is NULL, then ASSERT().\r
+ \r
+ @param PeiServicesTablePointer The address of PeiServices pointer.\r
+**/\r
+VOID\r
+EFIAPI\r
+SetPeiServicesTablePointer (\r
+ IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer\r
+ )\r
+{\r
+ UINTN *PeiPtrLoc;\r
+ ASSERT (PeiServicesTablePointer != NULL);\r
+\r
+ PeiPtrLoc = (UINTN *)(UINTN)PcdGet32(PcdPeiServicePtrAddr);\r
+ *PeiPtrLoc = (UINTN)PeiServicesTablePointer;\r
+}\r
+\r
+/**\r
+ Retrieves the cached value of the PEI Services Table pointer.\r
+\r
+ Returns the cached value of the PEI Services Table pointer in a CPU specific manner \r
+ as specified in the CPU binding section of the Platform Initialization Pre-EFI \r
+ Initialization Core Interface Specification.\r
+ \r
+ If the cached PEI Services Table pointer is NULL, then ASSERT().\r
+\r
+ @return The pointer to PeiServices.\r
+\r
+**/\r
+CONST EFI_PEI_SERVICES **\r
+EFIAPI\r
+GetPeiServicesTablePointer (\r
+ VOID\r
+ )\r
+{\r
+ UINTN *PeiPtrLoc;\r
+\r
+ PeiPtrLoc = (UINTN *)(UINTN)PcdGet32(PcdPeiServicePtrAddr);\r
+ return (CONST EFI_PEI_SERVICES **)*PeiPtrLoc;\r
+}\r
+\r
+\r
--- /dev/null
+## @file\r
+# Instance of PEI Services Table Pointer Library using global variable for the table pointer.\r
+#\r
+# PEI Services Table Pointer Library implementation that retrieves a pointer to the\r
+# PEI Services Table from a global variable. Not available to modules that execute from\r
+# read-only memory.\r
+#\r
+# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PeiServicesTablePointerLib\r
+ FILE_GUID = 1c747f6b-0a58-49ae-8ea3-0327a4fa10e3\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE SEC\r
+\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+#\r
+\r
+[Sources]\r
+ PeiServicesTablePointer.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ \r
+[Pcd]\r
+ gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr\r
--- /dev/null
+/** @file
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+
+#include <Library/BaseLib.h>
+#include <Library/TimerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Drivers/SP804Timer.h>
+#include <ArmPlatform.h>
+
+// Setup SP810's Timer2 for managing delay functions. And Timer3 for Performance counter
+// Note: ArmVE's Timer0 and Timer1 are used by TimerDxe.
+RETURN_STATUS
+EFIAPI
+TimerConstructor (
+ VOID
+ )
+{
+ // Check if Timer 2 is already initialized
+ if (MmioRead32(SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ return RETURN_SUCCESS;
+ } else {
+ // configure SP810 to use 1MHz clock and disable
+ MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
+
+ // configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled
+ MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
+
+ // preload the timer count register
+ MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1);
+
+ // enable the timer
+ MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
+ }
+
+ // Check if Timer 3 is already initialized
+ if (MmioRead32(SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ return RETURN_SUCCESS;
+ } else {
+ // configure SP810 to use 1MHz clock and disable
+ MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
+
+ // configure timer 3 for free running operation, 32 bits, no prescaler, interrupt disabled
+ MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
+
+ // enable the timer
+ MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param MicroSeconds The minimum number of microseconds to delay.
+
+ @return The value of MicroSeconds inputted.
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+ // load the timer count register
+ MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, MicroSeconds);
+
+ while (MmioRead32 (SP804_TIMER2_BASE + SP804_TIMER_CURRENT_REG) > 0) {
+ ;
+ }
+
+ return MicroSeconds;
+}
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return The value of NanoSeconds inputted.
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+ UINT32 MicroSeconds;
+
+ // Round up to 1us Tick Number
+ MicroSeconds = (UINT32)NanoSeconds / 1000;
+ MicroSeconds += ((UINT32)NanoSeconds % 1000) == 0 ? 0 : 1;
+
+ // load the timer count register
+ MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, MicroSeconds);
+
+ while (MmioRead32 (SP804_TIMER2_BASE + SP804_TIMER_CURRENT_REG) > 0) {
+ ;
+ }
+
+ return NanoSeconds;
+}
+
+/**
+ Retrieves the current value of a 64-bit free running performance counter.
+
+ The counter can either count up by 1 or count down by 1. If the physical
+ performance counter counts by a larger increment, then the counter values
+ must be translated. The properties of the counter can be retrieved from
+ GetPerformanceCounterProperties().
+
+ @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ )
+{
+ // Free running 64-bit/32-bit counter is needed here.
+ // Don't think we need this to boot, just to do performance profile
+ // ASSERT (FALSE);
+ UINT32 val = MmioRead32 (SP804_TIMER3_BASE + SP804_TIMER_CURRENT_REG);
+ ASSERT(val > 0);
+
+ return (UINT64)val;
+}
+
+
+/**
+ Retrieves the 64-bit frequency in Hz and the range of performance counter
+ values.
+
+ If StartValue is not NULL, then the value that the performance counter starts
+ with immediately after is it rolls over is returned in StartValue. If
+ EndValue is not NULL, then the value that the performance counter end with
+ immediately before it rolls over is returned in EndValue. The 64-bit
+ frequency of the performance counter in Hz is always returned. If StartValue
+ is less than EndValue, then the performance counter counts up. If StartValue
+ is greater than EndValue, then the performance counter counts down. For
+ example, a 64-bit free running counter that counts up would have a StartValue
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+ @param StartValue The value the performance counter starts with when it
+ rolls over.
+ @param EndValue The value that the performance counter ends with before
+ it rolls over.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
+ )
+{
+ if (StartValue != NULL) {
+ // Timer starts with the reload value
+ *StartValue = (UINT64)0ULL;
+ }
+
+ if (EndValue != NULL) {
+ // Timer counts up to 0xFFFFFFFF
+ *EndValue = 0xFFFFFFFF;
+ }
+
+ return 1000000;
+}
--- /dev/null
+#/** @file
+# Timer library implementation
+#
+#
+# Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SP804TimerLib
+ FILE_GUID = 09cefa99-0d07-487f-a651-fb44f094b1c7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib
+
+ CONSTRUCTOR = TimerConstructor
+
+[Sources.common]
+ SP804TimerLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ BaseLib
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+//\r
+// The package level header files this module uses\r
+//\r
+#include <PiPei.h>\r
+//\r
+// The protocols, PPI and GUID defintions for this module\r
+//\r
+#include <Ppi/MasterBootMode.h>\r
+#include <Ppi/BootInRecoveryMode.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+//\r
+// The Library classes this module consumes\r
+//\r
+#include <Library/DebugLib.h>\r
+#include <Library/PeimEntryPoint.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+\r
+//\r
+// Module globals\r
+//\r
+\r
+VOID\r
+InitMmu (\r
+ VOID\r
+ )\r
+{\r
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;\r
+ VOID *TranslationTableBase;\r
+ UINTN TranslationTableSize;\r
+\r
+ // Get Virtual Memory Map from the Platform Library\r
+ ArmPlatformGetVirtualMemoryMap(&MemoryTable);\r
+\r
+ //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in\r
+ // DRAM (even at the top of DRAM as it is the first permanent memory allocation)\r
+ ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
+}\r
+\r
+// May want to put this into a library so you only need the PCD setings if you are using the feature?\r
+VOID\r
+BuildMemoryTypeInformationHob (\r
+ VOID\r
+ )\r
+{\r
+ EFI_MEMORY_TYPE_INFORMATION Info[10];\r
+\r
+ Info[0].Type = EfiACPIReclaimMemory;\r
+ Info[0].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiACPIReclaimMemory);\r
+ Info[1].Type = EfiACPIMemoryNVS;\r
+ Info[1].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiACPIMemoryNVS);\r
+ Info[2].Type = EfiReservedMemoryType;\r
+ Info[2].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiReservedMemoryType);\r
+ Info[3].Type = EfiRuntimeServicesData;\r
+ Info[3].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiRuntimeServicesData);\r
+ Info[4].Type = EfiRuntimeServicesCode;\r
+ Info[4].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiRuntimeServicesCode);\r
+ Info[5].Type = EfiBootServicesCode;\r
+ Info[5].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiBootServicesCode);\r
+ Info[6].Type = EfiBootServicesData;\r
+ Info[6].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiBootServicesData);\r
+ Info[7].Type = EfiLoaderCode;\r
+ Info[7].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiLoaderCode);\r
+ Info[8].Type = EfiLoaderData;\r
+ Info[8].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiLoaderData);\r
+ \r
+ // Terminator for the list\r
+ Info[9].Type = EfiMaxMemoryType;\r
+ Info[9].NumberOfPages = 0;\r
+\r
+\r
+ BuildGuidDataHob (&gEfiMemoryTypeInformationGuid, &Info, sizeof (Info));\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeMemory (\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ \r
+\r
+Arguments:\r
+\r
+ FileHandle - Handle of the file being invoked.\r
+ PeiServices - Describes the list of possible PEI Services.\r
+ \r
+Returns:\r
+\r
+ Status - EFI_SUCCESS if the boot mode could be set\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR* EfiMemoryMap;\r
+ UINTN PeiMemoryBase;\r
+ UINTN PeiMemorySize;\r
+ UINTN Index;\r
+\r
+ DEBUG ((EFI_D_ERROR, "Memory Init PEIM Loaded\n"));\r
+\r
+ // If it is not a standalone version, then we need to initialize the System Memory\r
+ // In case of a standalone version, the DRAM is already initialized\r
+ if (FeaturePcdGet(PcdStandalone)) {\r
+ // Initialize the System Memory controller (DRAM)\r
+ ArmPlatformInitializeSystemMemory();\r
+ }\r
+\r
+ // Install the Memory to PEI\r
+ ArmPlatformGetPeiMemory (&PeiMemoryBase,&PeiMemorySize);\r
+ Status = PeiServicesInstallPeiMemory (PeiMemoryBase,PeiMemorySize);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Now, the permanent memory has been installed, we can call AllocatePages()\r
+ //\r
+\r
+ ArmPlatformGetEfiMemoryMap (&EfiMemoryMap);\r
+\r
+ // Install the EFI Memory Map\r
+ for (Index = 0; EfiMemoryMap[Index].ResourceAttribute != 0; Index++) {\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ EfiMemoryMap[Index].ResourceAttribute,\r
+ EfiMemoryMap[Index].PhysicalStart,\r
+ EfiMemoryMap[Index].NumberOfBytes\r
+ );\r
+ }\r
+\r
+ // Build Memory Allocation Hob\r
+ InitMmu ();\r
+\r
+ if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {\r
+ // Optional feature that helps prevent EFI memory map fragmentation. \r
+ BuildMemoryTypeInformationHob ();\r
+ }\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+#/** @file\r
+# \r
+# Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = MemoryInit\r
+ FILE_GUID = c61ef796-b50d-4f98-9f78-4f6f79d800d5\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = InitializeMemory\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ MemoryInit.c\r
+\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ \r
+[LibraryClasses]\r
+ PeimEntryPoint\r
+ DebugLib\r
+ HobLib\r
+ ArmLib\r
+ ArmPlatformLib\r
+\r
+[Guids]\r
+ gEfiMemoryTypeInformationGuid\r
+\r
+[Ppis]\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
+[FixedPcd]\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData\r
+ \r
+[depex]\r
+ TRUE\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+//\r
+// The package level header files this module uses\r
+//\r
+#include <PiPei.h>\r
+//\r
+// The protocols, PPI and GUID defintions for this module\r
+//\r
+#include <Ppi/MasterBootMode.h>\r
+#include <Ppi/BootInRecoveryMode.h>\r
+//\r
+// The Library classes this module consumes\r
+//\r
+#include <Library/DebugLib.h>\r
+#include <Library/PeimEntryPoint.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/HobLib.h>\r
+\r
+\r
+//\r
+// Module globals\r
+//\r
+EFI_PEI_PPI_DESCRIPTOR mPpiListBootMode = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiMasterBootModePpiGuid,\r
+ NULL\r
+};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiBootInRecoveryModePpiGuid,\r
+ NULL\r
+};\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+InitializePlatformPeim (\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ \r
+\r
+Arguments:\r
+\r
+ FileHandle - Handle of the file being invoked.\r
+ PeiServices - Describes the list of possible PEI Services.\r
+ \r
+Returns:\r
+\r
+ Status - EFI_SUCCESS if the boot mode could be set\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN BootMode;\r
+\r
+ DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
+\r
+ BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
+ \r
+ BuildFvHob (FixedPcdGet32(PcdFlashFvMainBase), FixedPcdGet32(PcdFlashFvMainSize));\r
+ \r
+ //\r
+ // Let's assume things are OK if not told otherwise\r
+ // Should we read an environment variable in order to easily change this?\r
+ //\r
+ BootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+\r
+ Status = (**PeiServices).SetBootMode (PeiServices, (UINT8) BootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = (**PeiServices).InstallPpi (PeiServices, &mPpiListBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
+ Status = (**PeiServices).InstallPpi (PeiServices, &mPpiListRecoveryBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+#/** @file\r
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformPei\r
+ FILE_GUID = 2ad0fc59-2314-4bf3-8633-13fa22a624a0\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = InitializePlatformPeim\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ PlatformPei.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+\r
+[LibraryClasses]\r
+ PeimEntryPoint\r
+ DebugLib\r
+ HobLib\r
+\r
+[Ppis]\r
+ gEfiPeiMasterBootModePpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED\r
+\r
+[FixedPcd]\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress #The base address of the FLASH Device.\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize #The size in bytes of the FLASH Device\r
+ gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase\r
+ gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize\r
+ \r
+[depex]\r
+ TRUE\r
+ \r
--- /dev/null
+//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <AutoGen.h>
+
+#start of the code section
+.text
+.align 5\r
+\r
+# IMPORT
+GCC_ASM_IMPORT(PeiCommonExceptionEntry)
+
+# EXPORT
+GCC_ASM_EXPORT(PeiVectorTable)
+\r
+//============================================================
+//Default Exception Handlers
+//============================================================
+
+//FIXME: One of the EDK2 tool is broken. It does not look to respect the alignment. Even, if we specify 32-byte alignment for this file.
+Dummy1: .word 0\r
+Dummy2: .word 0\r
+
+ASM_PFX(PeiVectorTable):
+ b _DefaultResetHandler
+ b _DefaultUndefined
+ b _DefaultSWI
+ b _DefaultPrefetchAbort
+ b _DefaultDataAbort
+ b _DefaultReserved
+ b _DefaultIrq
+ b _DefaultFiq
+
+//
+// Default Exception handlers: There is no plan to return from any of these exceptions.
+// No context saving at all.
+//
+_DefaultResetHandler:
+ mov r1, lr
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #0
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultUndefined:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #1
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultSWI:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #2
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultPrefetchAbort:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #3
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultDataAbort:
+ sub r1, LR, #8
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #4
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultReserved:
+ mov r1, lr
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #5
+ blx PeiCommonExceptionEntry
+
+_DefaultIrq:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #6
+ blx PeiCommonExceptionEntry
+
+_DefaultFiq:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #7
+ blx PeiCommonExceptionEntry
+\r
+.end\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+ IMPORT PeiCommonExceptionEntry\r
+ EXPORT PeiVectorTable\r
+ \r
+ PRESERVE8\r
+ AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=5\r
+\r
+//============================================================
+//Default Exception Handlers
+//============================================================
+
+//FIXME: One of the EDK2 tool is broken. It does not look to respect the alignment. Even, if we specify 32-byte alignment for this file.
+Dummy1 DCD 0\r
+Dummy2 DCD 0\r
+
+PeiVectorTable
+ b _DefaultResetHandler
+ b _DefaultUndefined
+ b _DefaultSWI
+ b _DefaultPrefetchAbort
+ b _DefaultDataAbort
+ b _DefaultReserved
+ b _DefaultIrq
+ b _DefaultFiq
+
+//\r
+// Default Exception handlers: There is no plan to return from any of these exceptions.\r
+// No context saving at all.
+//\r
+_DefaultResetHandler
+ mov r1, lr\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #0
+ blx PeiCommonExceptionEntry
+
+_DefaultUndefined
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #1
+ blx PeiCommonExceptionEntry
+
+_DefaultSWI
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #2
+ blx PeiCommonExceptionEntry
+
+_DefaultPrefetchAbort
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #3
+ blx PeiCommonExceptionEntry
+
+_DefaultDataAbort
+ sub r1, LR, #8\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #4
+ blx PeiCommonExceptionEntry
+
+_DefaultReserved
+ mov r1, lr\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #5
+ blx PeiCommonExceptionEntry
+
+_DefaultIrq
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #6
+ blx PeiCommonExceptionEntry
+
+_DefaultFiq
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #7
+ blx PeiCommonExceptionEntry
+\r
+ END\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/ArmMPCoreMailBoxLib.h>\r
+#include <Chipset/ArmV7.h>\r
+#include <Drivers/PL390Gic.h>\r
+\r
+extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
+\r
+/*\r
+ * This is the main function for secondary cores. They loop around until a non Null value is written to\r
+ * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r
+ * Note:The secondary cores, while executing secondary_main, assumes that:\r
+ * : SGI 0 is configured as Non-secure interrupt\r
+ * : Priority Mask is configured to allow SGI 0\r
+ * : Interrupt Distributor and CPU interfaces are enabled\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+secondary_main(IN UINTN CoreId)\r
+{\r
+ //Function pointer to Secondary Core entry point\r
+ VOID (*secondary_start)(VOID);\r
+ UINTN secondary_entry_addr=0;\r
+\r
+ //Clear Secondary cores MailBox\r
+ ArmClearMPCoreMailbox();\r
+\r
+ while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
+ ArmCallWFI();\r
+ //Acknowledge the interrupt and send End of Interrupt signal.\r
+ PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+ }\r
+\r
+ secondary_start = (VOID (*)())secondary_entry_addr;\r
+\r
+ //Jump to secondary core entry point.\r
+ secondary_start();\r
+\r
+ //the secondaries shouldn't reach here\r
+ ASSERT(FALSE);\r
+}\r
+\r
+VOID primary_main (\r
+ IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
+ )\r
+{\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+\r
+ //Enable the GIC Distributor\r
+ PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+\r
+ // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
+ if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
+ // Sending SGI to all the Secondary CPU interfaces\r
+ PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ }\r
+\r
+ //\r
+ // Bind this information into the SEC hand-off state\r
+ // Note: this must be in sync with the stuff in the asm file\r
+ // Note also: HOBs (pei temp ram) MUST be above stack\r
+ //\r
+ SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdEmbeddedFdBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdEmbeddedFdSize);\r
+ SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
+ SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
+ SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
+ SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+\r
+ // jump to pei core entry point\r
+ (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Chipset/ArmV7.h>\r
+\r
+extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
+\r
+VOID\r
+EFIAPI\r
+secondary_main(IN UINTN CoreId)\r
+{\r
+ ASSERT(FALSE);\r
+}\r
+\r
+VOID primary_main (\r
+ IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
+ )\r
+{\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+\r
+\r
+ //\r
+ // Bind this information into the SEC hand-off state\r
+ // Note: this must be in sync with the stuff in the asm file\r
+ // Note also: HOBs (pei temp ram) MUST be above stack\r
+ //\r
+ SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdEmbeddedFdBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdEmbeddedFdSize);\r
+ SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
+ SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
+ SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
+ SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+\r
+ // jump to pei core entry point\r
+ (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
+}\r
--- /dev/null
+/** @file\r
+* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Ppi/TemporaryRamSupport.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Chipset/ArmV7.h>\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamSupport (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
+ );\r
+\r
+VOID\r
+SecSwitchStack (\r
+ INTN StackDelta\r
+ );\r
+\r
+TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+ &gEfiTemporaryRamSupportPpiGuid,\r
+ &mSecTemporaryRamSupportPpi\r
+ }\r
+};\r
+\r
+// Vector Table for Pei Phase\r
+VOID PeiVectorTable (VOID);\r
+\r
+\r
+VOID\r
+CEntryPoint (\r
+ IN UINTN CoreId,\r
+ IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
+ )\r
+{\r
+ //Clean Data cache\r
+ ArmCleanInvalidateDataCache();\r
+\r
+ //Invalidate instruction cache\r
+ ArmInvalidateInstructionCache();\r
+\r
+ // Enable Instruction & Data caches\r
+ ArmEnableDataCache();\r
+ ArmEnableInstructionCache();\r
+\r
+ //\r
+ // Note: Doesn't have to Enable CPU interface in non-secure world,\r
+ // as Non-secure interface is already enabled in Secure world.\r
+ //\r
+\r
+ // Write VBAR - The Vector table must be 32-byte aligned\r
+ ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);\r
+ ArmWriteVBar((UINT32)PeiVectorTable);\r
+\r
+ //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
+\r
+ //If not primary Jump to Secondary Main\r
+ if(0 == CoreId) {\r
+ //Goto primary Main.\r
+ primary_main(PeiCoreEntryPoint);\r
+ } else {\r
+ secondary_main(CoreId);\r
+ }\r
+\r
+ // PEI Core should always load and never return\r
+ ASSERT (FALSE);\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamSupport (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
+ )\r
+{\r
+ //\r
+ // Migrate the whole temporary memory to permenent memory.\r
+ // \r
+ CopyMem (\r
+ (VOID*)(UINTN)PermanentMemoryBase, \r
+ (VOID*)(UINTN)TemporaryMemoryBase, \r
+ CopySize\r
+ );\r
+\r
+ SecSwitchStack((UINTN)(PermanentMemoryBase - TemporaryMemoryBase));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+VOID PeiCommonExceptionEntry(UINT32 Entry, UINT32 LR) {\r
+ switch (Entry) {\r
+ case 0:\r
+ DEBUG((EFI_D_ERROR,"Reset Exception at 0x%X\n",LR));\r
+ break;\r
+ case 1:\r
+ DEBUG((EFI_D_ERROR,"Undefined Exception at 0x%X\n",LR));\r
+ break;\r
+ case 2:\r
+ DEBUG((EFI_D_ERROR,"SWI Exception at 0x%X\n",LR));\r
+ break;\r
+ case 3:\r
+ DEBUG((EFI_D_ERROR,"PrefetchAbort Exception at 0x%X\n",LR));\r
+ break;\r
+ case 4:\r
+ DEBUG((EFI_D_ERROR,"DataAbort Exception at 0x%X\n",LR));\r
+ break;\r
+ case 5:\r
+ DEBUG((EFI_D_ERROR,"Reserved Exception at 0x%X\n",LR));\r
+ break;\r
+ case 6:\r
+ DEBUG((EFI_D_ERROR,"IRQ Exception at 0x%X\n",LR));\r
+ break;\r
+ case 7:\r
+ DEBUG((EFI_D_ERROR,"FIQ Exception at 0x%X\n",LR));\r
+ break;\r
+ default:\r
+ DEBUG((EFI_D_ERROR,"Unknown Exception at 0x%X\n",LR));\r
+ break;\r
+ }\r
+ while(1);\r
+}\r
--- /dev/null
+//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http:#opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/PcdLib.h>
+#include <AutoGen.h>
+
+#start of the code section
+.text
+.align 3
+
+#global symbols referenced by this module
+GCC_ASM_IMPORT(CEntryPoint)
+
+StartupAddr: .word CEntryPoint
+
+#make _ModuleEntryPoint as global
+GCC_ASM_EXPORT(_ModuleEntryPoint)
+
+
+ASM_PFX(_ModuleEntryPoint):
+ # Identify CPU ID
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, #0xf
+
+_SetupStack:
+ # Setup Stack for the 4 CPU cores
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase) ,r1)
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize) ,r2)
+
+ mov r3,r0 @ r3 = core_id
+ mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
+ add r3,r3,r1 @ r3 = stack_base + offset
+ add r3,r3,r2,LSR #1 @ r3 = stack_offset + (stack_size/2) <-- the top half is for the heap
+ mov sp, r3
+
+ # lr points to area in reset vector block containing PEI core address. lr needs to
+ # be saved from the beginning as the _ModuleEntryPoint could call helper functions
+ # that will overwrite 'lr'
+ LoadConstantToReg (FixedPcdGet32(PcdEmbeddedFdBaseAddress), r2)
+ add r2, r2, #4
+ ldr r1, [r2]
+
+ # move sec startup address into a data register
+ # ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr r2, StartupAddr
+
+ # jump to SEC C code
+ # r0 = core_id
+ # r1 = pei_core_address
+ blx r2
+
+#end of the file
+.end
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ IMPORT CEntryPoint\r
+ EXPORT _ModuleEntryPoint\r
+ \r
+ PRESERVE8\r
+ AREA PrePeiCoreEntryPoint, CODE, READONLY\r
+ \r
+StartupAddr DCD CEntryPoint\r
+\r
+SCC_SYS_SW EQU 0x0004\r
+\r
+_ModuleEntryPoint\r
+ // Identify CPU ID\r
+ mrc p15, 0, r0, c0, c0, 5\r
+ and r0, #0xf\r
+\r
+_SetupStack\r
+ // Setup Stack for the 4 CPU cores\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase) ,r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize) ,r2)\r
+ \r
+ mov r3,r0 // r3 = core_id\r
+ mul r3,r3,r2 // r3 = core_id * stack_size = offset from the stack base\r
+ add r3,r3,r1 // r3 = stack_base + offset\r
+ add r3,r3,r2,LSR #1 // r3 = stack_offset + (stack_size/2) <-- the top half is for the heap\r
+ mov sp, r3\r
+\r
+ // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
+ LoadConstantToReg (FixedPcdGet32(PcdEmbeddedFdBaseAddress), r2)\r
+ add r2, r2, #4\r
+ ldr r1, [r2]\r
+\r
+ // move sec startup address into a data register\r
+ // ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r2, StartupAddr\r
+\r
+ // jump to SEC C code\r
+ // r0 = core_id\r
+ // r1 = pei_core_address\r
+ blx r2\r
+\r
+ END\r
--- /dev/null
+#/** @file\r
+# Pre PeiCore - Hand-off to PEI Core in Normal World\r
+# \r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmPlatformPrePeiCore\r
+ FILE_GUID = 469fc080-aec1-11df-927c-0002a5d5c51b\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+\r
+[Sources.ARM]\r
+ PrePeiCoreEntryPoint.asm | RVCT\r
+ PrePeiCoreEntryPoint.S | GCC\r
+ PrePeiCore.c\r
+ MainMPCore.c\r
+ SwitchStack.asm | RVCT\r
+ SwitchStack.S | GCC\r
+ Exception.asm | RVCT\r
+ Exception.S | GCC\r
+ \r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ DebugLib\r
+ IoLib\r
+ ArmLib\r
+ ArmPlatformLib\r
+ ArmMPCoreMailBoxLib\r
+ PL390GicNonSecLib\r
+\r
+[Ppis]\r
+ gEfiTemporaryRamSupportPpiGuid\r
+\r
+[FeaturePcd]\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+ \r
+[FixedPcd]\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize\r
+ \r
+ gArmTokenSpaceGuid.PcdGicDistributorBase\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
--- /dev/null
+#/** @file\r
+# Pre PeiCore - Hand-off to PEI Core in Normal World\r
+# \r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmPlatformPrePeiCore\r
+ FILE_GUID = 469fc080-aec1-11df-927c-0002a5d5c51b\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+\r
+[Sources.ARM]\r
+ PrePeiCoreEntryPoint.asm | RVCT\r
+ PrePeiCoreEntryPoint.S | GCC\r
+ PrePeiCore.c\r
+ MainUniCore.c\r
+ SwitchStack.asm | RVCT\r
+ SwitchStack.S | GCC\r
+ Exception.asm | RVCT\r
+ Exception.S | GCC\r
+ \r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ DebugLib\r
+ IoLib\r
+ ArmLib\r
+ ArmPlatformLib\r
+\r
+[Ppis]\r
+ gEfiTemporaryRamSupportPpiGuid\r
+\r
+[FeaturePcd]\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+ \r
+[FixedPcd]\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize\r
+ \r
+ gArmTokenSpaceGuid.PcdGicDistributorBase\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
--- /dev/null
+#------------------------------------------------------------------------------ \r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+ \r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(SecSwitchStack)\r
+\r
+\r
+ \r
+#/**\r
+# This allows the caller to switch the stack and return\r
+#\r
+# @param StackDelta Signed amount by which to modify the stack pointer\r
+#\r
+# @return Nothing. Goes to the Entry Point passing in the new parameters\r
+#\r
+#**/\r
+#VOID\r
+#EFIAPI\r
+#SecSwitchStack (\r
+# VOID *StackDelta\r
+# )#\r
+#\r
+ASM_PFX(SecSwitchStack): \r
+ mov R1, R13\r
+ add R1, R0, R1\r
+ mov R13, R1\r
+ bx LR\r
+ \r
+ \r
+ \r
--- /dev/null
+;------------------------------------------------------------------------------ \r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+ \r
+ EXPORT SecSwitchStack\r
+ \r
+ AREA Switch_Stack, CODE, READONLY\r
+ \r
+;/**\r
+; This allows the caller to switch the stack and return\r
+;\r
+; @param StackDelta Signed amount by which to modify the stack pointer\r
+;\r
+; @return Nothing. Goes to the Entry Point passing in the new parameters\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;SecSwitchStack (\r
+; VOID *StackDelta\r
+; );\r
+;\r
+SecSwitchStack \r
+ MOV R1, SP\r
+ ADD R1, R0, R1\r
+ MOV SP, R1\r
+ BX LR\r
+ END\r
--- /dev/null
+//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <AutoGen.h>
+
+#start of the code section
+.text
+.align 5\r
+\r
+# IMPORT
+GCC_ASM_IMPORT(SecCommonExceptionEntry)
+
+# EXPORT
+GCC_ASM_EXPORT(SecVectorTable)
+\r
+//============================================================
+//Default Exception Handlers
+//============================================================
+
+//FIXME: One of the EDK2 tool is broken. It does not look to respect the alignment. Even, if we specify 32-byte alignment for this file.
+Dummy1: .word 0\r
+Dummy2: .word 0\r
+
+ASM_PFX(SecVectorTable):
+ b _DefaultResetHandler
+ b _DefaultUndefined
+ b _DefaultSWI
+ b _DefaultPrefetchAbort
+ b _DefaultDataAbort
+ b _DefaultReserved
+ b _DefaultIrq
+ b _DefaultFiq
+
+//
+// Default Exception handlers: There is no plan to return from any of these exceptions.
+// No context saving at all.
+//
+_DefaultResetHandler:
+ mov r1, lr
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #0
+ blx ASM_PFX(SecCommonExceptionEntry)
+
+_DefaultUndefined:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #1
+ blx ASM_PFX(SecCommonExceptionEntry)
+
+_DefaultSWI:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #2
+ blx ASM_PFX(SecCommonExceptionEntry)
+
+_DefaultPrefetchAbort:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #3
+ blx ASM_PFX(SecCommonExceptionEntry)
+
+_DefaultDataAbort:
+ sub r1, LR, #8
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #4
+ blx ASM_PFX(SecCommonExceptionEntry)
+
+_DefaultReserved:
+ mov r1, lr
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #5
+ blx SecCommonExceptionEntry
+
+_DefaultIrq:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #6
+ blx SecCommonExceptionEntry
+
+_DefaultFiq:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #7
+ blx SecCommonExceptionEntry
+\r
+.end\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+ IMPORT SecCommonExceptionEntry\r
+ EXPORT SecVectorTable\r
+ \r
+ PRESERVE8\r
+ AREA SecException, CODE, READONLY, CODEALIGN, ALIGN=5\r
+\r
+//============================================================
+//Default Exception Handlers
+//============================================================
+
+//FIXME: One of the EDK2 tool is broken. It does not look to respect the alignment. Even, if we specify 32-byte alignment for this file.
+Dummy1 DCD 0\r
+Dummy2 DCD 0\r
+
+SecVectorTable
+ b _DefaultResetHandler
+ b _DefaultUndefined
+ b _DefaultSWI
+ b _DefaultPrefetchAbort
+ b _DefaultDataAbort
+ b _DefaultReserved
+ b _DefaultIrq
+ b _DefaultFiq
+\r
+//
+// Default Exception handlers: There is no plan to return from any of these exceptions.\r
+// No context saving at all.\r
+//
+_DefaultResetHandler
+ mov r1, lr\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #0
+ blx SecCommonExceptionEntry
+
+_DefaultUndefined
+ sub r1, LR\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #1
+ blx SecCommonExceptionEntry
+
+_DefaultSWI
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #2
+ blx SecCommonExceptionEntry
+
+_DefaultPrefetchAbort
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #3
+ blx SecCommonExceptionEntry
+
+_DefaultDataAbort
+ sub r1, LR, #8\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #4
+ blx SecCommonExceptionEntry
+
+_DefaultReserved
+ mov r1, lr\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #5
+ blx SecCommonExceptionEntry
+
+_DefaultIrq
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #6
+ blx SecCommonExceptionEntry
+
+_DefaultFiq
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack
+ mov r0, #7
+ blx SecCommonExceptionEntry
+\r
+ END\r
--- /dev/null
+#========================================================================================\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http:#opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#=======================================================================================\r
+\r
+#start of the code section\r
+.text \r
+.align 3\r
+\r
+GCC_ASM_EXPORT(monitor_vector_table)\r
+GCC_ASM_EXPORT(return_from_exception)\r
+GCC_ASM_EXPORT(enter_monitor_mode)\r
+GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
+\r
+ASM_PFX(monitor_vector_table):\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+\r
+# arg0: Secure Monitor mode stack\r
+ASM_PFX(enter_monitor_mode):\r
+ mov r2, lr @ Save current lr\r
+\r
+ mrs r1, cpsr @ Save current mode (SVC) in r1\r
+ bic r3, r1, #0x1f @ Clear all mode bits\r
+ orr r3, r3, #0x16 @ Set bits for Monitor mode\r
+ msr cpsr_cxsf, r3 @ We are now in Monitor Mode\r
+\r
+ mov sp, r0 @ Use the passed sp\r
+ mov lr, r2 @ Use the same lr as before\r
+ \r
+ msr spsr_cxsf, r1 @ Use saved mode for the MOVS jump to the kernel\r
+ bx lr\r
+\r
+# We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.\r
+# When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into\r
+# 'pc'; we will not change the CPSR flag and it will crash.\r
+# The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'.\r
+ASM_PFX(return_from_exception):\r
+ ldr lr, returned_exception\r
+\r
+ #The following instruction breaks the code.\r
+ #movs pc, lr\r
+ mrs r2, cpsr\r
+ bic r2, r2, #0x1f\r
+ orr r2, r2, #0x13\r
+ msr cpsr_c, r2\r
+\r
+returned_exception: @ We are now in non-secure state\r
+ bx r0\r
+\r
+# Save the current Program Status Register (PSR) into the Saved PSR\r
+ASM_PFX(copy_cpsr_into_spsr):\r
+ mrs r0, cpsr\r
+ msr spsr_cxsf, r0\r
+ bx lr\r
+\r
+dead:\r
+ B dead\r
+ \r
+.end\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+ EXPORT monitor_vector_table\r
+ EXPORT return_from_exception\r
+ EXPORT enter_monitor_mode\r
+ EXPORT copy_cpsr_into_spsr\r
+ \r
+ AREA Helper, CODE, READONLY\r
+\r
+ ALIGN 32\r
+monitor_vector_table\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+ ldr pc, dead\r
+\r
+// arg0: Secure Monitor mode stack\r
+enter_monitor_mode\r
+ mov r2, lr // Save current lr\r
+\r
+ mrs r1, cpsr // Save current mode (SVC) in r1\r
+ bic r3, r1, #0x1f // Clear all mode bits\r
+ orr r3, r3, #0x16 // Set bits for Monitor mode\r
+ msr cpsr_cxsf, r3 // We are now in Monitor Mode\r
+\r
+ mov sp, r0 // Use the passed sp\r
+ mov lr, r2 // Use the same lr as before\r
+ \r
+ msr spsr_cxsf, r1 // Use saved mode for the MOVS jump to the kernel\r
+ bx lr\r
+\r
+// We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.\r
+// When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into\r
+// 'pc'; we will not change the CPSR flag and it will crash.\r
+// The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'.\r
+return_from_exception\r
+ adr lr, returned_exception\r
+ movs pc, lr\r
+returned_exception // We are now in non-secure state\r
+ bx r0\r
+\r
+// Save the current Program Status Register (PSR) into the Saved PSR\r
+copy_cpsr_into_spsr\r
+ mrs r0, cpsr\r
+ msr spsr_cxsf, r0\r
+ bx lr\r
+\r
+dead\r
+ B dead\r
+ \r
+ END\r
--- /dev/null
+/** @file
+* Main file supporting the SEC Phase for Versatile Express
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ArmLib.h>
+#include <Chipset/ArmV7.h>
+#include <Drivers/PL390Gic.h>
+#include <Library/L2X0CacheLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/ArmPlatformLib.h>
+
+extern VOID *monitor_vector_table;
+
+VOID ArmSetupGicNonSecure (
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
+);
+
+// Vector Table for Sec Phase
+VOID SecVectorTable (VOID);
+
+VOID NonSecureWaitForFirmware (
+ VOID
+ );
+
+VOID
+enter_monitor_mode(
+ IN VOID* Stack
+ );
+
+VOID
+return_from_exception (
+ IN UINTN NonSecureBase
+ );
+
+VOID
+copy_cpsr_into_spsr (
+ VOID
+ );
+
+VOID
+CEntryPoint (
+ IN UINTN CoreId
+ )
+{
+ // Primary CPU clears out the SCU tag RAMs, secondaries wait
+ if (CoreId == 0) {
+ if (FixedPcdGet32(PcdMPCoreSupport)) {
+ ArmInvalidScu();
+ }
+
+ // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
+ // In non SEC modules the init call is in autogenerated code.
+ SerialPortInitialize ();
+ // Start talking
+ DEBUG ((EFI_D_ERROR, "UART Enabled\n"));
+
+ // Now we've got UART, make the check:
+ // - The Vector table must be 32-byte aligned
+ ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
+ }
+
+ // Invalidate the data cache. Doesn't have to do the Data cache clean.
+ ArmInvalidateDataCache();
+
+ //Invalidate Instruction Cache
+ ArmInvalidateInstructionCache();
+
+ //Invalidate I & D TLBs
+ ArmInvalidateInstructionAndDataTlb();
+
+ // Enable Full Access to CoProcessors
+ ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
+
+ // Enable SWP instructions
+ ArmEnableSWPInstruction();
+
+ // Enable program flow prediction, if supported.
+ ArmEnableBranchPrediction();
+
+ if (FixedPcdGet32(PcdVFPEnabled)) {
+ ArmEnableVFP();
+ }
+
+ if (CoreId == 0) {
+ // Initialize L2X0 but not enabled
+ L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase), FALSE);
+
+ // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
+ // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
+ if (FeaturePcdGet(PcdSkipPeiCore) || !FeaturePcdGet(PcdStandalone)) {
+ // Initialize system memory (DRAM)
+ ArmPlatformInitializeSystemMemory();
+ }
+
+ // Turn Off NOR flash remapping to 0. We can will now see DRAM in low memory
+ ArmPlatformBootRemapping();
+ }
+
+ // Test if Trustzone is supported on this platform
+ if (ArmPlatformTrustzoneSupported()) {
+ if (FixedPcdGet32(PcdMPCoreSupport)) {
+ // Setup SMP in Non Secure world
+ ArmSetupSmpNonSecure(CoreId);
+ }
+
+ // Enter Monitor Mode
+ enter_monitor_mode((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * CoreId)));
+
+ //Write the monitor mode vector table address
+ ArmWriteVMBar((UINT32) &monitor_vector_table);
+
+ //-------------------- Monitor Mode ---------------------
+ // setup the Trustzone Chipsets
+ if (CoreId == 0) {
+ ArmPlatformTrustzoneInit();
+
+ // Wake up the secondary cores by sending a interrupt to everyone else
+ // NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
+ // MPcore test chip on Versatile Express board, So the Software doesn't have to
+ // enable SGI's explicitly.
+ // 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
+ // 3: As all the cores are in secure state, use secure SGI's
+ //
+
+ PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase));
+
+ // Send SGI to all Secondary core to wake them up from WFI state.
+ PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ } else {
+ // The secondary cores need to wait until the Trustzone chipsets configuration is done
+ // before swtching to Non Secure World
+
+ // Enabled GIC CPU Interface
+ PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+
+ // Waiting for the SGI from the primary core
+ ArmCallWFI();
+
+ //Acknowledge the interrupt and send End of Interrupt signal.
+ PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
+ }
+
+ // Transfer the interrupt to Non-secure World
+ PL390GicSetupNonSecure(PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
+
+ // Write to CP15 Non-secure Access Control Register :
+ // - Enable CP10 and CP11 accesses in NS World
+ // - Enable Access to Preload Engine in NS World
+ // - Enable lockable TLB entries allocation in NS world
+ // - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
+ ArmWriteNsacr(NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11));
+
+ // CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
+ // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
+ ArmWriteScr(SCR_NS | SCR_FW | SCR_AW);
+ } else {
+ if(0 == CoreId){
+ DEBUG ((EFI_D_ERROR, "Trust Zone Configuration is disabled\n"));
+ }
+
+ //Trustzone is not enabled, just enable the Distributor and CPU interface
+ PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase));
+
+ // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
+ // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
+ // Status Register as the the current one (CPSR).
+ copy_cpsr_into_spsr();
+ }
+
+ // If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
+ if (FeaturePcdGet(PcdStandalone) == FALSE) {
+ if (CoreId == 0) {
+ UINTN* StartAddress = (UINTN*)PcdGet32(PcdEmbeddedFdBaseAddress);
+
+ DEBUG ((EFI_D_ERROR, "Waiting for firmware at 0x%08X ...\n",StartAddress));
+
+ // Patch the DRAM to make an infinite loop at the start address
+ *StartAddress = 0xEAFFFFFE; // opcode for while(1)
+
+ // To enter into Non Secure state, we need to make a return from exception
+ return_from_exception(PcdGet32(PcdEmbeddedFdBaseAddress));
+ } else {
+ // When the primary core is stopped by the hardware debugger to copy the firmware
+ // into DRAM. The secondary cores are still running. As soon as the first bytes of
+ // the firmware are written into DRAM, the secondary cores will start to execute the
+ // code even if the firmware is not entirely written into the memory.
+ // That's why the secondary cores need to be parked in WFI and wake up once the
+ // firmware is ready.
+
+ // Enter Secondary Cores into non Secure State. To enter into Non Secure state, we need to make a return from exception
+ return_from_exception((UINTN)NonSecureWaitForFirmware);
+ }
+ } else {
+ if (CoreId == 0) {
+ DEBUG ((EFI_D_ERROR, "Standalone Firmware\n"));
+ }
+
+ // To enter into Non Secure state, we need to make a return from exception
+ return_from_exception(PcdGet32(PcdEmbeddedFdBaseAddress));
+ }
+ //-------------------- Non Secure Mode ---------------------
+
+ // PEI Core should always load and never return
+ ASSERT (FALSE);
+}
+
+// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
+// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
+VOID NonSecureWaitForFirmware() {
+ VOID (*secondary_start)(VOID);
+
+ // The secondary cores will execute the fimrware once wake from WFI.
+ secondary_start = (VOID (*)())PcdGet32(PcdEmbeddedFdBaseAddress);
+
+ ArmCallWFI();
+
+ //Acknowledge the interrupt and send End of Interrupt signal.
+ PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
+
+ //Jump to secondary core entry point.
+ secondary_start();
+
+ // PEI Core should always load and never return
+ ASSERT (FALSE);
+}
+
+VOID SecCommonExceptionEntry(UINT32 Entry, UINT32 LR) {
+ switch (Entry) {
+ case 0:
+ DEBUG((EFI_D_ERROR,"Reset Exception at 0x%X\n",LR));
+ break;
+ case 1:
+ DEBUG((EFI_D_ERROR,"Undefined Exception at 0x%X\n",LR));
+ break;
+ case 2:
+ DEBUG((EFI_D_ERROR,"SWI Exception at 0x%X\n",LR));
+ break;
+ case 3:
+ DEBUG((EFI_D_ERROR,"PrefetchAbort Exception at 0x%X\n",LR));
+ break;
+ case 4:
+ DEBUG((EFI_D_ERROR,"DataAbort Exception at 0x%X\n",LR));
+ break;
+ case 5:
+ DEBUG((EFI_D_ERROR,"Reserved Exception at 0x%X\n",LR));
+ break;
+ case 6:
+ DEBUG((EFI_D_ERROR,"IRQ Exception at 0x%X\n",LR));
+ break;
+ case 7:
+ DEBUG((EFI_D_ERROR,"FIQ Exception at 0x%X\n",LR));
+ break;
+ default:
+ DEBUG((EFI_D_ERROR,"Unknown Exception at 0x%X\n",LR));
+ break;
+ }
+ while(1);
+}
--- /dev/null
+#/** @file
+# SEC - Reset vector code that jumps to C and loads DXE core
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmPlatformSec
+ FILE_GUID = c536bbfe-c813-4e48-9f90-01fe1ecf9d54
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+
+[Sources.ARM]
+ Helper.asm | RVCT
+ Helper.S | GCC
+ Sec.c
+ SecEntryPoint.S | GCC
+ SecEntryPoint.asm | RVCT
+ Exception.asm | RVCT
+ Exception.S | GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ ArmLib
+ ArmPlatformLib
+ L2X0CacheLib
+ PL390GicSecLib
+
+[FeaturePcd]
+ gArmPlatformTokenSpaceGuid.PcdStandalone
+ gArmTokenSpaceGuid.PcdSkipPeiCore
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdVFPEnabled
+ gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
+
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
--- /dev/null
+#------------------------------------------------------------------------------
+#
+# ARM VE Entry point. Reset vector in FV header will brach to
+# _ModuleEntryPoint.
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/PcdLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <AutoGen.h>
+
+#Start of Code section
+.text
+.align 3
+
+#make _ModuleEntryPoint as global
+GCC_ASM_EXPORT(_ModuleEntryPoint)
+
+#global functions referenced by this module
+GCC_ASM_IMPORT(CEntryPoint)
+GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)
+GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
+GCC_ASM_IMPORT(ArmDisableInterrupts)
+GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
+GCC_ASM_IMPORT(ArmWriteVBar)
+GCC_ASM_IMPORT(SecVectorTable)
+
+#if (FixedPcdGet32(PcdMPCoreSupport))
+GCC_ASM_IMPORT(ArmIsScuEnable)
+#endif
+
+StartupAddr: .word CEntryPoint
+SecVectorTableAddr: .word SecVectorTable
+
+ASM_PFX(_ModuleEntryPoint):
+ #Set VBAR to the start of the exception vectors in Secure Mode
+ ldr r0, SecVectorTableAddr
+ bl ASM_PFX(ArmWriteVBar)
+
+ # First ensure all interrupts are disabled
+ bl ASM_PFX(ArmDisableInterrupts)
+
+ # Ensure that the MMU and caches are off
+ bl ASM_PFX(ArmDisableCachesAndMmu)
+
+_IdentifyCpu:
+ # Identify CPU ID
+ bl ASM_PFX(ArmReadMpidr)
+ and r5, r0, #0xf
+
+ #get ID of this CPU in Multicore system
+ cmp r5, #0
+ # Only the primary core initialize the memory (SMC)
+ beq _InitMem
+
+#if (FixedPcdGet32(PcdMPCoreSupport))
+ # ... The secondary cores wait for SCU to be enabled
+_WaitForEnabledScu:
+ bl ASM_PFX(ArmIsScuEnable)
+ tst r1, #1
+ beq _WaitForEnabledScu
+ b _SetupStack
+#endif
+
+_InitMem:
+ bl ASM_PFX(ArmPlatformIsMemoryInitialized)
+ bne _SetupStack
+
+ # Initialize Init Memory
+ bl ASM_PFX(ArmPlatformInitializeBootMemory)
+
+ # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
+ mov r5, #0
+
+_SetupStack:
+ # Setup Stack for the 4 CPU cores
+ #Read Stack Base address from PCD
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase) ,r1)
+
+ #read Stack size from PCD
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize) ,r2)
+
+ #calcuate Stack Pointer reg value using Stack size and CPU ID.
+ mov r3,r5 @ r3 = core_id
+ mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
+ add r3,r3,r1 @ r3 ldr= stack_base + offset
+ mov sp, r3
+
+ # move sec startup address into a data register
+ # ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr r3, StartupAddr
+
+ # Move the CoreId in r0 to be the first argument of the SEC Entry Point
+ mov r0, r5
+
+ # jump to SEC C code
+ # r0 = core_id
+ blx r3
+
+.end
--- /dev/null
+//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AutoGen.h>
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/PcdLib.h>
+#include <Library/ArmPlatformLib.h>
+
+ INCLUDE AsmMacroIoLib.inc
+
+ IMPORT CEntryPoint
+ IMPORT ArmPlatformIsMemoryInitialized
+ IMPORT ArmPlatformInitializeBootMemory
+ IMPORT ArmDisableInterrupts
+ IMPORT ArmDisableCachesAndMmu
+ IMPORT ArmWriteVBar
+ IMPORT ArmReadMpidr
+ IMPORT SecVectorTable
+ EXPORT _ModuleEntryPoint
+
+#if (FixedPcdGet32(PcdMPCoreSupport))
+ IMPORT ArmIsScuEnable
+#endif
+
+ PRESERVE8
+ AREA SecEntryPoint, CODE, READONLY
+
+StartupAddr DCD CEntryPoint
+
+_ModuleEntryPoint
+ //Set VBAR to the start of the exception vectors in Secure Mode
+ ldr r0, =SecVectorTable
+ blx ArmWriteVBar
+
+ // First ensure all interrupts are disabled
+ blx ArmDisableInterrupts
+
+ // Ensure that the MMU and caches are off
+ blx ArmDisableCachesAndMmu
+
+_IdentifyCpu
+ // Identify CPU ID
+ bl ArmReadMpidr
+ and r5, r0, #0xf
+
+ //get ID of this CPU in Multicore system
+ cmp r5, #0
+ // Only the primary core initialize the memory (SMC)
+ beq _InitMem
+
+#if (FixedPcdGet32(PcdMPCoreSupport))
+ // ... The secondary cores wait for SCU to be enabled
+_WaitForEnabledScu
+ bl ArmIsScuEnable
+ tst r1, #1
+ beq _WaitForEnabledScu
+ b _SetupStack
+#endif
+
+_InitMem
+ bl ArmPlatformIsMemoryInitialized
+ bne _SetupStack
+
+ // Initialize Init Memory
+ bl ArmPlatformInitializeBootMemory
+
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
+ mov r5, #0
+
+_SetupStack
+ // Setup Stack for the 4 CPU cores
+ //Read Stack Base address from PCD
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
+
+ // Read Stack size from PCD
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
+
+ // Calcuate Stack Pointer reg value using Stack size and CPU ID.
+ mov r3,r5 // r3 = core_id
+ mul r3,r3,r2 // r3 = core_id * stack_size = offset from the stack base
+ add r3,r3,r1 // r3 = stack_base + offset
+ mov sp, r3
+
+ // Move sec startup address into a data register
+ // ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr r3, StartupAddr
+
+ // Jump to SEC C code
+ // r0 = core_id
+ mov r0, r5
+ blx r3
+
+ END
projects / mirror_edk2.git / commitdiff