\r
Ia32/GccInline.c | GCC\r
Ia32/Thunk16.nasm | GCC\r
- Ia32/Thunk16.S | XCODE\r
Ia32/EnableDisableInterrupts.nasm| GCC\r
- Ia32/EnableDisableInterrupts.S | GCC\r
Ia32/EnablePaging64.nasm| GCC\r
- Ia32/EnablePaging64.S | GCC\r
Ia32/DisablePaging32.nasm| GCC\r
- Ia32/DisablePaging32.S | GCC\r
Ia32/EnablePaging32.nasm| GCC\r
- Ia32/EnablePaging32.S | GCC\r
Ia32/Mwait.nasm| GCC\r
- Ia32/Mwait.S | GCC\r
Ia32/Monitor.nasm| GCC\r
- Ia32/Monitor.S | GCC\r
Ia32/CpuIdEx.nasm| GCC\r
- Ia32/CpuIdEx.S | GCC\r
Ia32/CpuId.nasm| GCC\r
- Ia32/CpuId.S | GCC\r
Ia32/LongJump.nasm| GCC\r
- Ia32/LongJump.S | GCC\r
Ia32/SetJump.nasm| GCC\r
- Ia32/SetJump.S | GCC\r
Ia32/SwapBytes64.nasm| GCC\r
- Ia32/SwapBytes64.S | GCC\r
Ia32/DivU64x64Remainder.nasm| GCC\r
- Ia32/DivU64x64Remainder.S | GCC\r
Ia32/DivU64x32Remainder.nasm| GCC\r
- Ia32/DivU64x32Remainder.S | GCC\r
Ia32/ModU64x32.nasm| GCC\r
- Ia32/ModU64x32.S | GCC\r
Ia32/DivU64x32.nasm| GCC\r
- Ia32/DivU64x32.S | GCC\r
Ia32/MultU64x64.nasm| GCC\r
- Ia32/MultU64x64.S | GCC\r
Ia32/MultU64x32.nasm| GCC\r
- Ia32/MultU64x32.S | GCC\r
Ia32/RRotU64.nasm| GCC\r
- Ia32/RRotU64.S | GCC\r
Ia32/LRotU64.nasm| GCC\r
- Ia32/LRotU64.S | GCC\r
Ia32/ARShiftU64.nasm| GCC\r
- Ia32/ARShiftU64.S | GCC\r
Ia32/RShiftU64.nasm| GCC\r
- Ia32/RShiftU64.S | GCC\r
Ia32/LShiftU64.nasm| GCC\r
- Ia32/LShiftU64.S | GCC\r
Ia32/EnableCache.nasm| GCC\r
- Ia32/EnableCache.S | GCC\r
Ia32/DisableCache.nasm| GCC\r
- Ia32/DisableCache.S | GCC\r
Ia32/RdRand.nasm| GCC\r
- Ia32/RdRand.S | GCC\r
\r
Ia32/DivS64x64Remainder.c\r
Ia32/InternalSwitchStack.c | MSFT\r
Ia32/InternalSwitchStack.c | INTEL\r
- Ia32/InternalSwitchStack.S | GCC\r
Ia32/InternalSwitchStack.nasm | GCC\r
Ia32/Non-existing.c\r
Unaligned.c\r
X86PatchInstruction.c\r
X86SpeculationBarrier.c\r
X64/GccInline.c | GCC\r
- X64/Thunk16.S | XCODE\r
X64/SwitchStack.nasm| GCC\r
- X64/SwitchStack.S | GCC\r
X64/SetJump.nasm| GCC\r
- X64/SetJump.S | GCC\r
X64/LongJump.nasm| GCC\r
- X64/LongJump.S | GCC\r
X64/EnableDisableInterrupts.nasm| GCC\r
- X64/EnableDisableInterrupts.S | GCC\r
X64/DisablePaging64.nasm| GCC\r
- X64/DisablePaging64.S | GCC\r
X64/CpuId.nasm| GCC\r
- X64/CpuId.S | GCC\r
X64/CpuIdEx.nasm| GCC\r
- X64/CpuIdEx.S | GCC\r
X64/EnableCache.nasm| GCC\r
- X64/EnableCache.S | GCC\r
X64/DisableCache.nasm| GCC\r
- X64/DisableCache.S | GCC\r
X64/RdRand.nasm| GCC\r
- X64/RdRand.S | GCC\r
ChkStkGcc.c | GCC\r
\r
[Sources.EBC]\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# ARShiftU64.S\r
-#\r
-# Abstract:\r
-#\r
-# 64-bit arithmetic right shift function for IA-32\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathARShiftU64)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathARShiftU64 (\r
-# IN UINT64 Operand,\r
-# IN UINTN Count\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathARShiftU64):\r
- movb 12(%esp), %cl\r
- movl 8(%esp), %eax\r
- cltd\r
- testb $32, %cl\r
- jnz L0\r
- movl %eax, %edx\r
- movl 4(%esp), %eax\r
-L0:\r
- shrdl %cl, %edx, %eax\r
- sar %cl, %edx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# CpuId.S\r
-#\r
-# Abstract:\r
-#\r
-# AsmCpuid function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(AsmCpuid)\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# AsmCpuid (\r
-# IN UINT32 RegisterInEax,\r
-# OUT UINT32 *RegisterOutEax OPTIONAL,\r
-# OUT UINT32 *RegisterOutEbx OPTIONAL,\r
-# OUT UINT32 *RegisterOutEcx OPTIONAL,\r
-# OUT UINT32 *RegisterOutEdx OPTIONAL\r
-# )\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(AsmCpuid):\r
- push %ebx\r
- push %ebp\r
- movl %esp, %ebp\r
- movl 12(%ebp), %eax\r
- cpuid\r
- push %ecx\r
- movl 16(%ebp), %ecx\r
- jecxz L1\r
- movl %eax, (%ecx)\r
-L1:\r
- movl 20(%ebp), %ecx\r
- jecxz L2\r
- movl %ebx, (%ecx)\r
-L2:\r
- movl 24(%ebp), %ecx\r
- jecxz L3\r
- popl (%ecx)\r
-L3:\r
- movl 28(%ebp), %ecx\r
- jecxz L4\r
- movl %edx, (%ecx)\r
-L4:\r
- movl 12(%ebp), %eax\r
- leave\r
- pop %ebx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# CpuIdEx.S\r
-#\r
-# Abstract:\r
-#\r
-# AsmCpuidEx function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-\r
- .code:\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT32\r
-# EFIAPI\r
-# AsmCpuidEx (\r
-# IN UINT32 RegisterInEax,\r
-# IN UINT32 RegisterInEcx,\r
-# OUT UINT32 *RegisterOutEax OPTIONAL,\r
-# OUT UINT32 *RegisterOutEbx OPTIONAL,\r
-# OUT UINT32 *RegisterOutEcx OPTIONAL,\r
-# OUT UINT32 *RegisterOutEdx OPTIONAL\r
-# )\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(AsmCpuidEx)\r
-ASM_PFX(AsmCpuidEx):\r
- push %ebx\r
- push %ebp\r
- movl %esp, %ebp\r
- movl 12(%ebp), %eax\r
- movl 16(%ebp), %ecx\r
- cpuid\r
- push %ecx\r
- movl 20(%ebp), %ecx\r
- jecxz L1\r
- movl %eax, (%ecx)\r
-L1:\r
- movl 24(%ebp), %ecx\r
- jecxz L2\r
- movl %ebx, (%ecx)\r
-L2:\r
- movl 32(%ebp), %ecx\r
- jecxz L3\r
- movl %edx, (%ecx)\r
-L3:\r
- movl 28(%ebp), %ecx\r
- jecxz L4\r
- popl (%ecx)\r
-L4:\r
- movl 12(%ebp), %eax\r
- leave\r
- pop %ebx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# DisableCache.S\r
-#\r
-# Abstract:\r
-#\r
-# Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
-# WBINVD instruction.\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# AsmDisableCache (\r
-# VOID\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(AsmDisableCache)\r
-ASM_PFX(AsmDisableCache):\r
- movl %cr0, %eax\r
- btsl $30, %eax\r
- btrl $29, %eax\r
- movl %eax, %cr0\r
- wbinvd\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# DisablePaging32.S\r
-#\r
-# Abstract:\r
-#\r
-# InternalX86DisablePaging32 function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalX86DisablePaging32)\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# InternalX86DisablePaging32 (\r
-# IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
-# IN VOID *Context1, OPTIONAL\r
-# IN VOID *Context2, OPTIONAL\r
-# IN VOID *NewStack\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalX86DisablePaging32):\r
- movl 4(%esp), %ebx\r
- movl 8(%esp), %ecx\r
- movl 12(%esp), %edx\r
- pushfl\r
- pop %edi # save EFLAGS to edi\r
- cli\r
- movl %cr0, %eax\r
- btrl $31, %eax\r
- movl 16(%esp), %esp\r
- movl %eax, %cr0\r
- push %edi\r
- popfl # restore EFLAGS from edi\r
- push %edx\r
- push %ecx\r
- call *%ebx\r
- jmp . # EntryPoint() should not return\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# DivU64x32.S\r
-#\r
-# Abstract:\r
-#\r
-# Calculate the quotient of a 64-bit integer by a 32-bit integer\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathDivU64x32)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathDivU64x32 (\r
-# IN UINT64 Dividend,\r
-# IN UINT32 Divisor\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathDivU64x32):\r
- movl 8(%esp), %eax\r
- movl 12(%esp), %ecx\r
- xorl %edx, %edx\r
- divl %ecx\r
- push %eax # save quotient on stack\r
- movl 8(%esp), %eax\r
- divl %ecx\r
- pop %edx # restore high-order dword of the quotient\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# DivError.S\r
-#\r
-# Abstract:\r
-#\r
-# Set error flag for all division functions\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathDivRemU64x32)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathDivRemU64x32 (\r
-# IN UINT64 Dividend,\r
-# IN UINT32 Divisor,\r
-# OUT UINT32 *Remainder\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathDivRemU64x32):\r
- movl 12(%esp), %ecx # ecx <- divisor\r
- movl 8(%esp), %eax # eax <- dividend[32..63]\r
- xorl %edx, %edx\r
- divl %ecx # eax <- quotient[32..63], edx <- remainder\r
- push %eax\r
- movl 8(%esp), %eax # eax <- dividend[0..31]\r
- divl %ecx # eax <- quotient[0..31]\r
- movl 20(%esp), %ecx # ecx <- Remainder\r
- jecxz L1 # abandon remainder if Remainder == NULL\r
- movl %edx, (%ecx)\r
-L1:\r
- pop %edx # edx <- quotient[32..63]\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# DivU64x64Remainder.S\r
-#\r
-# Abstract:\r
-#\r
-# Calculate the quotient of a 64-bit integer by a 64-bit integer and returns\r
-# both the quotient and the remainder\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathDivRemU64x32), ASM_PFX(InternalMathDivRemU64x64)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathDivRemU64x64 (\r
-# IN UINT64 Dividend,\r
-# IN UINT64 Divisor,\r
-# OUT UINT64 *Remainder OPTIONAL\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathDivRemU64x64):\r
- movl 16(%esp), %ecx # ecx <- divisor[32..63]\r
- testl %ecx, %ecx\r
- jnz Hard # call _@DivRemU64x64 if Divisor > 2^32\r
- movl 20(%esp), %ecx\r
- jecxz L1\r
- andl $0, 4(%ecx) # zero high dword of remainder\r
- movl %ecx, 16(%esp) # set up stack frame to match DivRemU64x32\r
-L1:\r
- jmp ASM_PFX(InternalMathDivRemU64x32)\r
-Hard:\r
- push %ebx\r
- push %esi\r
- push %edi\r
- mov 20(%esp), %edx\r
- mov 16(%esp), %eax # edx:eax <- dividend\r
- movl %edx, %edi\r
- movl %eax, %esi # edi:esi <- dividend\r
- mov 24(%esp), %ebx # ecx:ebx <- divisor\r
-L2:\r
- shrl %edx\r
- rcrl $1, %eax\r
- shrdl $1, %ecx, %ebx\r
- shrl %ecx\r
- jnz L2\r
- divl %ebx\r
- movl %eax, %ebx # ebx <- quotient\r
- movl 28(%esp), %ecx # ecx <- high dword of divisor\r
- mull 24(%esp) # edx:eax <- quotient * divisor[0..31]\r
- imull %ebx, %ecx # ecx <- quotient * divisor[32..63]\r
- addl %ecx, %edx # edx <- (quotient * divisor)[32..63]\r
- mov 32(%esp), %ecx # ecx <- addr for Remainder\r
- jc TooLarge # product > 2^64\r
- cmpl %edx, %edi # compare high 32 bits\r
- ja Correct\r
- jb TooLarge # product > dividend\r
- cmpl %eax, %esi\r
- jae Correct # product <= dividend\r
-TooLarge:\r
- decl %ebx # adjust quotient by -1\r
- jecxz Return # return if Remainder == NULL\r
- sub 24(%esp), %eax\r
- sbb 28(%esp), %edx # edx:eax <- (quotient - 1) * divisor\r
-Correct:\r
- jecxz Return\r
- subl %eax, %esi\r
- sbbl %edx, %edi # edi:esi <- remainder\r
- movl %esi, (%ecx)\r
- movl %edi, 4(%ecx)\r
-Return:\r
- movl %ebx, %eax # eax <- quotient\r
- xorl %edx, %edx # quotient is 32 bits long\r
- pop %edi\r
- pop %esi\r
- pop %ebx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# EnableCache.S\r
-#\r
-# Abstract:\r
-#\r
-# Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear\r
-# the NW bit of CR0 to 0\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# AsmEnableCache (\r
-# VOID\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(AsmEnableCache)\r
-ASM_PFX(AsmEnableCache):\r
- wbinvd\r
- movl %cr0, %eax\r
- btrl $30, %eax\r
- btrl $29, %eax\r
- movl %eax, %cr0\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# EnableDisableInterrupts.S\r
-#\r
-# Abstract:\r
-#\r
-# EnableDisableInterrupts function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(EnableDisableInterrupts)\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# EnableDisableInterrupts (\r
-# VOID\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(EnableDisableInterrupts):\r
- sti\r
- cli\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# EnablePaging32.S\r
-#\r
-# Abstract:\r
-#\r
-# InternalX86EnablePaging32 function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalX86EnablePaging32)\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# InternalX86EnablePaging32 (\r
-# IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
-# IN VOID *Context1, OPTIONAL\r
-# IN VOID *Context2, OPTIONAL\r
-# IN VOID *NewStack\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalX86EnablePaging32):\r
- movl 4(%esp), %ebx\r
- movl 8(%esp), %ecx\r
- movl 12(%esp), %edx\r
- pushfl\r
- pop %edi # save flags in edi\r
- cli\r
- movl %cr0, %eax\r
- btsl $31, %eax\r
- movl 16(%esp), %esp\r
- movl %eax, %cr0\r
- push %edi\r
- popfl # restore flags\r
- push %edx\r
- push %ecx\r
- call *%ebx\r
- jmp .\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# EnablePaging64.S\r
-#\r
-# Abstract:\r
-#\r
-# InternalX86EnablePaging64 function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalX86EnablePaging64)\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# InternalX86EnablePaging64 (\r
-# IN UINT16 CodeSelector,\r
-# IN UINT64 EntryPoint,\r
-# IN UINT64 Context1, OPTIONAL\r
-# IN UINT64 Context2, OPTIONAL\r
-# IN UINT64 NewStack\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalX86EnablePaging64):\r
- cli\r
- movl $LongStart, (%esp) # offset for far retf, seg is the 1st arg\r
- movl %cr4, %eax\r
- orb $0x20, %al\r
- movl %eax, %cr4 # enable PAE\r
- movl $0xc0000080, %ecx\r
- rdmsr\r
- orb $1, %ah # set LME\r
- wrmsr\r
- movl %cr0, %eax\r
- btsl $31, %eax # set PG\r
- movl %eax, %cr0 # enable paging\r
- lret # topmost 2 dwords hold the address\r
-LongStart: # long mode starts here\r
- .byte 0x67, 0x48 # 32-bit address size, 64-bit operand size\r
- movl (%esp), %ebx # mov rbx, [esp]\r
- .byte 0x67, 0x48\r
- movl 8(%esp), %ecx # mov rcx, [esp + 8]\r
- .byte 0x67, 0x48\r
- movl 0x10(%esp), %edx # mov rdx, [esp + 10h]\r
- .byte 0x67, 0x48\r
- movl 0x18(%esp), %esp # mov rsp, [esp + 18h]\r
- .byte 0x48\r
- addl $-0x20, %esp # add rsp, -20h\r
- call *%ebx # call rbx\r
- jmp . # no one should get here\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# Portions copyright (c) 2011, Apple Inc. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# InternalSwitchStack.S\r
-#\r
-# Abstract:\r
-#\r
-# Implementation of a stack switch on IA-32.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalSwitchStack)\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# InternalSwitchStack (\r
-# IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
-# IN VOID *Context1, OPTIONAL\r
-# IN VOID *Context2, OPTIONAL\r
-# IN VOID *NewStack\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalSwitchStack):\r
- pushl %ebp\r
- movl %esp, %ebp\r
-\r
- movl 20(%ebp), %esp # switch stack\r
- subl $8, %esp\r
-\r
- movl 16(%ebp), %eax\r
- movl %eax, 4(%esp)\r
- movl 12(%ebp), %eax\r
- movl %eax, (%esp)\r
- pushl $0 # keeps gdb from unwinding stack\r
- jmp *8(%ebp) # call and never return\r
-\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# LRotU64.S\r
-#\r
-# Abstract:\r
-#\r
-# 64-bit left rotation for Ia32\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathLRotU64)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathLRotU64 (\r
-# IN UINT64 Operand,\r
-# IN UINTN Count\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathLRotU64):\r
- push %ebx\r
- movb 16(%esp), %cl\r
- movl 12(%esp), %edx\r
- movl 8(%esp), %eax\r
- shldl %cl, %edx, %ebx\r
- shldl %cl, %eax, %edx\r
- rorl %cl, %ebx\r
- shldl %cl, %ebx, %eax\r
- testb $32, %cl # Count >= 32?\r
- jz L0\r
- movl %eax, %ecx\r
- movl %edx, %eax\r
- movl %ecx, %edx\r
-L0:\r
- pop %ebx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# LShiftU64.S\r
-#\r
-# Abstract:\r
-#\r
-# 64-bit left shift function for IA-32\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathLShiftU64)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathLShiftU64 (\r
-# IN UINT64 Operand,\r
-# IN UINTN Count\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathLShiftU64):\r
- movb 12(%esp), %cl\r
- xorl %eax, %eax\r
- movl 4(%esp), %edx\r
- testb $32, %cl # Count >= 32?\r
- jnz L0\r
- movl %edx, %eax\r
- movl 0x8(%esp), %edx\r
-L0:\r
- shld %cl, %eax, %edx\r
- shl %cl, %eax\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# LongJump.S\r
-#\r
-# Abstract:\r
-#\r
-# Implementation of _LongJump() on IA-32.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalLongJump)\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# InternalLongJump (\r
-# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
-# IN UINTN Value\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalLongJump):\r
- pop %eax # skip return address\r
- pop %edx # edx <- JumpBuffer\r
- pop %eax # eax <- Value\r
- movl (%edx), %ebx\r
- movl 4(%edx), %esi\r
- movl 8(%edx), %edi\r
- movl 12(%edx), %ebp\r
- movl 16(%edx), %esp\r
- jmp *20(%edx) # restore "eip"\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# DivU64x32.S\r
-#\r
-# Abstract:\r
-#\r
-# Calculate the remainder of a 64-bit integer by a 32-bit integer\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathModU64x32)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT32\r
-# EFIAPI\r
-# InternalMathModU64x32 (\r
-# IN UINT64 Dividend,\r
-# IN UINT32 Divisor\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathModU64x32):\r
- movl 8(%esp), %eax\r
- movl 12(%esp), %ecx\r
- xorl %edx, %edx\r
- divl %ecx\r
- movl 4(%esp), %eax\r
- divl %ecx\r
- movl %edx, %eax\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# Monitor.S\r
-#\r
-# Abstract:\r
-#\r
-# AsmMonitor function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(AsmMonitor)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# AsmMonitor (\r
-# IN UINTN Eax,\r
-# IN UINTN Ecx,\r
-# IN UINTN Edx\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(AsmMonitor):\r
- movl 4(%esp), %eax\r
- movl 8(%esp), %ecx\r
- movl 12(%esp), %edx\r
- monitor %eax, %ecx, %edx # monitor\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# MultU64x32.S\r
-#\r
-# Abstract:\r
-#\r
-# Calculate the product of a 64-bit integer and a 32-bit integer\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-\r
- .code:\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathMultU64x32)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathMultU64x32 (\r
-# IN UINT64 Multiplicand,\r
-# IN UINT32 Multiplier\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathMultU64x32):\r
- movl 12(%esp), %ecx\r
- movl %ecx, %eax\r
- imull 8(%esp), %ecx # overflow not detectable\r
- mull 0x4(%esp)\r
- addl %ecx, %edx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# MultU64x64.S\r
-#\r
-# Abstract:\r
-#\r
-# Calculate the product of a 64-bit integer and another 64-bit integer\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathMultU64x64)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathMultU64x64 (\r
-# IN UINT64 Multiplicand,\r
-# IN UINT64 Multiplier\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathMultU64x64):\r
- push %ebx\r
- movl 8(%esp), %ebx # ebx <- M1[0..31]\r
- movl 16(%esp), %edx # edx <- M2[0..31]\r
- movl %ebx, %ecx\r
- movl %edx, %eax\r
- imull 20(%esp), %ebx # ebx <- M1[0..31] * M2[32..63]\r
- imull 12(%esp), %edx # edx <- M1[32..63] * M2[0..31]\r
- addl %edx, %ebx # carries are abandoned\r
- mull %ecx # edx:eax <- M1[0..31] * M2[0..31]\r
- addl %ebx, %edx # carries are abandoned\r
- pop %ebx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# Mwait.S\r
-#\r
-# Abstract:\r
-#\r
-# AsmMwait function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(AsmMwait)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# AsmMwait (\r
-# IN UINTN Eax,\r
-# IN UINTN Ecx\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(AsmMwait):\r
- movl 4(%esp), %eax\r
- movl 8(%esp), %ecx\r
- mwait\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# RRotU64.S\r
-#\r
-# Abstract:\r
-#\r
-# 64-bit right rotation for Ia32\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathRRotU64)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathRRotU64 (\r
-# IN UINT64 Operand,\r
-# IN UINTN Count\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathRRotU64):\r
- push %ebx\r
- movb 16(%esp), %cl\r
- movl 8(%esp), %eax\r
- movl 12(%esp), %edx\r
- shrdl %cl, %eax, %ebx\r
- shrdl %cl, %edx, %eax\r
- roll %cl, %ebx\r
- shrdl %cl, %ebx, %edx\r
- testb $32, %cl # Count >= 32?\r
- jz L0\r
- movl %eax, %ecx # switch eax & edx if Count >= 32\r
- movl %edx, %eax\r
- movl %ecx, %edx\r
-L0:\r
- pop %ebx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# RShiftU64.S\r
-#\r
-# Abstract:\r
-#\r
-# 64-bit logical right shift function for IA-32\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-\r
- .code:\r
-\r
-ASM_GLOBAL ASM_PFX(InternalMathRShiftU64)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathRShiftU64 (\r
-# IN UINT64 Operand,\r
-# IN UINTN Count\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathRShiftU64):\r
- movb 12(%esp), %cl # cl <- Count\r
- xorl %edx, %edx\r
- movl 8(%esp), %eax\r
- testb $32, %cl # Count >= 32?\r
- jnz L0\r
- movl %eax, %edx\r
- movl 0x4(%esp), %eax\r
-L0:\r
- shrdl %cl, %edx, %eax\r
- shr %cl, %edx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------ ;\r
-# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# RdRand.S\r
-#\r
-# Abstract:\r
-#\r
-# Generates random number through CPU RdRand instruction under 32-bit platform.\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-//------------------------------------------------------------------------------\r
-// Generates a 16 bit random number through RDRAND instruction.\r
-// Return TRUE if Rand generated successfully, or FALSE if not.\r
-//\r
-// BOOLEAN EFIAPI InternalX86RdRand16 (UINT16 *Rand);\r
-//------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(InternalX86RdRand16)\r
-ASM_PFX(InternalX86RdRand16):\r
- .byte 0x0f, 0xc7, 0xf0 // rdrand r16: "0f c7 /6 ModRM:r/m(w)"\r
- jc rn16_ok // jmp if CF=1\r
- xor %eax, %eax // reg=0 if CF=0\r
- ret // return with failure status\r
-rn16_ok:\r
- mov 0x4(%esp), %edx\r
- mov %ax, (%edx)\r
- mov $0x1, %eax\r
- ret\r
-\r
-//------------------------------------------------------------------------------\r
-// Generates a 32 bit random number through RDRAND instruction.\r
-// Return TRUE if Rand generated successfully, or FALSE if not.\r
-//\r
-// BOOLEAN EFIAPI InternalX86RdRand32 (UINT32 *Rand);\r
-//------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(InternalX86RdRand32)\r
-ASM_PFX(InternalX86RdRand32):\r
- .byte 0x0f, 0xc7, 0xf0 // rdrand r32: "0f c7 /6 ModRM:r/m(w)"\r
- jc rn32_ok // jmp if CF=1\r
- xor %eax, %eax // reg=0 if CF=0\r
- ret // return with failure status\r
-rn32_ok:\r
- mov 0x4(%esp), %edx\r
- mov %eax, (%edx)\r
- mov $0x1, %eax\r
- ret\r
-\r
-//------------------------------------------------------------------------------\r
-// Generates a 64 bit random number through RDRAND instruction.\r
-// Return TRUE if Rand generated successfully, or FALSE if not.\r
-//\r
-// BOOLEAN EFIAPI InternalX86RdRand64 (UINT64 *Rand);\r
-//------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(InternalX86RdRand64)\r
-ASM_PFX(InternalX86RdRand64):\r
- .byte 0x0f, 0xc7, 0xf0 // rdrand r32: "0f c7 /6 ModRM:r/m(w)"\r
- jnc rn64_ret // jmp if CF=0\r
- mov 0x4(%esp), %edx\r
- mov %eax, (%edx)\r
-\r
- .byte 0x0f, 0xc7, 0xf0 // generate another 32 bit RN\r
- jnc rn64_ret // jmp if CF=0\r
- mov %eax, 0x4(%edx)\r
-\r
- mov $0x1, %eax\r
- ret\r
-rn64_ret:\r
- xor %eax, %eax\r
- ret // return with failure status\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# SetJump.S\r
-#\r
-# Abstract:\r
-#\r
-# Implementation of SetJump() on IA-32.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(SetJump), ASM_PFX(InternalAssertJumpBuffer)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINTN\r
-# EFIAPI\r
-# SetJump (\r
-# OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(SetJump):\r
- pushl 0x4(%esp)\r
- call ASM_PFX(InternalAssertJumpBuffer) # To validate JumpBuffer\r
- pop %ecx\r
- pop %ecx # ecx <- return address\r
- movl (%esp), %edx\r
- movl %ebx, (%edx)\r
- movl %esi, 4(%edx)\r
- movl %edi, 8(%edx)\r
- movl %ebp, 12(%edx)\r
- movl %esp, 16(%edx)\r
- movl %ecx, 20(%edx) # eip value to restore in LongJump\r
- xorl %eax, %eax\r
- jmp *%ecx\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# CpuId.S\r
-#\r
-# Abstract:\r
-#\r
-# AsmCpuid function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathSwapBytes64 (\r
-# IN UINT64 Operand\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(InternalMathSwapBytes64)\r
-ASM_PFX(InternalMathSwapBytes64):\r
- movl 8(%esp), %eax # eax <- upper 32 bits\r
- movl 4(%esp), %edx # edx <- lower 32 bits\r
- bswapl %eax\r
- bswapl %edx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# Thunk16.S\r
-#\r
-# Abstract:\r
-#\r
-# Real mode thunk\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <Library/BaseLib.h>\r
-\r
-ASM_GLOBAL ASM_PFX(m16Start), ASM_PFX(m16Size), ASM_PFX(mThunk16Attr), ASM_PFX(m16Gdt), ASM_PFX(m16GdtrBase), ASM_PFX(mTransition)\r
-ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
-\r
-# define the structure of IA32_REGS\r
-.set _EDI, 0 #size 4\r
-.set _ESI, 4 #size 4\r
-.set _EBP, 8 #size 4\r
-.set _ESP, 12 #size 4\r
-.set _EBX, 16 #size 4\r
-.set _EDX, 20 #size 4\r
-.set _ECX, 24 #size 4\r
-.set _EAX, 28 #size 4\r
-.set _DS, 32 #size 2\r
-.set _ES, 34 #size 2\r
-.set _FS, 36 #size 2\r
-.set _GS, 38 #size 2\r
-.set _EFLAGS, 40 #size 4\r
-.set _EIP, 44 #size 4\r
-.set _CS, 48 #size 2\r
-.set _SS, 50 #size 2\r
-.set IA32_REGS_SIZE, 52\r
-\r
- .text\r
- .code16\r
-\r
-ASM_PFX(m16Start):\r
-\r
-SavedGdt: .space 6\r
-\r
-ASM_PFX(BackFromUserCode):\r
- push %ss\r
- push %cs\r
-\r
- calll L_Base1 # push eip\r
-L_Base1:\r
- pushfl\r
- cli # disable interrupts\r
- push %gs\r
- push %fs\r
- push %es\r
- push %ds\r
- pushal\r
- .byte 0x66, 0xba # mov edx, imm32\r
-ASM_PFX(ThunkAttr): .space 4\r
- testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
- jz 1f\r
- movw $0x2401, %ax\r
- int $0x15\r
- cli # disable interrupts\r
- jnc 2f\r
-1:\r
- testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
- jz 2f\r
- inb $0x92, %al\r
- orb $2, %al\r
- outb %al, $0x92 # deactivate A20M#\r
-2:\r
- xorl %eax, %eax\r
- movw %ss, %ax\r
- leal IA32_REGS_SIZE(%esp), %ebp\r
- mov %ebp, (_ESP - IA32_REGS_SIZE)(%bp)\r
- mov (_EIP - IA32_REGS_SIZE)(%bp), %bx\r
- shll $4, %eax\r
- addl %eax, %ebp\r
- .byte 0x66, 0xb8 # mov eax, imm32\r
-SavedCr4: .space 4\r
- movl %eax, %cr4\r
- lgdtl %cs:(SavedGdt - L_Base1)(%bx)\r
- .byte 0x66, 0xb8 # mov eax, imm32\r
-SavedCr0: .space 4\r
- movl %eax, %cr0\r
- .byte 0xb8 # mov ax, imm16\r
-SavedSs: .space 2\r
- movl %eax, %ss\r
- .byte 0x66, 0xbc # mov esp, imm32\r
-SavedEsp: .space 4\r
- lretl # return to protected mode\r
-\r
-_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
- .word 0x8\r
-_16Idtr: .word 0x3ff\r
- .long 0\r
-_16Gdtr: .word GdtEnd - _NullSegDesc - 1\r
-_16GdtrBase: .long _NullSegDesc\r
-\r
-ASM_PFX(ToUserCode):\r
- movw %ss, %dx\r
- movw %cx, %ss # set new segment selectors\r
- movw %cx, %ds\r
- movw %cx, %es\r
- movw %cx, %fs\r
- movw %cx, %gs\r
- movl %eax, %cr0 # real mode starts at next instruction\r
- # which (per SDM) *must* be a far JMP.\r
- ljmpw $0,$0 # will be filled in by InternalAsmThunk16\r
-L_Base: # to point here.\r
- movl %ebp, %cr4\r
- movw %si, %ss # set up 16-bit stack segment\r
- xchgl %ebx, %esp # set up 16-bit stack pointer\r
-\r
- movw IA32_REGS_SIZE(%esp), %bp # get BackToUserCode address from stack\r
- mov %dx, %cs:(SavedSs - ASM_PFX(BackFromUserCode))(%bp)\r
- mov %ebx, %cs:(SavedEsp - ASM_PFX(BackFromUserCode))(%bp)\r
- lidtl %cs:(_16Idtr - ASM_PFX(BackFromUserCode))(%bp)\r
- popal\r
- pop %ds\r
- pop %es\r
- pop %fs\r
- pop %gs\r
- popfl\r
- lretl # transfer control to user code\r
-\r
-_NullSegDesc: .quad 0\r
-_16CsDesc:\r
- .word -1\r
- .word 0\r
- .byte 0\r
- .byte 0x9b\r
- .byte 0x8f # 16-bit segment, 4GB limit\r
- .byte 0\r
-_16DsDesc:\r
- .word -1\r
- .word 0\r
- .byte 0\r
- .byte 0x93\r
- .byte 0x8f # 16-bit segment, 4GB limit\r
- .byte 0\r
-GdtEnd:\r
-\r
- .code32\r
-#\r
-# @param RegSet The pointer to a IA32_DWORD_REGS structure\r
-# @param Transition The pointer to the transition code\r
-# @return The address of the 16-bit stack after returning from user code\r
-#\r
-ASM_PFX(InternalAsmThunk16):\r
- push %ebp\r
- push %ebx\r
- push %esi\r
- push %edi\r
- push %ds\r
- push %es\r
- push %fs\r
- push %gs\r
- movl 36(%esp), %esi # esi <- RegSet\r
- movzwl _SS(%esi), %edx\r
- mov _ESP(%esi), %edi\r
- add $(-(IA32_REGS_SIZE + 4)), %edi\r
- movl %edi, %ebx # ebx <- stack offset\r
- imul $0x10, %edx, %eax\r
- push $(IA32_REGS_SIZE / 4)\r
- addl %eax, %edi # edi <- linear address of 16-bit stack\r
- pop %ecx\r
- rep\r
- movsl # copy RegSet\r
- movl 40(%esp), %eax # eax <- address of transition code\r
- movl %edx, %esi # esi <- 16-bit stack segment\r
- lea (SavedCr0 - ASM_PFX(m16Start))(%eax), %edx\r
- movl %eax, %ecx\r
- andl $0xf, %ecx\r
- shll $12, %eax\r
- lea (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%ecx), %ecx\r
- movw %cx, %ax\r
- stosl # [edi] <- return address of user code\r
- addl $(L_Base - ASM_PFX(BackFromUserCode)), %eax\r
- movl %eax, (L_Base - SavedCr0 - 4)(%edx)\r
- sgdtl (SavedGdt - SavedCr0)(%edx)\r
- sidtl 0x24(%esp)\r
- movl %cr0, %eax\r
- movl %eax, (%edx) # save CR0 in SavedCr0\r
- andl $0x7ffffffe, %eax # clear PE, PG bits\r
- movl %cr4, %ebp\r
- mov %ebp, (SavedCr4 - SavedCr0)(%edx)\r
- andl $0xffffffcf, %ebp # clear PAE, PSE bits\r
- pushl $0x10\r
- pop %ecx # ecx <- selector for data segments\r
- lgdtl (_16Gdtr - SavedCr0)(%edx)\r
- pushfl\r
- lcall *(_EntryPoint - SavedCr0)(%edx)\r
- popfl\r
- lidtl 0x24(%esp)\r
- lea -IA32_REGS_SIZE(%ebp), %eax\r
- pop %gs\r
- pop %fs\r
- pop %es\r
- pop %ds\r
- pop %edi\r
- pop %esi\r
- pop %ebx\r
- pop %ebp\r
- ret\r
-\r
- .const:\r
-\r
-ASM_PFX(m16Size): .word ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
-ASM_PFX(mThunk16Attr): .word ASM_PFX(ThunkAttr) - ASM_PFX(m16Start)\r
-ASM_PFX(m16Gdt): .word _NullSegDesc - ASM_PFX(m16Start)\r
-ASM_PFX(m16GdtrBase): .word _16GdtrBase - ASM_PFX(m16Start)\r
-ASM_PFX(mTransition): .word _EntryPoint - ASM_PFX(m16Start)\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# CpuId.S\r
-#\r
-# Abstract:\r
-#\r
-# AsmCpuid function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# AsmCpuid (\r
-# IN UINT32 RegisterInEax,\r
-# OUT UINT32 *RegisterOutEax OPTIONAL,\r
-# OUT UINT32 *RegisterOutEbx OPTIONAL,\r
-# OUT UINT32 *RegisterOutEcx OPTIONAL,\r
-# OUT UINT32 *RegisterOutEdx OPTIONAL\r
-# )\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(AsmCpuid)\r
-ASM_PFX(AsmCpuid):\r
- push %rbx\r
- mov %ecx, %eax\r
- push %rax # save Index on stack\r
- push %rdx\r
- cpuid\r
- test %r9, %r9\r
- jz L1\r
- mov %ecx, (%r9)\r
-L1:\r
- pop %rcx\r
- jrcxz L2\r
- mov %eax, (%rcx)\r
-L2:\r
- mov %r8, %rcx\r
- jrcxz L3\r
- mov %ebx, (%rcx)\r
-L3:\r
- mov 0x38(%rsp), %rcx\r
- jrcxz L4\r
- mov %edx, (%rcx)\r
-L4:\r
- pop %rax # restore Index to rax as return value\r
- pop %rbx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# CpuIdEx.S\r
-#\r
-# Abstract:\r
-#\r
-# AsmCpuidEx function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT32\r
-# EFIAPI\r
-# AsmCpuidEx (\r
-# IN UINT32 RegisterInEax,\r
-# IN UINT32 RegisterInEcx,\r
-# OUT UINT32 *RegisterOutEax OPTIONAL,\r
-# OUT UINT32 *RegisterOutEbx OPTIONAL,\r
-# OUT UINT32 *RegisterOutEcx OPTIONAL,\r
-# OUT UINT32 *RegisterOutEdx OPTIONAL\r
-# )\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(AsmCpuidEx)\r
-ASM_PFX(AsmCpuidEx):\r
- push %rbx\r
- movl %ecx,%eax\r
- movl %edx,%ecx\r
- push %rax # save Index on stack\r
- cpuid\r
- mov 0x38(%rsp), %r10\r
- test %r10, %r10\r
- jz L1\r
- mov %ecx,(%r10)\r
-L1:\r
- mov %r8, %rcx\r
- jrcxz L2\r
- movl %eax,(%rcx)\r
-L2:\r
- mov %r9, %rcx\r
- jrcxz L3\r
- mov %ebx, (%rcx)\r
-L3:\r
- mov 0x40(%rsp), %rcx\r
- jrcxz L4\r
- mov %edx, (%rcx)\r
-L4:\r
- pop %rax # restore Index to rax as return value\r
- pop %rbx\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# DisableCache.S\r
-#\r
-# Abstract:\r
-#\r
-# Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
-# WBINVD instruction.\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# AsmDisableCache (\r
-# VOID\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(AsmDisableCache)\r
-ASM_PFX(AsmDisableCache):\r
- movq %cr0, %rax\r
- btsq $30, %rax\r
- btrq $29, %rax\r
- movq %rax, %cr0\r
- wbinvd\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# DisablePaging64.S\r
-#\r
-# Abstract:\r
-#\r
-# AsmDisablePaging64 function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# InternalX86DisablePaging64 (\r
-# IN UINT16 Cs,\r
-# IN UINT32 EntryPoint,\r
-# IN UINT32 Context1, OPTIONAL\r
-# IN UINT32 Context2, OPTIONAL\r
-# IN UINT32 NewStack\r
-# );\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalX86DisablePaging64)\r
-ASM_PFX(InternalX86DisablePaging64):\r
- cli\r
- lea L1(%rip), %rsi # rsi <- The start address of transition code\r
- mov 0x28(%rsp), %edi # rdi <- New stack\r
- lea _mTransitionEnd(%rip), %rax # rax <- end of transition code\r
- sub %rsi, %rax # rax <- The size of transition piece code\r
- add $4, %rax # round rax up to the next 4 byte boundary\r
- and $0xfc, %al\r
- sub %rax, %rdi # rdi <- use stack to hold transition code\r
- mov %edi, %r10d # r10 <- The start address of transicition code below 4G\r
- push %rcx # save rcx to stack\r
- mov %rax, %rcx # rcx <- The size of transition piece code\r
- rep\r
- movsb # copy transition code to (new stack - 64byte) below 4G\r
- pop %rcx # restore rcx\r
-\r
- mov %r8d, %esi\r
- mov %r9d, %edi\r
- mov %r10d, %eax\r
- sub $4, %eax\r
- push %rcx # push Cs to stack\r
- push %r10 # push address of transition code on stack\r
- .byte 0x48, 0xcb # retq: Use far return to load CS register from stack\r
- # (Use raw byte code since some GNU assemblers generates incorrect code for "retq")\r
-L1:\r
- mov %eax,%esp # set up new stack\r
- mov %cr0,%rax\r
- btr $0x1f,%eax # clear CR0.PG\r
- mov %rax,%cr0 # disable paging\r
-\r
- mov %edx,%ebx # save EntryPoint to ebx, for rdmsr will overwrite edx\r
- mov $0xc0000080,%ecx\r
- rdmsr\r
- and $0xfe,%ah # clear LME\r
- wrmsr\r
- mov %cr4,%rax\r
- and $0xdf,%al # clear PAE\r
- mov %rax,%cr4\r
- push %rdi # push Context2\r
- push %rsi # push Context1\r
- callq *%rbx # transfer control to EntryPoint\r
- jmp . # no one should get here\r
-\r
-_mTransitionEnd :\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# EnableCache.S\r
-#\r
-# Abstract:\r
-#\r
-# Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear\r
-# the NW bit of CR0 to 0\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# AsmEnableCache (\r
-# VOID\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(AsmEnableCache)\r
-ASM_PFX(AsmEnableCache):\r
- wbinvd\r
- movq %cr0, %rax\r
- btrq $30, %rax\r
- btrq $29, %rax\r
- movq %rax, %cr0\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# EnableDisableInterrupts.S\r
-#\r
-# Abstract:\r
-#\r
-# EnableDisableInterrupts function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# EnableDisableInterrupts (\r
-# VOID\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(EnableDisableInterrupts)\r
-ASM_PFX(EnableDisableInterrupts):\r
- sti\r
- cli\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# LongJump.S\r
-#\r
-# Abstract:\r
-#\r
-# Implementation of _LongJump() on x64.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# InternalLongJump (\r
-# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
-# IN UINTN Value\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(InternalLongJump)\r
-ASM_PFX(InternalLongJump):\r
- mov (%rcx), %rbx\r
- mov 0x8(%rcx), %rsp\r
- mov 0x10(%rcx), %rbp\r
- mov 0x18(%rcx), %rdi\r
- mov 0x20(%rcx), %rsi\r
- mov 0x28(%rcx), %r12\r
- mov 0x30(%rcx), %r13\r
- mov 0x38(%rcx), %r14\r
- mov 0x40(%rcx), %r15\r
- # load non-volatile fp registers\r
- ldmxcsr 0x50(%rcx)\r
- movdqu 0x58(%rcx), %xmm6\r
- movdqu 0x68(%rcx), %xmm7\r
- movdqu 0x78(%rcx), %xmm8\r
- movdqu 0x88(%rcx), %xmm9\r
- movdqu 0x98(%rcx), %xmm10\r
- movdqu 0xA8(%rcx), %xmm11\r
- movdqu 0xB8(%rcx), %xmm12\r
- movdqu 0xC8(%rcx), %xmm13\r
- movdqu 0xD8(%rcx), %xmm14\r
- movdqu 0xE8(%rcx), %xmm15\r
- mov %rdx, %rax # set return value\r
- jmp *0x48(%rcx)\r
+++ /dev/null
-#------------------------------------------------------------------------------ ;\r
-# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# RdRand.S\r
-#\r
-# Abstract:\r
-#\r
-# Generates random number through CPU RdRand instruction under 64-bit platform.\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-//------------------------------------------------------------------------------\r
-// Generates a 16 bit random number through RDRAND instruction.\r
-// Return TRUE if Rand generated successfully, or FALSE if not.\r
-//\r
-// BOOLEAN EFIAPI InternalX86RdRand16 (UINT16 *Rand);\r
-//------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(InternalX86RdRand16)\r
-ASM_PFX(InternalX86RdRand16):\r
- .byte 0x0f, 0xc7, 0xf0 // rdrand r16: "0f c7 /6 ModRM:r/m(w)"\r
- jc rn16_ok // jmp if CF=1\r
- xor %rax, %rax // reg=0 if CF=0\r
- ret // return with failure status\r
-rn16_ok:\r
- mov %ax, (%rcx)\r
- mov $0x1, %rax\r
- ret\r
-\r
-//------------------------------------------------------------------------------\r
-// Generates a 32 bit random number through RDRAND instruction.\r
-// Return TRUE if Rand generated successfully, or FALSE if not.\r
-//\r
-// BOOLEAN EFIAPI InternalX86RdRand32 (UINT32 *Rand);\r
-//------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(InternalX86RdRand32)\r
-ASM_PFX(InternalX86RdRand32):\r
- .byte 0x0f, 0xc7, 0xf0 // rdrand r32: "0f c7 /6 ModRM:r/m(w)"\r
- jc rn32_ok // jmp if CF=1\r
- xor %rax, %rax // reg=0 if CF=0\r
- ret // return with failure status\r
-rn32_ok:\r
- mov %eax, (%rcx)\r
- mov $0x1, %rax\r
- ret\r
-\r
-//------------------------------------------------------------------------------\r
-// Generates a 64 bit random number through RDRAND instruction.\r
-// Return TRUE if Rand generated successfully, or FALSE if not.\r
-//\r
-// BOOLEAN EFIAPI InternalX86RdRand64 (UINT64 *Rand);\r
-//------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(InternalX86RdRand64)\r
-ASM_PFX(InternalX86RdRand64):\r
- .byte 0x48, 0x0f, 0xc7, 0xf0 // rdrand r64: "REX.W + 0f c7 /6 ModRM:r/m(w)"\r
- jc rn64_ok // jmp if CF=1\r
- xor %rax, %rax // reg=0 if CF=0\r
- ret // return with failure status\r
-rn64_ok:\r
- mov %rax, (%rcx)\r
- mov $0x1, %rax\r
- ret\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# SetJump.S\r
-#\r
-# Abstract:\r
-#\r
-# Implementation of SetJump() on x86_64\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(SetJump)\r
-ASM_PFX(SetJump):\r
- push %rcx\r
- add $0xffffffffffffffe0,%rsp\r
- call ASM_PFX(InternalAssertJumpBuffer)\r
- add $0x20,%rsp\r
- pop %rcx\r
- pop %rdx\r
- mov %rbx,(%rcx)\r
- mov %rsp,0x8(%rcx)\r
- mov %rbp,0x10(%rcx)\r
- mov %rdi,0x18(%rcx)\r
- mov %rsi,0x20(%rcx)\r
- mov %r12,0x28(%rcx)\r
- mov %r13,0x30(%rcx)\r
- mov %r14,0x38(%rcx)\r
- mov %r15,0x40(%rcx)\r
- mov %rdx,0x48(%rcx)\r
- # save non-volatile fp registers\r
- stmxcsr 0x50(%rcx)\r
- movdqu %xmm6, 0x58(%rcx)\r
- movdqu %xmm7, 0x68(%rcx)\r
- movdqu %xmm8, 0x78(%rcx)\r
- movdqu %xmm9, 0x88(%rcx)\r
- movdqu %xmm10, 0x98(%rcx)\r
- movdqu %xmm11, 0xA8(%rcx)\r
- movdqu %xmm12, 0xB8(%rcx)\r
- movdqu %xmm13, 0xC8(%rcx)\r
- movdqu %xmm14, 0xD8(%rcx)\r
- movdqu %xmm15, 0xE8(%rcx)\r
- xor %rax,%rax\r
- jmpq *%rdx\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# SwitchStack.S\r
-#\r
-# Abstract:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-\r
-#------------------------------------------------------------------------------\r
-# Routine Description:\r
-#\r
-# Routine for switching stacks with 2 parameters\r
-#\r
-# Arguments:\r
-#\r
-# (rcx) EntryPoint - Entry point with new stack.\r
-# (rdx) Context1 - Parameter1 for entry point.\r
-# (r8) Context2 - Parameter2 for entry point.\r
-# (r9) NewStack - The pointer to new stack.\r
-#\r
-# Returns:\r
-#\r
-# None\r
-#\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(InternalSwitchStack)\r
-ASM_PFX(InternalSwitchStack):\r
- pushq %rbp\r
- movq %rsp, %rbp\r
-\r
- mov %rcx, %rax // Shift registers for new call\r
- mov %rdx, %rcx\r
- mov %r8, %rdx\r
- #\r
- # Reserve space for register parameters (rcx, rdx, r8 & r9) on the stack,\r
- # in case the callee wishes to spill them.\r
- #\r
- lea -0x20(%r9), %rsp\r
- pushq $0 // stop gdb stack unwind\r
- jmp *%rax // call EntryPoint ()\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-# Thunk16.S\r
-#\r
-# Abstract:\r
-#\r
-# Real mode thunk\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <Library/BaseLib.h>\r
-\r
-ASM_GLOBAL ASM_PFX(m16Start)\r
-ASM_GLOBAL ASM_PFX(m16Size)\r
-ASM_GLOBAL ASM_PFX(mThunk16Attr)\r
-ASM_GLOBAL ASM_PFX(m16Gdt)\r
-ASM_GLOBAL ASM_PFX(m16GdtrBase)\r
-ASM_GLOBAL ASM_PFX(mTransition)\r
-ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
-\r
-# define the structure of IA32_REGS\r
-.set _EDI, 0 #size 4\r
-.set _ESI, 4 #size 4\r
-.set _EBP, 8 #size 4\r
-.set _ESP, 12 #size 4\r
-.set _EBX, 16 #size 4\r
-.set _EDX, 20 #size 4\r
-.set _ECX, 24 #size 4\r
-.set _EAX, 28 #size 4\r
-.set _DS, 32 #size 2\r
-.set _ES, 34 #size 2\r
-.set _FS, 36 #size 2\r
-.set _GS, 38 #size 2\r
-.set _EFLAGS, 40 #size 8\r
-.set _EIP, 48 #size 4\r
-.set _CS, 52 #size 2\r
-.set _SS, 54 #size 2\r
-.set IA32_REGS_SIZE, 56\r
-\r
- .data\r
-\r
-.set Lm16Size, ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
-ASM_PFX(m16Size): .word Lm16Size\r
-.set LmThunk16Attr, L_ThunkAttr - ASM_PFX(m16Start)\r
-ASM_PFX(mThunk16Attr): .word LmThunk16Attr\r
-.set Lm16Gdt, ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r
-ASM_PFX(m16Gdt): .word Lm16Gdt\r
-.set Lm16GdtrBase, _16GdtrBase - ASM_PFX(m16Start)\r
-ASM_PFX(m16GdtrBase): .word Lm16GdtrBase\r
-.set LmTransition, _EntryPoint - ASM_PFX(m16Start)\r
-ASM_PFX(mTransition): .word LmTransition\r
-\r
- .text\r
-\r
-ASM_PFX(m16Start):\r
-\r
-SavedGdt: .space 10\r
-\r
-#------------------------------------------------------------------------------\r
-# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
-# by user code. It will be shadowed to somewhere in memory below 1MB.\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(BackFromUserCode)\r
-ASM_PFX(BackFromUserCode):\r
- #\r
- # The order of saved registers on the stack matches the order they appears\r
- # in IA32_REGS structure. This facilitates wrapper function to extract them\r
- # into that structure.\r
- #\r
- # Some instructions for manipulation of segment registers have to be written\r
- # in opcode since 64-bit MASM prevents accesses to those registers.\r
- #\r
- .byte 0x16 # push ss\r
- .byte 0xe # push cs\r
- .byte 0x66\r
- call L_Base # push eip\r
-L_Base:\r
- .byte 0x66\r
- pushq $0 # reserved high order 32 bits of EFlags\r
- .byte 0x66, 0x9c # pushfd actually\r
- cli # disable interrupts\r
- push %gs\r
- push %fs\r
- .byte 6 # push es\r
- .byte 0x1e # push ds\r
- .byte 0x66,0x60 # pushad\r
- .byte 0x66,0xba # mov edx, imm32\r
-L_ThunkAttr: .space 4\r
- testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
- jz L_1\r
- movl $0x15cd2401,%eax # mov ax, 2401h & int 15h\r
- cli # disable interrupts\r
- jnc L_2\r
-L_1:\r
- testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
- jz L_2\r
- inb $0x92,%al\r
- orb $2,%al\r
- outb %al, $0x92 # deactivate A20M#\r
-L_2:\r
- xorw %ax, %ax # xor eax, eax\r
- movl %ss, %eax # mov ax, ss\r
- lea IA32_REGS_SIZE(%esp), %bp\r
- #\r
- # rsi in the following 2 instructions is indeed bp in 16-bit code\r
- #\r
- movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
- .byte 0x66\r
- movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
- shlw $4,%ax # shl eax, 4\r
- addw %ax,%bp # add ebp, eax\r
- movw %cs,%ax\r
- shlw $4,%ax\r
- lea (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
- .byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax\r
- .word L_64Eip - L_Base\r
- .byte 0x66,0xb8 # mov eax, imm32\r
-L_SavedCr4: .space 4\r
- movq %rax, %cr4\r
- #\r
- # rdi in the instruction below is indeed bx in 16-bit code\r
- #\r
- .byte 0x66,0x2e # 2eh is "cs:" segment override\r
- lgdt (SavedGdt - L_Base)(%rdi)\r
- .byte 0x66\r
- movl $0xc0000080,%ecx\r
- rdmsr\r
- orb $1,%ah\r
- wrmsr\r
- .byte 0x66,0xb8 # mov eax, imm32\r
-L_SavedCr0: .space 4\r
- movq %rax, %cr0\r
- .byte 0x66,0xea # jmp far cs:L_64Bit\r
-L_64Eip: .space 4\r
-L_SavedCs: .space 2\r
-L_64BitCode:\r
- .byte 0x90\r
- .byte 0x48,0xbc # mov rsp, imm64\r
-L_SavedSp: .space 8 # restore stack\r
- nop\r
- ret\r
-\r
-_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
- .word CODE16\r
-_16Gdtr: .word GDT_SIZE - 1\r
-_16GdtrBase: .quad 0\r
-_16Idtr: .word 0x3ff\r
- .long 0\r
-\r
-#------------------------------------------------------------------------------\r
-# _ToUserCode() takes control in real mode before passing control to user code.\r
-# It will be shadowed to somewhere in memory below 1MB.\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(ToUserCode)\r
-ASM_PFX(ToUserCode):\r
- movl %edx,%ss # set new segment selectors\r
- movl %edx,%ds\r
- movl %edx,%es\r
- movl %edx,%fs\r
- movl %edx,%gs\r
- .byte 0x66\r
- movl $0xc0000080,%ecx\r
- movq %rax, %cr0\r
- rdmsr\r
- andb $0xfe, %ah # $0b11111110\r
- wrmsr\r
- movq %rbp, %cr4\r
- movl %esi,%ss # set up 16-bit stack segment\r
- movw %bx,%sp # set up 16-bit stack pointer\r
- .byte 0x66 # make the following call 32-bit\r
- call L_Base1 # push eip\r
-L_Base1:\r
- popw %bp # ebp <- address of L_Base1\r
- pushq (IA32_REGS_SIZE + 2)(%esp)\r
- lea 0x0c(%rsi), %eax\r
- pushq %rax\r
- lret # execution begins at next instruction\r
-L_RealMode:\r
- .byte 0x66,0x2e # CS and operand size override\r
- lidt (_16Idtr - L_Base1)(%rsi)\r
- .byte 0x66,0x61 # popad\r
- .byte 0x1f # pop ds\r
- .byte 0x7 # pop es\r
- .byte 0x0f, 0xa1 # pop fs\r
- .byte 0x0f, 0xa9 # pop gs\r
- .byte 0x66, 0x9d # popfd\r
- leaw 4(%esp),%sp # skip high order 32 bits of EFlags\r
- .byte 0x66 # make the following retf 32-bit\r
- lret # transfer control to user code\r
-\r
-.set CODE16, ASM_PFX(_16Code) - .\r
-.set DATA16, ASM_PFX(_16Data) - .\r
-.set DATA32, ASM_PFX(_32Data) - .\r
-\r
-ASM_PFX(NullSeg): .quad 0\r
-ASM_PFX(_16Code):\r
- .word -1\r
- .word 0\r
- .byte 0\r
- .byte 0x9b\r
- .byte 0x8f # 16-bit segment, 4GB limit\r
- .byte 0\r
-ASM_PFX(_16Data):\r
- .word -1\r
- .word 0\r
- .byte 0\r
- .byte 0x93\r
- .byte 0x8f # 16-bit segment, 4GB limit\r
- .byte 0\r
-ASM_PFX(_32Data):\r
- .word -1\r
- .word 0\r
- .byte 0\r
- .byte 0x93\r
- .byte 0xcf # 16-bit segment, 4GB limit\r
- .byte 0\r
-\r
-.set GDT_SIZE, . - ASM_PFX(NullSeg)\r
-\r
-#------------------------------------------------------------------------------\r
-# IA32_REGISTER_SET *\r
-# EFIAPI\r
-# InternalAsmThunk16 (\r
-# IN IA32_REGISTER_SET *RegisterSet,\r
-# IN OUT VOID *Transition\r
-# );\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
-ASM_PFX(InternalAsmThunk16):\r
- pushq %rbp\r
- pushq %rbx\r
- pushq %rsi\r
- pushq %rdi\r
-\r
- movl %ds, %ebx\r
- pushq %rbx # Save ds segment register on the stack\r
- movl %es, %ebx\r
- pushq %rbx # Save es segment register on the stack\r
- movl %ss, %ebx\r
- pushq %rbx # Save ss segment register on the stack\r
-\r
- .byte 0x0f, 0xa0 #push fs\r
- .byte 0x0f, 0xa8 #push gs\r
- movq %rcx, %rsi\r
- movzwl _SS(%rsi), %r8d\r
- movl _ESP(%rsi), %edi\r
- lea -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
- imul $16, %r8d, %eax\r
- movl %edi,%ebx # ebx <- stack for 16-bit code\r
- pushq $(IA32_REGS_SIZE / 4)\r
- addl %eax,%edi # edi <- linear address of 16-bit stack\r
- popq %rcx\r
- rep\r
- movsl # copy RegSet\r
- lea (L_SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
- movl %edx,%eax # eax <- transition code address\r
- andl $0xf,%edx\r
- shll $12,%eax # segment address in high order 16 bits\r
- .set LBackFromUserCodeDelta, ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start)\r
- lea (LBackFromUserCodeDelta)(%rdx), %ax\r
- stosl # [edi] <- return address of user code\r
- sgdt 0x60(%rsp) # save GDT stack in argument space\r
- movzwq 0x60(%rsp), %r10 # r10 <- GDT limit\r
- lea ((ASM_PFX(InternalAsmThunk16) - L_SavedCr4) + 0xf)(%rcx), %r11\r
- andq $0xfffffffffffffff0, %r11 # r11 <- 16-byte aligned shadowed GDT table in real mode buffer\r
-\r
- movw %r10w, (SavedGdt - L_SavedCr4)(%rcx) # save the limit of shadowed GDT table\r
- movq %r11, (SavedGdt - L_SavedCr4 + 0x2)(%rcx) # save the base address of shadowed GDT table\r
-\r
- movq 0x62(%rsp) ,%rsi # rsi <- the original GDT base address\r
- xchg %r10, %rcx # save rcx to r10 and initialize rcx to be the limit of GDT table\r
- incq %rcx # rcx <- the size of memory to copy\r
- xchg %r11, %rdi # save rdi to r11 and initialize rdi to the base address of shadowed GDT table\r
- rep\r
- movsb # perform memory copy to shadow GDT table\r
- movq %r10, %rcx # restore the orignal rcx before memory copy\r
- movq %r11, %rdi # restore the original rdi before memory copy\r
-\r
- sidt 0x50(%rsp)\r
- movq %cr0, %rax\r
- .set LSavedCrDelta, L_SavedCr0 - L_SavedCr4\r
- movl %eax, (LSavedCrDelta)(%rcx)\r
- andl $0x7ffffffe,%eax # clear PE, PG bits\r
- movq %cr4, %rbp\r
- movl %ebp, (%rcx) # save CR4 in SavedCr4\r
- andl $0xffffffcf,%ebp # clear PAE, PSE bits\r
- movl %r8d, %esi # esi <- 16-bit stack segment\r
- .byte 0x6a, DATA32\r
- popq %rdx\r
- lgdt (_16Gdtr - L_SavedCr4)(%rcx)\r
- movl %edx,%ss\r
- pushfq\r
- lea -8(%rdx), %edx\r
- lea L_RetFromRealMode(%rip), %r8\r
- pushq %r8\r
- movl %cs, %r8d\r
- movw %r8w, (L_SavedCs - L_SavedCr4)(%rcx)\r
- movq %rsp, (L_SavedSp - L_SavedCr4)(%rcx)\r
- .byte 0xff, 0x69 # jmp (_EntryPoint - L_SavedCr4)(%rcx)\r
- .set Ltemp1, _EntryPoint - L_SavedCr4\r
- .byte Ltemp1\r
-L_RetFromRealMode:\r
- popfq\r
- lgdt 0x60(%rsp) # restore protected mode GDTR\r
- lidt 0x50(%rsp) # restore protected mode IDTR\r
- lea -IA32_REGS_SIZE(%rbp), %eax\r
- .byte 0x0f, 0xa9 # pop gs\r
- .byte 0x0f, 0xa1 # pop fs\r
-\r
- popq %rbx\r
- movl %ebx, %ss\r
- popq %rbx\r
- movl %ebx, %es\r
- popq %rbx\r
- movl %ebx, %ds\r
-\r
- popq %rdi\r
- popq %rsi\r
- popq %rbx\r
- popq %rbp\r
-\r
- ret\r
projects / mirror_edk2.git / commitdiff