]> git.proxmox.com Git - mirror_edk2.git/commitdiff
Update PCI bus driver to support non-standard PCI to PCI bridge I/O window alignment...
authorrsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524>
Thu, 24 Dec 2009 11:58:04 +0000 (11:58 +0000)
committerrsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524>
Thu, 24 Dec 2009 11:58:04 +0000 (11:58 +0000)
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9598 6f19259b-4bc3-4df7-8a09-765794883524

MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
MdeModulePkg/MdeModulePkg.dec

index 722f31d03c5c4ea7d5b8bab858fc153c2ebaa1bb..90fdaa3b62b97dc1e94fda4847b2340ad3c374aa 100644 (file)
@@ -268,6 +268,12 @@ struct _PCI_IO_DEVICE {
   UINT32                                    SystemPageSize;\r
   UINT16                                    InitialVFs;\r
   UINT16                                    ReservedBusNum;\r
+  //\r
+  // Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
+  // but some chipsets support non-stardard I/O window aligments less than 4K.\r
+  // This field is used to support this case.\r
+  //\r
+  UINT16                                    BridgeIoAlignment;\r
 };\r
 \r
 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
index cd7865c0b0b700e8091fc1a5dea9b6825c87359c..5d502f68b92150bc698b7ad6491edc7922790060 100644 (file)
   gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciBridgeIoAlignmentProbe\r
 \r
 [FixedPcd.common]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize\r
+\r
 # [Event]\r
 #   ##\r
 #   # Notify event set by CreateEventForHpc () for PCI Hot Plug controller.\r
index bd256cfc8564e334bc338419a6429d59a03397b4..ece3ee830ff02f6049b8d860d5a5795b0445bb71 100644 (file)
@@ -1428,7 +1428,7 @@ PciBridgeResourceAllocator (
   IoBridge = CreateResourceNode (\r
                Bridge,\r
                0,\r
-               0xFFF,\r
+               Bridge->BridgeIoAlignment,\r
                0,\r
                PciBarTypeIo16,\r
                PciResUsageTypical\r
index 8f3ed5eb374d8baa6ce7523b69b871426644ab63..940d8d296108026c5a126b602687f1e6da40f02d 100644 (file)
@@ -469,6 +469,36 @@ GatherPpbInfo (
     }\r
   }\r
 \r
+  //\r
+  // if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes\r
+  // PCI bridge supporting non-stardard I/O window alignment less than 4K.\r
+  //\r
+\r
+  PciIoDevice->BridgeIoAlignment = 0xFFF;\r
+  if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe)) {\r
+    //\r
+    // Check any bits of bit 3-1 of I/O Base Register are writable.\r
+    // if so, it is assumed non-stardard I/O window alignment is supported by this bridge.\r
+    // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.\r
+    //\r
+    Value = Temp ^ (BIT3 | BIT2 | BIT1);\r
+    PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
+    PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
+    PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
+    Value = (Value ^ Temp) & (BIT3 | BIT2 | BIT1);\r
+    switch (Value) {\r
+      case BIT3:\r
+        PciIoDevice->BridgeIoAlignment = 0x7FF;\r
+        break;\r
+      case BIT3 | BIT2:\r
+        PciIoDevice->BridgeIoAlignment = 0x3FF;\r
+        break;\r
+      case BIT3 | BIT2 | BIT1:\r
+        PciIoDevice->BridgeIoAlignment = 0x1FF;\r
+        break;\r
+    }\r
+  }\r
+\r
   Status = BarExisted (\r
             PciIoDevice,\r
             0x24,\r
index f40000672fc63f4a9200676c6951053ab5cac03a..d01a1f8f4b89fb93fe06df5622beebf9d0be9a69 100644 (file)
@@ -236,10 +236,14 @@ PciHostBridgeResourceAllocator (
       // enumerator. Several resource tree was created\r
       //\r
 \r
+      //\r
+      // If non-stardard PCI Bridge I/O window alignment is supported,\r
+      // set I/O aligment to minimum possible alignment for root bridge.\r
+      //\r
       IoBridge = CreateResourceNode (\r
                    RootBridgeDev,\r
                    0,\r
-                   0xFFF,\r
+                   FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF: 0xFFF,\r
                    0,\r
                    PciBarTypeIo16,\r
                    PciResUsageTypical\r
index 2cacd441c8830f40c82711f36f143bde87f6c25c..7fd856e5cae3bec202646f1ea78b24f79a5252f7 100644 (file)
@@ -803,14 +803,12 @@ CreateResourceMap (
       //\r
       // If the device has children, create a bridge resource node for this PPB\r
       // Note: For PPB, memory aperture is aligned with 1MB and IO aperture\r
-      // is aligned with 4KB\r
-      // This device is typically a bridge device like PPB and P2C\r
-      // Note: 0x1000 aligned\r
+      // is aligned with 4KB (smaller alignments may be supported).\r
       //\r
       IoBridge = CreateResourceNode (\r
                    Temp,\r
                    0,\r
-                   0xFFF,\r
+                   Temp->BridgeIoAlignment,\r
                    PPB_IO_RANGE,\r
                    PciBarTypeIo16,\r
                    PciResUsageTypical\r
index 3e25d81eff62d971236f4aa4a32f4258d4bfd391..d8a2d4c34bc00617ecfb41cc8e9307309fa76795 100644 (file)
   ## This PCD specifies whether the Multi Root I/O virtualization support.\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE|BOOLEAN|0x10000046\r
 \r
+  ## This PCD specifies whether the PCI bus driver probes non-standard, \r
+  #  such as 2K/1K/512, granularity for PCI to PCI bridge I/O window.\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciBridgeIoAlignmentProbe|FALSE|BOOLEAN|0x10000047\r
 \r
 [PcdsFeatureFlag.IA32]\r
   ##\r