Per PCI Spec, the option ROM BAR is 32bit so the maximum option ROM
size can be hold by UINT32 type.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
/** @file\r
Header files and data structures needed by PCI Bus module.\r
\r
/** @file\r
Header files and data structures needed by PCI Bus module.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
// The OptionRom Size\r
//\r
//\r
// The OptionRom Size\r
//\r
\r
//\r
// TRUE if all OpROM (in device or in platform specific position) have been processed\r
\r
//\r
// TRUE if all OpROM (in device or in platform specific position) have been processed\r
/** @file\r
Supporting functions implementaion for PCI devices management.\r
\r
/** @file\r
Supporting functions implementaion for PCI devices management.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2018 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
(C) Copyright 2018 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
);\r
if (!EFI_ERROR (Status)) {\r
PciIoDevice->EmbeddedRom = FALSE;\r
);\r
if (!EFI_ERROR (Status)) {\r
PciIoDevice->EmbeddedRom = FALSE;\r
- PciIoDevice->RomSize = PlatformOpRomSize;\r
+ PciIoDevice->RomSize = (UINT32) PlatformOpRomSize;\r
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;\r
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;\r
//\r
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;\r
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;\r
//\r
);\r
if (!EFI_ERROR (Status)) {\r
PciIoDevice->EmbeddedRom = FALSE;\r
);\r
if (!EFI_ERROR (Status)) {\r
PciIoDevice->EmbeddedRom = FALSE;\r
- PciIoDevice->RomSize = PlatformOpRomSize;\r
+ PciIoDevice->RomSize = (UINT32) PlatformOpRomSize;\r
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;\r
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;\r
//\r
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;\r
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;\r
//\r
/** @file\r
PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
\r
/** @file\r
PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
@return Max size of option rom needed.\r
\r
**/\r
@return Max size of option rom needed.\r
\r
**/\r
GetMaxOptionRomSize (\r
IN PCI_IO_DEVICE *Bridge\r
)\r
{\r
LIST_ENTRY *CurrentLink;\r
PCI_IO_DEVICE *Temp;\r
GetMaxOptionRomSize (\r
IN PCI_IO_DEVICE *Bridge\r
)\r
{\r
LIST_ENTRY *CurrentLink;\r
PCI_IO_DEVICE *Temp;\r
- UINT64 MaxOptionRomSize;\r
- UINT64 TempOptionRomSize;\r
+ UINT32 MaxOptionRomSize;\r
+ UINT32 TempOptionRomSize;\r
\r
MaxOptionRomSize = 0;\r
\r
\r
MaxOptionRomSize = 0;\r
\r
/** @file\r
PCI bus enumeration logic function declaration for PCI bus module.\r
\r
/** @file\r
PCI bus enumeration logic function declaration for PCI bus module.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@return Max size of option rom needed.\r
\r
**/\r
@return Max size of option rom needed.\r
\r
**/\r
GetMaxOptionRomSize (\r
IN PCI_IO_DEVICE *Bridge\r
);\r
GetMaxOptionRomSize (\r
IN PCI_IO_DEVICE *Bridge\r
);\r
/** @file\r
Internal library implementation for PCI Bus module.\r
\r
/** @file\r
Internal library implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
UINT64 PMem32ResStatus;\r
UINT64 Mem64ResStatus;\r
UINT64 PMem64ResStatus;\r
UINT64 PMem32ResStatus;\r
UINT64 Mem64ResStatus;\r
UINT64 PMem64ResStatus;\r
- UINT64 MaxOptionRomSize;\r
+ UINT32 MaxOptionRomSize;\r
PCI_RESOURCE_NODE *IoBridge;\r
PCI_RESOURCE_NODE *Mem32Bridge;\r
PCI_RESOURCE_NODE *PMem32Bridge;\r
PCI_RESOURCE_NODE *IoBridge;\r
PCI_RESOURCE_NODE *Mem32Bridge;\r
PCI_RESOURCE_NODE *PMem32Bridge;\r