--- /dev/null
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ExceptionHandlersStart)
+GCC_ASM_EXPORT(ExceptionHandlersEnd)
+GCC_ASM_EXPORT(CommonExceptionEntry)
+GCC_ASM_EXPORT(AsmCommonExceptionEntry)
+GCC_ASM_EXPORT(CommonCExceptionHandler)
+
+ASM_PFX(ExceptionHandlersStart):
+
+ASM_PFX(Reset):
+ b ASM_PFX(ResetEntry)
+
+ASM_PFX(UndefinedInstruction):
+ b ASM_PFX(UndefinedInstructionEntry)
+
+ASM_PFX(SoftwareInterrupt):
+ b ASM_PFX(SoftwareInterruptEntry)
+
+ASM_PFX(PrefetchAbort):
+ b ASM_PFX(PrefetchAbortEntry)
+
+ASM_PFX(DataAbort):
+ b ASM_PFX(DataAbortEntry)
+
+ASM_PFX(ReservedException):
+ b ASM_PFX(ReservedExceptionEntry)
+
+ASM_PFX(Irq):
+ b ASM_PFX(IrqEntry)
+
+ASM_PFX(Fiq):
+ b ASM_PFX(FiqEntry)
+
+ASM_PFX(ResetEntry):
+ srsdb #0x13! @ Store return state on SVC stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov R0,#0
+ ldr R1,ASM_PFX(CommonExceptionEntry)
+ bx R1
+
+ASM_PFX(UndefinedInstructionEntry):
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov r0,#1
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(SoftwareInterruptEntry):
+ srsdb #0x13! @ Store return state on SVC stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov r0,#2
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(PrefetchAbortEntry):
+ sub LR,LR,#4
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov r0,#3
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(DataAbortEntry):
+ sub LR,LR,#8
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov r0,#4
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(ReservedExceptionEntry):
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov r0,#5
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(IrqEntry):
+ sub LR,LR,#4
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov r0,#6
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(FiqEntry):
+ sub LR,LR,#4
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov r0,#7
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(CommonExceptionEntry):
+ .byte 0x12
+ .byte 0x34
+ .byte 0x56
+ .byte 0x78
+
+ASM_PFX(ExceptionHandlersEnd):
+
+ASM_PFX(AsmCommonExceptionEntry):
+ mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
+ str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
+
+ mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
+ str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
+
+ mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
+ str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
+
+ mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
+ str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
+
+ ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
+ str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
+ and r1, r1, #0x1f @ Check to see if User or System Mode
+ cmp r1, #0x1f
+ cmpne r1, #0x10
+ add R2, SP, #0x38 @ Store it in EFI_SYSTEM_CONTEXT_ARM.LR
+ ldmneed r2, {lr}^ @ User or System mode, use unbanked register
+ ldmneed r2, {lr} @ All other modes used banked register
+
+ ldr R1, [SP, #0x58] @ PC is the LR pushed by srsdb
+ str R1, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
+
+ sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
+ str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
+
+ @ R0 is exception type
+ mov R1,SP @ Prepare System Context pointer as an argument for the exception handler
+ blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
+
+ ldr R2,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
+ str R2,[SP,#0x5c] @ Store it back to srsdb stack slot so it can be restored
+
+ ldr R2,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
+ str R2,[SP,#0x58] @ Store it back to srsdb stack slot so it can be restored
+
+ ldmfd SP!,{R0-R12} @ Restore general purpose registers
+ @ Exception handler can not change SP or LR as we would blow chunks
+
+ add SP,SP,#0x20 @ Clear out the remaining stack space
+ ldmfd SP!,{LR} @ restore the link register for this context
+ rfefd SP! @ return from exception via srsdb stack slot
--- /dev/null
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+ EXPORT ExceptionHandlersStart
+ EXPORT ExceptionHandlersEnd
+ EXPORT CommonExceptionEntry
+ EXPORT AsmCommonExceptionEntry
+ IMPORT CommonCExceptionHandler
+
+ PRESERVE8
+ AREA DxeExceptionHandlers, CODE, READONLY
+
+ExceptionHandlersStart
+
+Reset
+ b ResetEntry
+
+UndefinedInstruction
+ b UndefinedInstructionEntry
+
+SoftwareInterrupt
+ b SoftwareInterruptEntry
+
+PrefetchAbort
+ b PrefetchAbortEntry
+
+DataAbort
+ b DataAbortEntry
+
+ReservedException
+ b ReservedExceptionEntry
+
+Irq
+ b IrqEntry
+
+Fiq
+ b FiqEntry
+
+ResetEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#0
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+UndefinedInstructionEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#1
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+SoftwareInterruptEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#2
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+PrefetchAbortEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#3
+ SUB LR,LR,#4
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+DataAbortEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#4
+ SUB LR,LR,#8
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+ReservedExceptionEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#5
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+IrqEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#6
+ SUB LR,LR,#4
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+FiqEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#7
+ SUB LR,LR,#4
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+CommonExceptionEntry
+ dcd 0x12345678
+
+ExceptionHandlersEnd
+
+AsmCommonExceptionEntry
+ mrc p15, 0, r1, c6, c0, 2 ; Read IFAR
+ stmfd SP!,{R1} ; Store the IFAR
+
+ mrc p15, 0, r1, c5, c0, 1 ; Read IFSR
+ stmfd SP!,{R1} ; Store the IFSR
+
+ mrc p15, 0, r1, c6, c0, 0 ; Read DFAR
+ stmfd SP!,{R1} ; Store the DFAR
+
+ mrc p15, 0, r1, c5, c0, 0 ; Read DFSR
+ stmfd SP!,{R1} ; Store the DFSR
+
+ mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)
+ stmfd SP!,{R1} ; Store the SPSR
+
+ stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)
+ stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register
+ nop ; Required by ARM architecture
+ SUB SP,SP,#0x08 ; Adjust stack pointer
+ stmfd SP!,{R2-R12} ; Store general purpose registers
+
+ ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)
+ ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)
+ stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1
+
+ mov R1,SP ; Prepare System Context pointer as an argument for the exception handler
+
+ sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment
+ blx CommonCExceptionHandler ; Call exception handler
+ add SP,SP,#4 ; Adjust SP back to where we were
+
+ ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed
+ MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler
+
+ ldmfd SP!,{R0-R12} ; Restore general purpose registers
+ ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register
+ nop ; Required by ARM architecture
+ add SP,SP,#0x08 ; Adjust stack pointer
+ ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)
+ add SP,SP,#0x1C ; Clear out the remaining stack space
+ movs PC,LR ; Return from exception
+
+ END
+
+
--- /dev/null
+#------------------------------------------------------------------------------
+#
+# Use ARMv6 instruction to operate on a single stack
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#include <Library/PcdLib.h>
+
+/*
+
+This is the stack constructed by the exception handler (low address to high address)
+ # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
+ Reg Offset
+ === ======
+ R0 0x00 # stmfd SP!,{R0-R12}
+ R1 0x04
+ R2 0x08
+ R3 0x0c
+ R4 0x10
+ R5 0x14
+ R6 0x18
+ R7 0x1c
+ R8 0x20
+ R9 0x24
+ R10 0x28
+ R11 0x2c
+ R12 0x30
+ SP 0x34 # reserved via adding 0x20 (32) to the SP
+ LR 0x38
+ PC 0x3c
+ CPSR 0x40
+ DFSR 0x44
+ DFAR 0x48
+ IFSR 0x4c
+ IFAR 0x50
+
+ LR 0x54 # SVC Link register (we need to restore it)
+
+ LR 0x58 # pushed by srsfd
+ CPSR 0x5c
+
+ */
+
+
+GCC_ASM_EXPORT(ExceptionHandlersStart)
+GCC_ASM_EXPORT(ExceptionHandlersEnd)
+GCC_ASM_EXPORT(CommonExceptionEntry)
+GCC_ASM_EXPORT(AsmCommonExceptionEntry)
+GCC_ASM_EXPORT(CommonCExceptionHandler)
+
+.text
+#if !defined(__APPLE__)
+.fpu neon @ makes vpush/vpop assemble
+#endif
+.align 5
+
+
+//
+// This code gets copied to the ARM vector table
+// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
+//
+ASM_PFX(ExceptionHandlersStart):
+
+ASM_PFX(Reset):
+ b ASM_PFX(ResetEntry)
+
+ASM_PFX(UndefinedInstruction):
+ b ASM_PFX(UndefinedInstructionEntry)
+
+ASM_PFX(SoftwareInterrupt):
+ b ASM_PFX(SoftwareInterruptEntry)
+
+ASM_PFX(PrefetchAbort):
+ b ASM_PFX(PrefetchAbortEntry)
+
+ASM_PFX(DataAbort):
+ b ASM_PFX(DataAbortEntry)
+
+ASM_PFX(ReservedException):
+ b ASM_PFX(ReservedExceptionEntry)
+
+ASM_PFX(Irq):
+ b ASM_PFX(IrqEntry)
+
+ASM_PFX(Fiq):
+ b ASM_PFX(FiqEntry)
+
+ASM_PFX(ResetEntry):
+ srsdb #0x13! @ Store return state on SVC stack
+ @ We are already in SVC mode
+
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov R0,#0 @ ExceptionType
+ ldr R1,ASM_PFX(CommonExceptionEntry)
+ bx R1
+
+ASM_PFX(UndefinedInstructionEntry):
+ sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov R0,#1 @ ExceptionType
+ ldr R1,ASM_PFX(CommonExceptionEntry)
+ bx R1
+
+ASM_PFX(SoftwareInterruptEntry):
+ sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
+ srsdb #0x13! @ Store return state on SVC stack
+ @ We are already in SVC mode
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov R0,#2 @ ExceptionType
+ ldr R1,ASM_PFX(CommonExceptionEntry)
+ bx R1
+
+ASM_PFX(PrefetchAbortEntry):
+ sub LR,LR,#4
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov R0,#3 @ ExceptionType
+ ldr R1,ASM_PFX(CommonExceptionEntry)
+ bx R1
+
+ASM_PFX(DataAbortEntry):
+ sub LR,LR,#8
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov R0,#4
+ ldr R1,ASM_PFX(CommonExceptionEntry)
+ bx R1
+
+ASM_PFX(ReservedExceptionEntry):
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov R0,#5
+ ldr R1,ASM_PFX(CommonExceptionEntry)
+ bx R1
+
+ASM_PFX(IrqEntry):
+ sub LR,LR,#4
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+
+ mov R0,#6 @ ExceptionType
+ ldr R1,ASM_PFX(CommonExceptionEntry)
+ bx R1
+
+ASM_PFX(FiqEntry):
+ sub LR,LR,#4
+ srsdb #0x13! @ Store return state on SVC stack
+ cps #0x13 @ Switch to SVC for common stack
+ stmfd SP!,{LR} @ Store the link register for the current mode
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} @ Store the register state
+ @ Since we have already switch to SVC R8_fiq - R12_fiq
+ @ never get used or saved
+ mov R0,#7 @ ExceptionType
+ ldr R1,ASM_PFX(CommonExceptionEntry)
+ bx R1
+
+//
+// This gets patched by the C code that patches in the vector table
+//
+ASM_PFX(CommonExceptionEntry):
+ .word ASM_PFX(AsmCommonExceptionEntry)
+
+ASM_PFX(ExceptionHandlersEnd):
+
+//
+// This code runs from CpuDxe driver loaded address. It is patched into
+// CommonExceptionEntry.
+//
+ASM_PFX(AsmCommonExceptionEntry):
+ mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
+ str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
+
+ mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
+ str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
+
+ mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
+ str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
+
+ mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
+ str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
+
+ ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
+ str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
+
+ add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
+ and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
+ cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))
+ cmpne R3, #0x10 @
+ stmeqed R2, {lr}^ @ save unbanked lr
+ @ else
+ stmneed R2, {lr} @ save SVC lr
+
+
+ ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
+ @ Check to see if we have to adjust for Thumb entry
+ sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {
+ cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
+ bhi NoAdjustNeeded
+
+ tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
+ addne R5, R5, #2 @ PC += 2@
+ str R5,[SP,#0x58] @ Update LR value pused by srsfd
+
+NoAdjustNeeded:
+
+ str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
+
+ sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
+ str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
+
+ @ R0 is ExceptionType
+ mov R1,SP @ R1 is SystemContext
+
+#if (FixedPcdGet32(PcdVFPEnabled))
+ vpush {d0-d15} @ save vstm registers in case they are used in optimizations
+#endif
+
+/*
+VOID
+EFIAPI
+CommonCExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType, R0
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
+ )
+
+*/
+ blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
+
+#if (FixedPcdGet32(PcdVFPEnabled))
+ vpop {d0-d15}
+#endif
+
+ ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
+ mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
+
+ ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
+ mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
+
+ ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
+ str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
+
+ ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
+ str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
+
+ add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
+ add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
+ and R1, R1, #0x1f @ Check to see if User or System Mode
+ cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
+ cmpne R1, #0x10 @
+ ldmeqed R2, {lr}^ @ restore unbanked lr
+ @ else
+ ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
+
+ ldmfd SP!,{R0-R12} @ Restore general purpose registers
+ @ Exception handler can not change SP
+
+ add SP,SP,#0x20 @ Clear out the remaining stack space
+ ldmfd SP!,{LR} @ restore the link register for this context
+ rfefd SP! @ return from exception via srsfd stack slot
+
--- /dev/null
+//------------------------------------------------------------------------------ \r
+//\r
+// Use ARMv6 instruction to operate on a single stack\r
+//\r
+// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+#include <Library/PcdLib.h>\r
+\r
+/*\r
+\r
+This is the stack constructed by the exception handler (low address to high address)\r
+ # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM\r
+ Reg Offset\r
+ === ====== \r
+ R0 0x00 # stmfd SP!,{R0-R12}\r
+ R1 0x04\r
+ R2 0x08\r
+ R3 0x0c\r
+ R4 0x10\r
+ R5 0x14\r
+ R6 0x18\r
+ R7 0x1c\r
+ R8 0x20\r
+ R9 0x24\r
+ R10 0x28\r
+ R11 0x2c\r
+ R12 0x30\r
+ SP 0x34 # reserved via adding 0x20 (32) to the SP\r
+ LR 0x38\r
+ PC 0x3c\r
+ CPSR 0x40\r
+ DFSR 0x44\r
+ DFAR 0x48\r
+ IFSR 0x4c\r
+ IFAR 0x50\r
+ \r
+ LR 0x54 # SVC Link register (we need to restore it)\r
+ \r
+ LR 0x58 # pushed by srsfd \r
+ CPSR 0x5c \r
+\r
+ */\r
+ \r
+ \r
+ EXPORT ExceptionHandlersStart\r
+ EXPORT ExceptionHandlersEnd\r
+ EXPORT CommonExceptionEntry\r
+ EXPORT AsmCommonExceptionEntry\r
+ IMPORT CommonCExceptionHandler\r
+\r
+ PRESERVE8\r
+ AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5\r
+ \r
+//\r
+// This code gets copied to the ARM vector table\r
+// ExceptionHandlersStart - ExceptionHandlersEnd gets copied\r
+//\r
+ExceptionHandlersStart\r
+\r
+Reset\r
+ b ResetEntry\r
+\r
+UndefinedInstruction\r
+ b UndefinedInstructionEntry\r
+\r
+SoftwareInterrupt\r
+ b SoftwareInterruptEntry\r
+\r
+PrefetchAbort\r
+ b PrefetchAbortEntry\r
+\r
+DataAbort\r
+ b DataAbortEntry\r
+\r
+ReservedException\r
+ b ReservedExceptionEntry\r
+\r
+Irq\r
+ b IrqEntry\r
+\r
+Fiq\r
+ b FiqEntry\r
+\r
+ResetEntry\r
+ srsfd #0x13! ; Store return state on SVC stack\r
+ ; We are already in SVC mode\r
+ stmfd SP!,{LR} ; Store the link register for the current mode\r
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} ; Store the register state\r
+ \r
+ mov R0,#0 ; ExceptionType\r
+ ldr R1,CommonExceptionEntry\r
+ bx R1\r
+\r
+UndefinedInstructionEntry\r
+ sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry\r
+ srsfd #0x13! ; Store return state on SVC stack\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ stmfd SP!,{LR} ; Store the link register for the current mode\r
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} ; Store the register state\r
+\r
+ mov R0,#1 ; ExceptionType\r
+ ldr R1,CommonExceptionEntry; \r
+ bx R1\r
+\r
+SoftwareInterruptEntry\r
+ sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry\r
+ srsfd #0x13! ; Store return state on SVC stack\r
+ ; We are already in SVC mode\r
+ stmfd SP!,{LR} ; Store the link register for the current mode\r
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} ; Store the register state\r
+\r
+ mov R0,#2 ; ExceptionType\r
+ ldr R1,CommonExceptionEntry\r
+ bx R1\r
+\r
+PrefetchAbortEntry\r
+ sub LR,LR,#4\r
+ srsfd #0x13! ; Store return state on SVC stack\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ stmfd SP!,{LR} ; Store the link register for the current mode\r
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} ; Store the register state\r
+\r
+ mov R0,#3 ; ExceptionType\r
+ ldr R1,CommonExceptionEntry\r
+ bx R1\r
+\r
+DataAbortEntry\r
+ sub LR,LR,#8\r
+ srsfd #0x13! ; Store return state on SVC stack\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ stmfd SP!,{LR} ; Store the link register for the current mode\r
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} ; Store the register state\r
+\r
+ mov R0,#4 ; ExceptionType\r
+ ldr R1,CommonExceptionEntry\r
+ bx R1\r
+\r
+ReservedExceptionEntry\r
+ srsfd #0x13! ; Store return state on SVC stack\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ stmfd SP!,{LR} ; Store the link register for the current mode\r
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} ; Store the register state\r
+\r
+ mov R0,#5 ; ExceptionType\r
+ ldr R1,CommonExceptionEntry\r
+ bx R1\r
+\r
+IrqEntry\r
+ sub LR,LR,#4\r
+ srsfd #0x13! ; Store return state on SVC stack\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ stmfd SP!,{LR} ; Store the link register for the current mode\r
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} ; Store the register state\r
+\r
+ mov R0,#6 ; ExceptionType\r
+ ldr R1,CommonExceptionEntry\r
+ bx R1\r
+\r
+FiqEntry\r
+ sub LR,LR,#4\r
+ srsfd #0x13! ; Store return state on SVC stack\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ stmfd SP!,{LR} ; Store the link register for the current mode\r
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} ; Store the register state\r
+ ; Since we have already switch to SVC R8_fiq - R12_fiq\r
+ ; never get used or saved\r
+ mov R0,#7 ; ExceptionType\r
+ ldr R1,CommonExceptionEntry\r
+ bx R1\r
+\r
+//\r
+// This gets patched by the C code that patches in the vector table\r
+//\r
+CommonExceptionEntry\r
+ dcd AsmCommonExceptionEntry\r
+\r
+ExceptionHandlersEnd\r
+\r
+//\r
+// This code runs from CpuDxe driver loaded address. It is patched into \r
+// CommonExceptionEntry.\r
+//\r
+AsmCommonExceptionEntry\r
+ mrc p15, 0, R1, c6, c0, 2 ; Read IFAR\r
+ str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR \r
+ \r
+ mrc p15, 0, R1, c5, c0, 1 ; Read IFSR\r
+ str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r
+ \r
+ mrc p15, 0, R1, c6, c0, 0 ; Read DFAR\r
+ str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r
+ \r
+ mrc p15, 0, R1, c5, c0, 0 ; Read DFSR\r
+ str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r
+ \r
+ ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack \r
+ str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r
+\r
+ add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
+ and R3, R1, #0x1f ; Check CPSR to see if User or System Mode\r
+ cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1df))\r
+ cmpne R3, #0x10 ; \r
+ stmeqed R2, {lr}^ ; save unbanked lr\r
+ ; else \r
+ stmneed R2, {lr} ; save SVC lr\r
+\r
+\r
+ ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd \r
+ ; Check to see if we have to adjust for Thumb entry\r
+ sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType ==2)) {\r
+ cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb \r
+ bhi NoAdjustNeeded\r
+ \r
+ tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry \r
+ addne R5, R5, #2 ; PC += 2;\r
+ str R5,[SP,#0x58] ; Update LR value pused by srsfd \r
+ \r
+NoAdjustNeeded\r
+\r
+ str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r
+ \r
+ sub R1, SP, #0x60 ; We pused 0x60 bytes on the stack \r
+ str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r
+ \r
+ ; R0 is ExceptionType \r
+ mov R1,SP ; R1 is SystemContext \r
+\r
+#if (FixedPcdGet32(PcdVFPEnabled))\r
+ vpush {d0-d15} ; save vstm registers in case they are used in optimizations\r
+#endif\r
+\r
+/* \r
+VOID\r
+EFIAPI\r
+CommonCExceptionHandler (\r
+ IN EFI_EXCEPTION_TYPE ExceptionType, R0\r
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext R1\r
+ )\r
+\r
+*/\r
+ blx CommonCExceptionHandler ; Call exception handler\r
+\r
+#if (FixedPcdGet32(PcdVFPEnabled))\r
+ vpop {d0-d15}\r
+#endif\r
+ \r
+ ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR\r
+ mcr p15, 0, R1, c5, c0, 1 ; Write IFSR\r
+\r
+ ldr R1, [SP, #0x44] ; sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR\r
+ mcr p15, 0, R1, c5, c0, 0 ; Write DFSR\r
+ \r
+ ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC\r
+ str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored \r
+\r
+ ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR\r
+ str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored \r
+ \r
+ add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry\r
+ add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
+ and R1, R1, #0x1f ; Check to see if User or System Mode\r
+ cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))\r
+ cmpne R1, #0x10 ; \r
+ ldmeqed R2, {lr}^ ; restore unbanked lr\r
+ ; else\r
+ ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}\r
+ \r
+ ldmfd SP!,{R0-R12} ; Restore general purpose registers\r
+ ; Exception handler can not change SP\r
+ \r
+ add SP,SP,#0x20 ; Clear out the remaining stack space\r
+ ldmfd SP!,{LR} ; restore the link register for this context\r
+ rfefd SP! ; return from exception via srsfd stack slot\r
+ \r
+ END\r
+\r
+\r
# DXE CPU driver\r
# \r
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
ENTRY_POINT = CpuDxeInitialize\r
\r
-[Sources.ARM]\r
+[Sources.Common]\r
CpuDxe.c\r
CpuDxe.h\r
CpuMpCore.c\r
- Exception.c\r
\r
#\r
# Prior to ARMv6 we have multiple stacks, one per mode\r
#\r
-# ExceptionSupport.asm | RVCT\r
-# ExceptionSupport.S | GCC\r
+# ArmV4/ExceptionSupport.asm | RVCT\r
+# ArmV4/ExceptionSupport.S | GCC\r
\r
#\r
# ARMv6 or later uses a single stack via srs/stm instructions\r
#\r
- ExceptionSupport.ARMv6.asm | RVCT\r
- ExceptionSupport.ARMv6.S | GCC\r
- Mmu.c \r
+\r
+[Sources.ARM]\r
+ Mmu.c\r
+ Exception.c\r
+ ArmV6/ExceptionSupport.asm | RVCT\r
+ ArmV6/ExceptionSupport.S | GCC\r
\r
\r
[Packages]\r
+++ /dev/null
-#------------------------------------------------------------------------------
-#
-# Use ARMv6 instruction to operate on a single stack
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <Library/PcdLib.h>
-
-/*
-
-This is the stack constructed by the exception handler (low address to high address)
- # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
- Reg Offset
- === ======
- R0 0x00 # stmfd SP!,{R0-R12}
- R1 0x04
- R2 0x08
- R3 0x0c
- R4 0x10
- R5 0x14
- R6 0x18
- R7 0x1c
- R8 0x20
- R9 0x24
- R10 0x28
- R11 0x2c
- R12 0x30
- SP 0x34 # reserved via adding 0x20 (32) to the SP
- LR 0x38
- PC 0x3c
- CPSR 0x40
- DFSR 0x44
- DFAR 0x48
- IFSR 0x4c
- IFAR 0x50
-
- LR 0x54 # SVC Link register (we need to restore it)
-
- LR 0x58 # pushed by srsfd
- CPSR 0x5c
-
- */
-
-
-GCC_ASM_EXPORT(ExceptionHandlersStart)
-GCC_ASM_EXPORT(ExceptionHandlersEnd)
-GCC_ASM_EXPORT(CommonExceptionEntry)
-GCC_ASM_EXPORT(AsmCommonExceptionEntry)
-GCC_ASM_EXPORT(CommonCExceptionHandler)
-
-.text
-#if !defined(__APPLE__)
-.fpu neon @ makes vpush/vpop assemble
-#endif
-.align 5
-
-
-//
-// This code gets copied to the ARM vector table
-// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
-//
-ASM_PFX(ExceptionHandlersStart):
-
-ASM_PFX(Reset):
- b ASM_PFX(ResetEntry)
-
-ASM_PFX(UndefinedInstruction):
- b ASM_PFX(UndefinedInstructionEntry)
-
-ASM_PFX(SoftwareInterrupt):
- b ASM_PFX(SoftwareInterruptEntry)
-
-ASM_PFX(PrefetchAbort):
- b ASM_PFX(PrefetchAbortEntry)
-
-ASM_PFX(DataAbort):
- b ASM_PFX(DataAbortEntry)
-
-ASM_PFX(ReservedException):
- b ASM_PFX(ReservedExceptionEntry)
-
-ASM_PFX(Irq):
- b ASM_PFX(IrqEntry)
-
-ASM_PFX(Fiq):
- b ASM_PFX(FiqEntry)
-
-ASM_PFX(ResetEntry):
- srsdb #0x13! @ Store return state on SVC stack
- @ We are already in SVC mode
-
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#0 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(UndefinedInstructionEntry):
- sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#1 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(SoftwareInterruptEntry):
- sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
- srsdb #0x13! @ Store return state on SVC stack
- @ We are already in SVC mode
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#2 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(PrefetchAbortEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#3 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(DataAbortEntry):
- sub LR,LR,#8
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#4
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(ReservedExceptionEntry):
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#5
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(IrqEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#6 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(FiqEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
- @ Since we have already switch to SVC R8_fiq - R12_fiq
- @ never get used or saved
- mov R0,#7 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-//
-// This gets patched by the C code that patches in the vector table
-//
-ASM_PFX(CommonExceptionEntry):
- .word ASM_PFX(AsmCommonExceptionEntry)
-
-ASM_PFX(ExceptionHandlersEnd):
-
-//
-// This code runs from CpuDxe driver loaded address. It is patched into
-// CommonExceptionEntry.
-//
-ASM_PFX(AsmCommonExceptionEntry):
- mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
- str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
-
- mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
- str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
-
- mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
- str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
-
- mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
- str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
-
- ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
- str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
-
- add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
- and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
- cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))
- cmpne R3, #0x10 @
- stmeqed R2, {lr}^ @ save unbanked lr
- @ else
- stmneed R2, {lr} @ save SVC lr
-
-
- ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
- @ Check to see if we have to adjust for Thumb entry
- sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {
- cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
- bhi NoAdjustNeeded
-
- tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
- addne R5, R5, #2 @ PC += 2@
- str R5,[SP,#0x58] @ Update LR value pused by srsfd
-
-NoAdjustNeeded:
-
- str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
-
- sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
- str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
-
- @ R0 is ExceptionType
- mov R1,SP @ R1 is SystemContext
-
-#if (FixedPcdGet32(PcdVFPEnabled))
- vpush {d0-d15} @ save vstm registers in case they are used in optimizations
-#endif
-
-/*
-VOID
-EFIAPI
-CommonCExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType, R0
- IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
- )
-
-*/
- blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
-
-#if (FixedPcdGet32(PcdVFPEnabled))
- vpop {d0-d15}
-#endif
-
- ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
- mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
-
- ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
- mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
-
- ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
- str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
-
- ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
- str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
-
- add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
- add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
- and R1, R1, #0x1f @ Check to see if User or System Mode
- cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
- cmpne R1, #0x10 @
- ldmeqed R2, {lr}^ @ restore unbanked lr
- @ else
- ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
-
- ldmfd SP!,{R0-R12} @ Restore general purpose registers
- @ Exception handler can not change SP
-
- add SP,SP,#0x20 @ Clear out the remaining stack space
- ldmfd SP!,{LR} @ restore the link register for this context
- rfefd SP! @ return from exception via srsfd stack slot
-
+++ /dev/null
-//------------------------------------------------------------------------------ \r
-//\r
-// Use ARMv6 instruction to operate on a single stack\r
-//\r
-// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-#include <Library/PcdLib.h>\r
-\r
-/*\r
-\r
-This is the stack constructed by the exception handler (low address to high address)\r
- # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM\r
- Reg Offset\r
- === ====== \r
- R0 0x00 # stmfd SP!,{R0-R12}\r
- R1 0x04\r
- R2 0x08\r
- R3 0x0c\r
- R4 0x10\r
- R5 0x14\r
- R6 0x18\r
- R7 0x1c\r
- R8 0x20\r
- R9 0x24\r
- R10 0x28\r
- R11 0x2c\r
- R12 0x30\r
- SP 0x34 # reserved via adding 0x20 (32) to the SP\r
- LR 0x38\r
- PC 0x3c\r
- CPSR 0x40\r
- DFSR 0x44\r
- DFAR 0x48\r
- IFSR 0x4c\r
- IFAR 0x50\r
- \r
- LR 0x54 # SVC Link register (we need to restore it)\r
- \r
- LR 0x58 # pushed by srsfd \r
- CPSR 0x5c \r
-\r
- */\r
- \r
- \r
- EXPORT ExceptionHandlersStart\r
- EXPORT ExceptionHandlersEnd\r
- EXPORT CommonExceptionEntry\r
- EXPORT AsmCommonExceptionEntry\r
- IMPORT CommonCExceptionHandler\r
-\r
- PRESERVE8\r
- AREA DxeExceptionHandlers, CODE, READONLY\r
- \r
- ALIGN 32\r
- \r
-//\r
-// This code gets copied to the ARM vector table\r
-// ExceptionHandlersStart - ExceptionHandlersEnd gets copied\r
-//\r
-ExceptionHandlersStart\r
-\r
-Reset\r
- b ResetEntry\r
-\r
-UndefinedInstruction\r
- b UndefinedInstructionEntry\r
-\r
-SoftwareInterrupt\r
- b SoftwareInterruptEntry\r
-\r
-PrefetchAbort\r
- b PrefetchAbortEntry\r
-\r
-DataAbort\r
- b DataAbortEntry\r
-\r
-ReservedException\r
- b ReservedExceptionEntry\r
-\r
-Irq\r
- b IrqEntry\r
-\r
-Fiq\r
- b FiqEntry\r
-\r
-ResetEntry\r
- srsfd #0x13! ; Store return state on SVC stack\r
- ; We are already in SVC mode\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
- \r
- mov R0,#0 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-UndefinedInstructionEntry\r
- sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#1 ; ExceptionType\r
- ldr R1,CommonExceptionEntry; \r
- bx R1\r
-\r
-SoftwareInterruptEntry\r
- sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry\r
- srsfd #0x13! ; Store return state on SVC stack\r
- ; We are already in SVC mode\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#2 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-PrefetchAbortEntry\r
- sub LR,LR,#4\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#3 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-DataAbortEntry\r
- sub LR,LR,#8\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#4 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-ReservedExceptionEntry\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#5 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-IrqEntry\r
- sub LR,LR,#4\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#6 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-FiqEntry\r
- sub LR,LR,#4\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
- ; Since we have already switch to SVC R8_fiq - R12_fiq\r
- ; never get used or saved\r
- mov R0,#7 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-//\r
-// This gets patched by the C code that patches in the vector table\r
-//\r
-CommonExceptionEntry\r
- dcd AsmCommonExceptionEntry\r
-\r
-ExceptionHandlersEnd\r
-\r
-//\r
-// This code runs from CpuDxe driver loaded address. It is patched into \r
-// CommonExceptionEntry.\r
-//\r
-AsmCommonExceptionEntry\r
- mrc p15, 0, R1, c6, c0, 2 ; Read IFAR\r
- str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR \r
- \r
- mrc p15, 0, R1, c5, c0, 1 ; Read IFSR\r
- str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r
- \r
- mrc p15, 0, R1, c6, c0, 0 ; Read DFAR\r
- str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r
- \r
- mrc p15, 0, R1, c5, c0, 0 ; Read DFSR\r
- str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r
- \r
- ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack \r
- str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r
-\r
- add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
- and R3, R1, #0x1f ; Check CPSR to see if User or System Mode\r
- cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1df))\r
- cmpne R3, #0x10 ; \r
- stmeqed R2, {lr}^ ; save unbanked lr\r
- ; else \r
- stmneed R2, {lr} ; save SVC lr\r
-\r
-\r
- ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd \r
- ; Check to see if we have to adjust for Thumb entry\r
- sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType ==2)) {\r
- cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb \r
- bhi NoAdjustNeeded\r
- \r
- tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry \r
- addne R5, R5, #2 ; PC += 2;\r
- str R5,[SP,#0x58] ; Update LR value pused by srsfd \r
- \r
-NoAdjustNeeded\r
-\r
- str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r
- \r
- sub R1, SP, #0x60 ; We pused 0x60 bytes on the stack \r
- str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r
- \r
- ; R0 is ExceptionType \r
- mov R1,SP ; R1 is SystemContext \r
-\r
-#if (FixedPcdGet32(PcdVFPEnabled))\r
- vpush {d0-d15} ; save vstm registers in case they are used in optimizations\r
-#endif\r
-\r
-/* \r
-VOID\r
-EFIAPI\r
-CommonCExceptionHandler (\r
- IN EFI_EXCEPTION_TYPE ExceptionType, R0\r
- IN OUT EFI_SYSTEM_CONTEXT SystemContext R1\r
- )\r
-\r
-*/\r
- blx CommonCExceptionHandler ; Call exception handler\r
-\r
-#if (FixedPcdGet32(PcdVFPEnabled))\r
- vpop {d0-d15}\r
-#endif\r
- \r
- ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR\r
- mcr p15, 0, R1, c5, c0, 1 ; Write IFSR\r
-\r
- ldr R1, [SP, #0x44] ; sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR\r
- mcr p15, 0, R1, c5, c0, 0 ; Write DFSR\r
- \r
- ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC\r
- str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored \r
-\r
- ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR\r
- str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored \r
- \r
- add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry\r
- add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
- and R1, R1, #0x1f ; Check to see if User or System Mode\r
- cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))\r
- cmpne R1, #0x10 ; \r
- ldmeqed R2, {lr}^ ; restore unbanked lr\r
- ; else\r
- ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}\r
- \r
- ldmfd SP!,{R0-R12} ; Restore general purpose registers\r
- ; Exception handler can not change SP\r
- \r
- add SP,SP,#0x20 ; Clear out the remaining stack space\r
- ldmfd SP!,{LR} ; restore the link register for this context\r
- rfefd SP! ; return from exception via srsfd stack slot\r
- \r
- END\r
-\r
-\r
+++ /dev/null
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.align 3
-
-GCC_ASM_EXPORT(ExceptionHandlersStart)
-GCC_ASM_EXPORT(ExceptionHandlersEnd)
-GCC_ASM_EXPORT(CommonExceptionEntry)
-GCC_ASM_EXPORT(AsmCommonExceptionEntry)
-GCC_ASM_EXPORT(CommonCExceptionHandler)
-
-ASM_PFX(ExceptionHandlersStart):
-
-ASM_PFX(Reset):
- b ASM_PFX(ResetEntry)
-
-ASM_PFX(UndefinedInstruction):
- b ASM_PFX(UndefinedInstructionEntry)
-
-ASM_PFX(SoftwareInterrupt):
- b ASM_PFX(SoftwareInterruptEntry)
-
-ASM_PFX(PrefetchAbort):
- b ASM_PFX(PrefetchAbortEntry)
-
-ASM_PFX(DataAbort):
- b ASM_PFX(DataAbortEntry)
-
-ASM_PFX(ReservedException):
- b ASM_PFX(ReservedExceptionEntry)
-
-ASM_PFX(Irq):
- b ASM_PFX(IrqEntry)
-
-ASM_PFX(Fiq):
- b ASM_PFX(FiqEntry)
-
-ASM_PFX(ResetEntry):
- srsdb #0x13! @ Store return state on SVC stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#0
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(UndefinedInstructionEntry):
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#1
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(SoftwareInterruptEntry):
- srsdb #0x13! @ Store return state on SVC stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#2
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(PrefetchAbortEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#3
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(DataAbortEntry):
- sub LR,LR,#8
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#4
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(ReservedExceptionEntry):
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#5
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(IrqEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#6
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(FiqEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#7
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(CommonExceptionEntry):
- .byte 0x12
- .byte 0x34
- .byte 0x56
- .byte 0x78
-
-ASM_PFX(ExceptionHandlersEnd):
-
-ASM_PFX(AsmCommonExceptionEntry):
- mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
- str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
-
- mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
- str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
-
- mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
- str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
-
- mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
- str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
-
- ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
- str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
- and r1, r1, #0x1f @ Check to see if User or System Mode
- cmp r1, #0x1f
- cmpne r1, #0x10
- add R2, SP, #0x38 @ Store it in EFI_SYSTEM_CONTEXT_ARM.LR
- ldmneed r2, {lr}^ @ User or System mode, use unbanked register
- ldmneed r2, {lr} @ All other modes used banked register
-
- ldr R1, [SP, #0x58] @ PC is the LR pushed by srsdb
- str R1, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
-
- sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
- str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
-
- @ R0 is exception type
- mov R1,SP @ Prepare System Context pointer as an argument for the exception handler
- blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
-
- ldr R2,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
- str R2,[SP,#0x5c] @ Store it back to srsdb stack slot so it can be restored
-
- ldr R2,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
- str R2,[SP,#0x58] @ Store it back to srsdb stack slot so it can be restored
-
- ldmfd SP!,{R0-R12} @ Restore general purpose registers
- @ Exception handler can not change SP or LR as we would blow chunks
-
- add SP,SP,#0x20 @ Clear out the remaining stack space
- ldmfd SP!,{LR} @ restore the link register for this context
- rfefd SP! @ return from exception via srsdb stack slot
+++ /dev/null
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
- EXPORT ExceptionHandlersStart
- EXPORT ExceptionHandlersEnd
- EXPORT CommonExceptionEntry
- EXPORT AsmCommonExceptionEntry
- IMPORT CommonCExceptionHandler
-
- PRESERVE8
- AREA DxeExceptionHandlers, CODE, READONLY
-
-ExceptionHandlersStart
-
-Reset
- b ResetEntry
-
-UndefinedInstruction
- b UndefinedInstructionEntry
-
-SoftwareInterrupt
- b SoftwareInterruptEntry
-
-PrefetchAbort
- b PrefetchAbortEntry
-
-DataAbort
- b DataAbortEntry
-
-ReservedException
- b ReservedExceptionEntry
-
-Irq
- b IrqEntry
-
-Fiq
- b FiqEntry
-
-ResetEntry
- stmfd SP!,{R0-R1}
- mov R0,#0
- ldr R1,CommonExceptionEntry
- bx R1
-
-UndefinedInstructionEntry
- stmfd SP!,{R0-R1}
- mov R0,#1
- ldr R1,CommonExceptionEntry
- bx R1
-
-SoftwareInterruptEntry
- stmfd SP!,{R0-R1}
- mov R0,#2
- ldr R1,CommonExceptionEntry
- bx R1
-
-PrefetchAbortEntry
- stmfd SP!,{R0-R1}
- mov R0,#3
- SUB LR,LR,#4
- ldr R1,CommonExceptionEntry
- bx R1
-
-DataAbortEntry
- stmfd SP!,{R0-R1}
- mov R0,#4
- SUB LR,LR,#8
- ldr R1,CommonExceptionEntry
- bx R1
-
-ReservedExceptionEntry
- stmfd SP!,{R0-R1}
- mov R0,#5
- ldr R1,CommonExceptionEntry
- bx R1
-
-IrqEntry
- stmfd SP!,{R0-R1}
- mov R0,#6
- SUB LR,LR,#4
- ldr R1,CommonExceptionEntry
- bx R1
-
-FiqEntry
- stmfd SP!,{R0-R1}
- mov R0,#7
- SUB LR,LR,#4
- ldr R1,CommonExceptionEntry
- bx R1
-
-CommonExceptionEntry
- dcd 0x12345678
-
-ExceptionHandlersEnd
-
-AsmCommonExceptionEntry
- mrc p15, 0, r1, c6, c0, 2 ; Read IFAR
- stmfd SP!,{R1} ; Store the IFAR
-
- mrc p15, 0, r1, c5, c0, 1 ; Read IFSR
- stmfd SP!,{R1} ; Store the IFSR
-
- mrc p15, 0, r1, c6, c0, 0 ; Read DFAR
- stmfd SP!,{R1} ; Store the DFAR
-
- mrc p15, 0, r1, c5, c0, 0 ; Read DFSR
- stmfd SP!,{R1} ; Store the DFSR
-
- mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)
- stmfd SP!,{R1} ; Store the SPSR
-
- stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)
- stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register
- nop ; Required by ARM architecture
- SUB SP,SP,#0x08 ; Adjust stack pointer
- stmfd SP!,{R2-R12} ; Store general purpose registers
-
- ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)
- ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)
- stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1
-
- mov R1,SP ; Prepare System Context pointer as an argument for the exception handler
-
- sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment
- blx CommonCExceptionHandler ; Call exception handler
- add SP,SP,#4 ; Adjust SP back to where we were
-
- ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed
- MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler
-
- ldmfd SP!,{R0-R12} ; Restore general purpose registers
- ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register
- nop ; Required by ARM architecture
- add SP,SP,#0x08 ; Adjust stack pointer
- ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)
- add SP,SP,#0x1C ; Clear out the remaining stack space
- movs PC,LR ; Return from exception
-
- END
-
-
ENTRY_POINT = SemihostFsEntryPoint
-
[Sources.ARM]
Arm/SemihostFs.c
#\r
\r
\r
-[Sources.ARM]\r
+[Sources.Common]\r
ScanMem64Wrapper.c\r
ScanMem32Wrapper.c\r
ScanMem16Wrapper.c\r
MemLibGeneric.c\r
MemLibGuid.c \r
MemLibInternals.h\r
+\r
+[Sources.ARM]\r
Arm/CopyMem.asm\r
Arm/CopyMem.S\r
Arm/SetMem.asm\r
--- /dev/null
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http:#opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+#.include AsmMacroIoLib.inc\r
+\r
+#include <Chipset/ArmCortexA9.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
+\r
+# IN None\r
+# OUT r0 = SCU Base Address\r
+ASM_PFX(ArmGetScuBaseAddress):\r
+ # Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ # offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ bx lr\r
+\r
+# IN None\r
+# OUT r0 = number of cores present in the system\r
+ASM_PFX(ArmGetCpuCountPerCluster):\r
+ stmfd SP!, {r1-r2}\r
+\r
+ # Read CP15 MIDR\r
+ mrc p15, 0, r1, c0, c0, 0\r
+\r
+ # Check if the CPU is A15\r
+ mov r1, r1, LSR #4\r
+ LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r
+ and r1, r1, r0\r
+\r
+ LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r
+ cmp r1, r0\r
+ beq _Read_cp15_reg\r
+\r
+_CPU_is_not_A15:\r
+ mov r2, lr @ Save link register\r
+ bl ArmGetScuBaseAddress @ Read SCU Base Address\r
+ mov lr, r2 @ Restore link register val\r
+ ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r
+ b _Return\r
+\r
+_Read_cp15_reg:\r
+ mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r
+ lsr r0, #24\r
+\r
+_Return:\r
+ and r0, r0, #3\r
+ # Add '1' to the number of CPU on the Cluster\r
+ add r0, r0, #1\r
+ ldmfd SP!, {r1-r2}\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Chipset/ArmCortexA9.h>\r
+\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmGetCpuCountPerCluster\r
+ \r
+ AREA RTSMHelper, CODE, READONLY\r
+\r
+// IN None\r
+// OUT r0 = SCU Base Address\r
+ArmGetScuBaseAddress\r
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ // offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ bx lr\r
+\r
+// IN None\r
+// OUT r0 = number of cores present in the system\r
+ArmGetCpuCountPerCluster\r
+ stmfd SP!, {r1-r2}\r
+\r
+ // Read CP15 MIDR\r
+ mrc p15, 0, r1, c0, c0, 0\r
+\r
+ // Check if the CPU is A15\r
+ mov r1, r1, LSR #4\r
+ mov r0, #ARM_CPU_TYPE_MASK\r
+ and r1, r1, r0\r
+\r
+ mov r0, #ARM_CPU_TYPE_A15\r
+ cmp r1, r0\r
+ beq _Read_cp15_reg\r
+\r
+_CPU_is_not_A15\r
+ mov r2, lr ; Save link register\r
+ bl ArmGetScuBaseAddress ; Read SCU Base Address\r
+ mov lr, r2 ; Restore link register val\r
+ ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r
+ b _Return\r
+\r
+_Read_cp15_reg\r
+ mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r
+ lsr r0, #24\r
+\r
+\r
+_Return\r
+ and r0, r0, #3\r
+ // Add '1' to the number of CPU on the Cluster\r
+ add r0, r0, #1\r
+ ldmfd SP!, {r1-r2}\r
+ bx lr\r
+\r
+ END\r
\r
[Sources.common]\r
RTSM.c\r
- RTSMMem.c \r
- RTSMHelper.asm | RVCT\r
- RTSMHelper.S | GCC\r
+ RTSMMem.c\r
+\r
+[Sources.ARM]\r
+ Arm/RTSMHelper.asm | RVCT\r
+ Arm/RTSMHelper.S | GCC\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
\r
[Sources.common]\r
RTSM.c\r
- RTSMHelper.asm | RVCT\r
- RTSMHelper.S | GCC\r
+\r
+[Sources.ARM]\r
+ Arm/RTSMHelper.asm | RVCT\r
+ Arm/RTSMHelper.S | GCC\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+++ /dev/null
-#\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http:#opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-#.include AsmMacroIoLib.inc\r
-\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
-\r
-# IN None\r
-# OUT r0 = SCU Base Address\r
-ASM_PFX(ArmGetScuBaseAddress):\r
- # Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- # offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
-\r
-# IN None\r
-# OUT r0 = number of cores present in the system\r
-ASM_PFX(ArmGetCpuCountPerCluster):\r
- stmfd SP!, {r1-r2}\r
-\r
- # Read CP15 MIDR\r
- mrc p15, 0, r1, c0, c0, 0\r
-\r
- # Check if the CPU is A15\r
- mov r1, r1, LSR #4\r
- LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r
- and r1, r1, r0\r
-\r
- LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r
- cmp r1, r0\r
- beq _Read_cp15_reg\r
-\r
-_CPU_is_not_A15:\r
- mov r2, lr @ Save link register\r
- bl ArmGetScuBaseAddress @ Read SCU Base Address\r
- mov lr, r2 @ Restore link register val\r
- ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r
- b _Return\r
-\r
-_Read_cp15_reg:\r
- mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r
- lsr r0, #24\r
-\r
-_Return:\r
- and r0, r0, #3\r
- # Add '1' to the number of CPU on the Cluster\r
- add r0, r0, #1\r
- ldmfd SP!, {r1-r2}\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmGetCpuCountPerCluster\r
- \r
- AREA RTSMHelper, CODE, READONLY\r
-\r
-// IN None\r
-// OUT r0 = SCU Base Address\r
-ArmGetScuBaseAddress\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
-\r
-// IN None\r
-// OUT r0 = number of cores present in the system\r
-ArmGetCpuCountPerCluster\r
- stmfd SP!, {r1-r2}\r
-\r
- // Read CP15 MIDR\r
- mrc p15, 0, r1, c0, c0, 0\r
-\r
- // Check if the CPU is A15\r
- mov r1, r1, LSR #4\r
- mov r0, #ARM_CPU_TYPE_MASK\r
- and r1, r1, r0\r
-\r
- mov r0, #ARM_CPU_TYPE_A15\r
- cmp r1, r0\r
- beq _Read_cp15_reg\r
-\r
-_CPU_is_not_A15\r
- mov r2, lr ; Save link register\r
- bl ArmGetScuBaseAddress ; Read SCU Base Address\r
- mov lr, r2 ; Restore link register val\r
- ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r
- b _Return\r
-\r
-_Read_cp15_reg\r
- mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r
- lsr r0, #24\r
-\r
-\r
-_Return\r
- and r0, r0, #3\r
- // Add '1' to the number of CPU on the Cluster\r
- add r0, r0, #1\r
- ldmfd SP!, {r1-r2}\r
- bx lr\r
-\r
- END\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <AutoGen.h>\r
+#include <ArmPlatform.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
+\r
+/**\r
+ Call at the beginning of the platform boot up\r
+\r
+ This function allows the firmware platform to do extra actions at the early\r
+ stage of the platform power up.\r
+\r
+ Note: This function must be implemented in assembler as there is no stack set up yet\r
+\r
+**/\r
+ASM_PFX(ArmPlatformSecBootAction):\r
+ bx lr\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ASM_PFX(ArmPlatformSecBootMemoryInit):\r
+ // The SMC does not need to be initialized for RTSM\r
+ bx lr\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <AutoGen.h>\r
+#include <ArmPlatform.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformSecBootAction\r
+ EXPORT ArmPlatformSecBootMemoryInit\r
+\r
+ PRESERVE8\r
+ AREA RTSMVExpressBootMode, CODE, READONLY\r
+\r
+/**\r
+ Call at the beginning of the platform boot up\r
+\r
+ This function allows the firmware platform to do extra actions at the early\r
+ stage of the platform power up.\r
+\r
+ Note: This function must be implemented in assembler as there is no stack set up yet\r
+\r
+**/\r
+ArmPlatformSecBootAction\r
+ bx lr\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ArmPlatformSecBootMemoryInit\r
+ // The SMC does not need to be initialized for RTSM\r
+ bx lr\r
+\r
+ END\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http:#opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+#.include AsmMacroIoLib.inc\r
+\r
+#include <Chipset/ArmCortexA9.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
+\r
+# IN None\r
+# OUT r0 = SCU Base Address\r
+ASM_PFX(ArmGetScuBaseAddress):\r
+ # Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ # offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ bx lr\r
+\r
+# IN None\r
+# OUT r0 = number of cores present in the system\r
+ASM_PFX(ArmGetCpuCountPerCluster):\r
+ stmfd SP!, {r1-r2}\r
+\r
+ # Read CP15 MIDR\r
+ mrc p15, 0, r1, c0, c0, 0\r
+\r
+ # Check if the CPU is A15\r
+ mov r1, r1, LSR #4\r
+ LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r
+ and r1, r1, r0\r
+\r
+ LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r
+ cmp r1, r0\r
+ beq _Read_cp15_reg\r
+\r
+_CPU_is_not_A15:\r
+ mov r2, lr @ Save link register\r
+ bl ArmGetScuBaseAddress @ Read SCU Base Address\r
+ mov lr, r2 @ Restore link register val\r
+ ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r
+ b _Return\r
+\r
+_Read_cp15_reg:\r
+ mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r
+ lsr r0, #24\r
+\r
+_Return:\r
+ and r0, r0, #3\r
+ # Add '1' to the number of CPU on the Cluster\r
+ add r0, r0, #1\r
+ ldmfd SP!, {r1-r2}\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
--- /dev/null
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Chipset/ArmCortexA9.h>\r
+\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmGetCpuCountPerCluster\r
+ \r
+ AREA RTSMHelper, CODE, READONLY\r
+\r
+// IN None\r
+// OUT r0 = SCU Base Address\r
+ArmGetScuBaseAddress\r
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ // offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ bx lr\r
+\r
+// IN None\r
+// OUT r0 = number of cores present in the system\r
+ArmGetCpuCountPerCluster\r
+ stmfd SP!, {r1-r2}\r
+\r
+ // Read CP15 MIDR\r
+ mrc p15, 0, r1, c0, c0, 0\r
+\r
+ // Check if the CPU is A15\r
+ mov r1, r1, LSR #4\r
+ mov r0, #ARM_CPU_TYPE_MASK\r
+ and r1, r1, r0\r
+\r
+ mov r0, #ARM_CPU_TYPE_A15\r
+ cmp r1, r0\r
+ beq _Read_cp15_reg\r
+\r
+_CPU_is_not_A15\r
+ mov r2, lr ; Save link register\r
+ bl ArmGetScuBaseAddress ; Read SCU Base Address\r
+ mov lr, r2 ; Restore link register val\r
+ ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r
+ b _Return\r
+\r
+_Read_cp15_reg\r
+ mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r
+ lsr r0, #24\r
+\r
+\r
+_Return\r
+ and r0, r0, #3\r
+ // Add '1' to the number of CPU on the Cluster\r
+ add r0, r0, #1\r
+ ldmfd SP!, {r1-r2}\r
+ bx lr\r
+\r
+ END\r
[Sources.common]
RTSMSec.c
- RTSMBoot.asm | RVCT
- RTSMBoot.S | GCC
- RTSMHelper.asm | RVCT
- RTSMHelper.S | GCC
+
+[Sources.ARM]
+ Arm/RTSMBoot.asm | RVCT
+ Arm/RTSMBoot.S | GCC
+ Arm/RTSMHelper.asm | RVCT
+ Arm/RTSMHelper.S | GCC
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <AutoGen.h>\r
-#include <ArmPlatform.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootAction):\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootMemoryInit):\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <AutoGen.h>\r
-#include <ArmPlatform.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmPlatformSecBootAction\r
- EXPORT ArmPlatformSecBootMemoryInit\r
-\r
- PRESERVE8\r
- AREA RTSMVExpressBootMode, CODE, READONLY\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ArmPlatformSecBootAction\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ArmPlatformSecBootMemoryInit\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http:#opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-#.include AsmMacroIoLib.inc\r
-\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
-\r
-# IN None\r
-# OUT r0 = SCU Base Address\r
-ASM_PFX(ArmGetScuBaseAddress):\r
- # Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- # offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
-\r
-# IN None\r
-# OUT r0 = number of cores present in the system\r
-ASM_PFX(ArmGetCpuCountPerCluster):\r
- stmfd SP!, {r1-r2}\r
-\r
- # Read CP15 MIDR\r
- mrc p15, 0, r1, c0, c0, 0\r
-\r
- # Check if the CPU is A15\r
- mov r1, r1, LSR #4\r
- LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r
- and r1, r1, r0\r
-\r
- LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r
- cmp r1, r0\r
- beq _Read_cp15_reg\r
-\r
-_CPU_is_not_A15:\r
- mov r2, lr @ Save link register\r
- bl ArmGetScuBaseAddress @ Read SCU Base Address\r
- mov lr, r2 @ Restore link register val\r
- ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r
- b _Return\r
-\r
-_Read_cp15_reg:\r
- mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r
- lsr r0, #24\r
-\r
-_Return:\r
- and r0, r0, #3\r
- # Add '1' to the number of CPU on the Cluster\r
- add r0, r0, #1\r
- ldmfd SP!, {r1-r2}\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmGetCpuCountPerCluster\r
- \r
- AREA RTSMHelper, CODE, READONLY\r
-\r
-// IN None\r
-// OUT r0 = SCU Base Address\r
-ArmGetScuBaseAddress\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
-\r
-// IN None\r
-// OUT r0 = number of cores present in the system\r
-ArmGetCpuCountPerCluster\r
- stmfd SP!, {r1-r2}\r
-\r
- // Read CP15 MIDR\r
- mrc p15, 0, r1, c0, c0, 0\r
-\r
- // Check if the CPU is A15\r
- mov r1, r1, LSR #4\r
- mov r0, #ARM_CPU_TYPE_MASK\r
- and r1, r1, r0\r
-\r
- mov r0, #ARM_CPU_TYPE_A15\r
- cmp r1, r0\r
- beq _Read_cp15_reg\r
-\r
-_CPU_is_not_A15\r
- mov r2, lr ; Save link register\r
- bl ArmGetScuBaseAddress ; Read SCU Base Address\r
- mov lr, r2 ; Restore link register val\r
- ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r
- b _Return\r
-\r
-_Read_cp15_reg\r
- mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r
- lsr r0, #24\r
-\r
-\r
-_Return\r
- and r0, r0, #3\r
- // Add '1' to the number of CPU on the Cluster\r
- add r0, r0, #1\r
- ldmfd SP!, {r1-r2}\r
- bx lr\r
-\r
- END\r
\r
[Sources.common]\r
ArmPlatformLibNullSec.c\r
+\r
+[Sources.ARM]\r
ArmPlatformLibNullBoot.asm | RVCT\r
ArmPlatformLibNullBoot.S | GCC\r
\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <AutoGen.h>\r
+#include <Library/PcdLib.h>\r
+\r
+.text\r
+.align 5\r
+\r
+GCC_ASM_EXPORT(MonitorVectorTable)\r
+\r
+ASM_PFX(MonitorVectorTable):\r
+\r
+_MonitorResetEntry:\r
+ b _MonitorResetEntry\r
+_MonitorUndefinedEntry:\r
+ b _MonitorUndefinedEntry\r
+_MonitorSmcEntry:\r
+ b _MonitorSmcEntry\r
+_MonitorPrefetchEntry:\r
+ b _MonitorPrefetchEntry\r
+_MonitorDataAbortEntry:\r
+ b _MonitorDataAbortEntry\r
+_MonitorReservedEntry:\r
+ b _MonitorReservedEntry\r
+_MonitorIrqEntry:\r
+ b _MonitorIrqEntry\r
+_MonitorFiqEntry:\r
+ b _MonitorFiqEntry\r
+\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <Library/PcdLib.h>\r
+\r
+ EXPORT MonitorVectorTable\r
+\r
+ PRESERVE8\r
+ AREA MonitoVectorTableArea, CODE, READONLY, CODEALIGN, ALIGN=5\r
+\r
+MonitorVectorTable\r
+\r
+_MonitorResetEntry\r
+ b _MonitorResetEntry\r
+_MonitorUndefinedEntry\r
+ b _MonitorUndefinedEntry\r
+_MonitorSmcEntry\r
+ b _MonitorSmcEntry\r
+_MonitorPrefetchEntry\r
+ b _MonitorPrefetchEntry\r
+_MonitorDataAbortEntry\r
+ b _MonitorDataAbortEntry\r
+_MonitorReservedEntry\r
+ b _MonitorReservedEntry\r
+_MonitorIrqEntry\r
+ b _MonitorIrqEntry\r
+_MonitorFiqEntry\r
+ b _MonitorFiqEntry\r
+\r
+ END\r
#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
\r
[Sources.common]\r
ArmTrustedMonitorLibNull.c\r
- MonitorTable.asm | RVCT\r
- MonitorTable.S | GCC\r
+\r
+[Sources.ARM]\r
+ Arm/MonitorTable.asm | RVCT\r
+ Arm/MonitorTable.S | GCC\r
\r
[Packages]\r
ArmPkg/ArmPkg.dec\r
BaseLib\r
DebugLib\r
PcdLib\r
-
\ No newline at end of file
+ \r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <AutoGen.h>\r
-#include <Library/PcdLib.h>\r
-\r
-.text\r
-.align 5\r
-\r
-GCC_ASM_EXPORT(MonitorVectorTable)\r
-\r
-ASM_PFX(MonitorVectorTable):\r
-\r
-_MonitorResetEntry:\r
- b _MonitorResetEntry\r
-_MonitorUndefinedEntry:\r
- b _MonitorUndefinedEntry\r
-_MonitorSmcEntry:\r
- b _MonitorSmcEntry\r
-_MonitorPrefetchEntry:\r
- b _MonitorPrefetchEntry\r
-_MonitorDataAbortEntry:\r
- b _MonitorDataAbortEntry\r
-_MonitorReservedEntry:\r
- b _MonitorReservedEntry\r
-_MonitorIrqEntry:\r
- b _MonitorIrqEntry\r
-_MonitorFiqEntry:\r
- b _MonitorFiqEntry\r
-\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Library/PcdLib.h>\r
-\r
- EXPORT MonitorVectorTable\r
-\r
- PRESERVE8\r
- AREA MonitoVectorTableArea, CODE, READONLY, CODEALIGN, ALIGN=5\r
-\r
-MonitorVectorTable\r
-\r
-_MonitorResetEntry\r
- b _MonitorResetEntry\r
-_MonitorUndefinedEntry\r
- b _MonitorUndefinedEntry\r
-_MonitorSmcEntry\r
- b _MonitorSmcEntry\r
-_MonitorPrefetchEntry\r
- b _MonitorPrefetchEntry\r
-_MonitorDataAbortEntry\r
- b _MonitorDataAbortEntry\r
-_MonitorReservedEntry\r
- b _MonitorReservedEntry\r
-_MonitorIrqEntry\r
- b _MonitorIrqEntry\r
-_MonitorFiqEntry\r
- b _MonitorFiqEntry\r
-\r
- END\r
projects / mirror_edk2.git / commitdiff