Fix build break when doing 32-bit build with some certain C compiler option combinations.

Use the library functions for shift operations in BaseLib for a 64-bit integer where the code is shared for 32-bit and 64-bit.
Defining bitfields in structures with > 32 bits will cause these types of issues on IA32 builds. So the largest bitfield should be type UINT32 with a max size of :32.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10983 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h
index e22900d0cc2eb542c42d594bc2ef5c11cca08d01..9f8f1bb8bb7de0c195087bcef931d1cf08d47206 100644 (file)
--- a/UefiCpuPkg/Include/Register/LocalApic.h
+++ b/UefiCpuPkg/Include/Register/LocalApic.h
@@ -62,12 +62,13 @@
 \r
 typedef union {\r
   struct {\r
-    UINT64  Reserved0:8;   ///< Reserved.\r
-    UINT64  Bsp:1;         ///< Processor is BSP.\r
-    UINT64  Reserved1:1;   ///< Reserved.\r
-    UINT64  Extd:1;        ///< Enable x2APIC mode.\r
-    UINT64  En:1;          ///< xAPIC global enable/disable.\r
-    UINT64  ApicBase:52;   ///< APIC Base physical address. The actual field width depends on physical address width.\r
+    UINT32  Reserved0:8;     ///< Reserved.\r
+    UINT32  Bsp:1;           ///< Processor is BSP.\r
+    UINT32  Reserved1:1;     ///< Reserved.\r
+    UINT32  Extd:1;          ///< Enable x2APIC mode.\r
+    UINT32  En:1;            ///< xAPIC global enable/disable.\r
+    UINT32  ApicBaseLow:20;  ///< APIC Base physical address. The actual field width depends on physical address width.\r
+    UINT32  ApicBaseHigh:32;\r
   } Bits;\r
   UINT64    Uint64;\r
 } MSR_IA32_APIC_BASE;\r

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 1cba34cd598e605d3840d24e2f1ba22c5bdc3edc..9f08f5d188c14d9ec5313275b0ce0b67aa16c9e0 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -151,7 +151,7 @@ SendIpi (
     // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an \r
     // interrupt in x2APIC mode.\r
     //\r
-    MsrValue = (((UINT64)ApicId) << 32) | IcrLow;\r
+    MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;\r
     AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);\r
   }\r
 }\r