NASM has replaced ASM and S files.
1. Remove ASM from all modules expect for the ones in ResetVector directory.
The ones in ResetVector directory are included by Vtf0.nasmb. They are
also nasm style.
2. Remove S files from the drivers only.
3. https://bugzilla.tianocore.org/show_bug.cgi?id=881
After NASM is updated, S files can be removed from Library.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
## @file\r
# CPU driver installs CPU Architecture Protocol and CPU MP protocol.\r
#\r
-# Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>\r
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
CpuPageTable.c\r
\r
[Sources.IA32]\r
- Ia32/CpuAsm.asm\r
Ia32/CpuAsm.nasm\r
- Ia32/CpuAsm.S\r
\r
[Sources.X64]\r
- X64/CpuAsm.asm\r
X64/CpuAsm.nasm\r
- X64/CpuAsm.S\r
\r
[Protocols]\r
gEfiCpuArchProtocolGuid ## PRODUCES\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#*\r
-#* Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
-#* This program and the accompanying materials\r
-#* are licensed and made available under the terms and conditions of the BSD License\r
-#* which accompanies this distribution. The full text of the license may be found at\r
-#* http://opensource.org/licenses/bsd-license.php\r
-#*\r
-#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#*\r
-#* CpuAsm.S\r
-#*\r
-#* Abstract:\r
-#*\r
-#------------------------------------------------------------------------------\r
-\r
-\r
-#.MMX\r
-#.XMM\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# SetCodeSelector (\r
-# UINT16 Selector\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(SetCodeSelector)\r
-ASM_PFX(SetCodeSelector):\r
- movl 4(%esp), %ecx\r
- subl $0x10, %esp \r
- leal setCodeSelectorLongJump, %eax \r
- movl %eax, (%esp)\r
- movw %cx, 4(%esp)\r
- .byte 0xFF, 0x2C, 0x24 # jmp *(%esp) note:(FWORD jmp) \r
-setCodeSelectorLongJump:\r
- addl $0x10, %esp \r
- ret\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# SetDataSelectors (\r
-# UINT16 Selector\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(SetDataSelectors)\r
-ASM_PFX(SetDataSelectors):\r
- movl 4(%esp), %ecx\r
- movw %cx, %ss\r
- movw %cx, %ds\r
- movw %cx, %es\r
- movw %cx, %fs\r
- movw %cx, %gs\r
- ret\r
-\r
-#END\r
-\r
+++ /dev/null
- TITLE CpuAsm.asm:\r
-;------------------------------------------------------------------------------\r
-;*\r
-;* Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
-;* This program and the accompanying materials\r
-;* are licensed and made available under the terms and conditions of the BSD License\r
-;* which accompanies this distribution. The full text of the license may be found at\r
-;* http://opensource.org/licenses/bsd-license.php\r
-;*\r
-;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;*\r
-;* CpuAsm.asm\r
-;*\r
-;* Abstract:\r
-;*\r
-;------------------------------------------------------------------------------\r
-\r
- .686\r
- .model flat,C\r
- .code\r
-\r
-;------------------------------------------------------------------------------\r
-; VOID\r
-; SetCodeSelector (\r
-; UINT16 Selector\r
-; );\r
-;------------------------------------------------------------------------------\r
-SetCodeSelector PROC PUBLIC\r
- mov ecx, [esp+4]\r
- sub esp, 0x10\r
- lea eax, setCodeSelectorLongJump\r
- mov [esp], eax\r
- mov [esp+4], cx\r
- jmp fword ptr [esp]\r
-setCodeSelectorLongJump:\r
- add esp, 0x10\r
- ret\r
-SetCodeSelector ENDP\r
-\r
-;------------------------------------------------------------------------------\r
-; VOID\r
-; SetDataSelectors (\r
-; UINT16 Selector\r
-; );\r
-;------------------------------------------------------------------------------\r
-SetDataSelectors PROC PUBLIC\r
- mov ecx, [esp+4]\r
- mov ss, cx\r
- mov ds, cx\r
- mov es, cx\r
- mov fs, cx\r
- mov gs, cx\r
- ret\r
-SetDataSelectors ENDP\r
-\r
-\r
-END\r
+++ /dev/null
-# TITLE CpuAsm.S: \r
-\r
-#------------------------------------------------------------------------------\r
-#*\r
-#* Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
-#* This program and the accompanying materials\r
-#* are licensed and made available under the terms and conditions of the BSD License\r
-#* which accompanies this distribution. The full text of the license may be found at\r
-#* http://opensource.org/licenses/bsd-license.php\r
-#*\r
-#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#*\r
-#* CpuAsm.S\r
-#*\r
-#* Abstract:\r
-#*\r
-#------------------------------------------------------------------------------\r
-\r
-\r
-#text SEGMENT\r
-\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# SetCodeSelector (\r
-# UINT16 Selector\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(SetCodeSelector)\r
-ASM_PFX(SetCodeSelector):\r
- subq $0x10, %rsp \r
- leaq L_setCodeSelectorLongJump(%rip), %rax \r
- movq %rax, (%rsp) \r
- movw %cx, 4(%rsp)\r
- .byte 0xFF, 0x2C, 0x24 # jmp (%rsp) note:fword jmp\r
-L_setCodeSelectorLongJump:\r
- addq $0x10, %rsp\r
- ret\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# SetDataSelectors (\r
-# UINT16 Selector\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(SetDataSelectors)\r
-ASM_PFX(SetDataSelectors):\r
- movw %cx, %ss\r
- movw %cx, %ds\r
- movw %cx, %es\r
- movw %cx, %fs\r
- movw %cx, %gs\r
- ret\r
-\r
-#text ENDS\r
-\r
-#END\r
-\r
-\r
+++ /dev/null
- TITLE CpuAsm.asm: \r
-;------------------------------------------------------------------------------\r
-;*\r
-;* Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
-;* This program and the accompanying materials \r
-;* are licensed and made available under the terms and conditions of the BSD License \r
-;* which accompanies this distribution. The full text of the license may be found at \r
-;* http://opensource.org/licenses/bsd-license.php \r
-;* \r
-;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-;* \r
-;* CpuAsm.asm\r
-;* \r
-;* Abstract:\r
-;*\r
-;------------------------------------------------------------------------------\r
-\r
- .code\r
-\r
-;------------------------------------------------------------------------------\r
-; VOID\r
-; SetCodeSelector (\r
-; UINT16 Selector\r
-; );\r
-;------------------------------------------------------------------------------\r
-SetCodeSelector PROC PUBLIC\r
- sub rsp, 0x10\r
- lea rax, setCodeSelectorLongJump\r
- mov [rsp], rax\r
- mov [rsp+4], cx\r
- jmp fword ptr [rsp]\r
-setCodeSelectorLongJump:\r
- add rsp, 0x10\r
- ret\r
-SetCodeSelector ENDP\r
-\r
-;------------------------------------------------------------------------------\r
-; VOID\r
-; SetDataSelectors (\r
-; UINT16 Selector\r
-; );\r
-;------------------------------------------------------------------------------\r
-SetDataSelectors PROC PUBLIC\r
- mov ss, cx\r
- mov ds, cx\r
- mov es, cx\r
- mov fs, cx\r
- mov gs, cx\r
- ret\r
-SetDataSelectors ENDP\r
-\r
-END\r
-\r
#\r
# The library routines are UEFI specification compliant.\r
#\r
-# Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
#\r
\r
[Sources.IA32]\r
- Ia32/InitializeFpu.asm\r
Ia32/InitializeFpu.nasm\r
Ia32/InitializeFpu.S\r
\r
[Sources.X64]\r
- X64/InitializeFpu.asm\r
X64/InitializeFpu.nasm\r
X64/InitializeFpu.S\r
\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-;*\r
-;* Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>\r
-;* This program and the accompanying materials\r
-;* are licensed and made available under the terms and conditions of the BSD License\r
-;* which accompanies this distribution. The full text of the license may be found at\r
-;* http://opensource.org/licenses/bsd-license.php\r
-;*\r
-;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;*\r
-;* \r
-;------------------------------------------------------------------------------\r
-\r
-\r
- .686\r
- .model flat,C\r
- .const\r
-;\r
-; Float control word initial value: \r
-; all exceptions masked, double-precision, round-to-nearest\r
-;\r
-mFpuControlWord DW 027Fh\r
-;\r
-; Multimedia-extensions control word:\r
-; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
-;\r
-mMmxControlWord DD 01F80h \r
-\r
- .xmm\r
- .code\r
-\r
-;\r
-; Initializes floating point units for requirement of UEFI specification.\r
-;\r
-; This function initializes floating-point control word to 0x027F (all exceptions\r
-; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
-; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
-; for masked underflow).\r
-;\r
-InitializeFloatingPointUnits PROC PUBLIC\r
-\r
- push ebx\r
-\r
- ;\r
- ; Initialize floating point units\r
- ;\r
- finit\r
- fldcw mFpuControlWord\r
- \r
- ;\r
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
- ; whether the processor supports SSE instruction.\r
- ;\r
- mov eax, 1\r
- cpuid\r
- bt edx, 25\r
- jnc Done\r
- \r
- ;\r
- ; Set OSFXSR bit 9 in CR4\r
- ;\r
- mov eax, cr4\r
- or eax, BIT9\r
- mov cr4, eax\r
- \r
- ;\r
- ; The processor should support SSE instruction and we can use\r
- ; ldmxcsr instruction\r
- ;\r
- ldmxcsr mMmxControlWord\r
-Done:\r
- pop ebx\r
-\r
- ret\r
-\r
-InitializeFloatingPointUnits ENDP\r
-\r
-END\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-;*\r
-;* Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>\r
-;* This program and the accompanying materials\r
-;* are licensed and made available under the terms and conditions of the BSD License\r
-;* which accompanies this distribution. The full text of the license may be found at\r
-;* http://opensource.org/licenses/bsd-license.php\r
-;*\r
-;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;*\r
-;*\r
-;------------------------------------------------------------------------------\r
-\r
-\r
-.const\r
-;\r
-; Float control word initial value: \r
-; all exceptions masked, double-extended-precision, round-to-nearest\r
-;\r
-mFpuControlWord DW 037Fh\r
-;\r
-; Multimedia-extensions control word:\r
-; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
-;\r
-mMmxControlWord DD 01F80h \r
-\r
-.code\r
-\r
-\r
-;\r
-; Initializes floating point units for requirement of UEFI specification.\r
-;\r
-; This function initializes floating-point control word to 0x027F (all exceptions\r
-; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
-; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
-; for masked underflow).\r
-;\r
-InitializeFloatingPointUnits PROC PUBLIC\r
-\r
- ;\r
- ; Initialize floating point units\r
- ;\r
- ; The following opcodes stand for instruction 'finit' \r
- ; to be supported by some 64-bit assemblers\r
- ;\r
- DB 9Bh, 0DBh, 0E3h\r
- fldcw mFpuControlWord\r
- \r
- ;\r
- ; Set OSFXSR bit 9 in CR4\r
- ;\r
- mov rax, cr4\r
- or rax, BIT9\r
- mov cr4, rax\r
-\r
- ldmxcsr mMmxControlWord\r
- \r
- ret\r
-InitializeFloatingPointUnits ENDP\r
-\r
-END\r
## @file\r
# CPU Exception Handler library instance for DXE modules.\r
#\r
-# Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
#\r
\r
[Sources.Ia32]\r
- Ia32/ExceptionHandlerAsm.asm\r
Ia32/ExceptionHandlerAsm.nasm\r
Ia32/ExceptionTssEntryAsm.nasm\r
Ia32/ExceptionHandlerAsm.S\r
Ia32/ArchInterruptDefs.h\r
\r
[Sources.X64]\r
- X64/ExceptionHandlerAsm.asm\r
X64/ExceptionHandlerAsm.nasm\r
X64/ExceptionHandlerAsm.S\r
X64/ArchExceptionHandler.c\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; ExceptionHandlerAsm.Asm\r
-;\r
-; Abstract:\r
-;\r
-; IA32 CPU Exception Handler\r
-;\r
-; Notes:\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
- .686\r
- .model flat,C\r
-\r
-;\r
-; CommonExceptionHandler()\r
-;\r
-CommonExceptionHandler PROTO C\r
-\r
-.data\r
-\r
-EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions\r
-EXTRN mDoFarReturnFlag:DWORD ; Do far return flag\r
-\r
-.code\r
-\r
-ALIGN 8\r
-\r
-;\r
-; exception handler stub table\r
-;\r
-AsmIdtVectorBegin:\r
-REPEAT 32\r
- db 6ah ; push #VectorNum\r
- db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum\r
- push eax\r
- mov eax, CommonInterruptEntry\r
- jmp eax\r
-ENDM\r
-AsmIdtVectorEnd:\r
-\r
-HookAfterStubBegin:\r
- db 6ah ; push\r
-VectorNum:\r
- db 0 ; 0 will be fixed\r
- push eax\r
- mov eax, HookAfterStubHeaderEnd\r
- jmp eax\r
-HookAfterStubHeaderEnd:\r
- pop eax\r
- sub esp, 8 ; reserve room for filling exception data later\r
- push [esp + 8]\r
- xchg ecx, [esp] ; get vector number\r
- bt mErrorCodeFlag, ecx\r
- jnc @F\r
- push [esp] ; addition push if exception data needed\r
-@@:\r
- xchg ecx, [esp] ; restore ecx\r
- push eax\r
-\r
-;----------------------------------------------------------------------------;\r
-; CommonInterruptEntry ;\r
-;----------------------------------------------------------------------------;\r
-; The follow algorithm is used for the common interrupt routine.\r
-; Entry from each interrupt with a push eax and eax=interrupt number\r
-; Stack:\r
-; +---------------------+\r
-; + EFlags +\r
-; +---------------------+\r
-; + CS +\r
-; +---------------------+\r
-; + EIP +\r
-; +---------------------+\r
-; + Error Code +\r
-; +---------------------+\r
-; + Vector Number +\r
-; +---------------------+\r
-; + EBP +\r
-; +---------------------+ <-- EBP\r
-CommonInterruptEntry PROC PUBLIC\r
- cli\r
- pop eax\r
- ;\r
- ; All interrupt handlers are invoked through interrupt gates, so\r
- ; IF flag automatically cleared at the entry point\r
- ;\r
-\r
- ;\r
- ; Get vector number from top of stack\r
- ;\r
- xchg ecx, [esp]\r
- and ecx, 0FFh ; Vector number should be less than 256\r
- cmp ecx, 32 ; Intel reserved vector for exceptions?\r
- jae NoErrorCode\r
- bt mErrorCodeFlag, ecx\r
- jc HasErrorCode\r
-\r
-NoErrorCode:\r
-\r
- ;\r
- ; Stack:\r
- ; +---------------------+\r
- ; + EFlags +\r
- ; +---------------------+\r
- ; + CS +\r
- ; +---------------------+\r
- ; + EIP +\r
- ; +---------------------+\r
- ; + ECX +\r
- ; +---------------------+ <-- ESP\r
- ;\r
- ; Registers:\r
- ; ECX - Vector Number\r
- ;\r
-\r
- ;\r
- ; Put Vector Number on stack\r
- ;\r
- push ecx\r
-\r
- ;\r
- ; Put 0 (dummy) error code on stack, and restore ECX\r
- ;\r
- xor ecx, ecx ; ECX = 0\r
- xchg ecx, [esp+4]\r
-\r
- jmp ErrorCodeAndVectorOnStack\r
-\r
-HasErrorCode:\r
-\r
- ;\r
- ; Stack:\r
- ; +---------------------+\r
- ; + EFlags +\r
- ; +---------------------+\r
- ; + CS +\r
- ; +---------------------+\r
- ; + EIP +\r
- ; +---------------------+\r
- ; + Error Code +\r
- ; +---------------------+\r
- ; + ECX +\r
- ; +---------------------+ <-- ESP\r
- ;\r
- ; Registers:\r
- ; ECX - Vector Number\r
- ;\r
-\r
- ;\r
- ; Put Vector Number on stack and restore ECX\r
- ;\r
- xchg ecx, [esp]\r
-\r
-ErrorCodeAndVectorOnStack:\r
- push ebp\r
- mov ebp, esp\r
-\r
- ;\r
- ; Stack:\r
- ; +---------------------+\r
- ; + EFlags +\r
- ; +---------------------+\r
- ; + CS +\r
- ; +---------------------+\r
- ; + EIP +\r
- ; +---------------------+\r
- ; + Error Code +\r
- ; +---------------------+\r
- ; + Vector Number +\r
- ; +---------------------+\r
- ; + EBP +\r
- ; +---------------------+ <-- EBP\r
- ;\r
-\r
- ;\r
- ; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32\r
- ; is 16-byte aligned\r
- ;\r
- and esp, 0fffffff0h\r
- sub esp, 12\r
-\r
- sub esp, 8\r
- push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler\r
- push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag\r
-\r
-;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- push eax\r
- push ecx\r
- push edx\r
- push ebx\r
- lea ecx, [ebp + 6 * 4]\r
- push ecx ; ESP\r
- push dword ptr [ebp] ; EBP\r
- push esi\r
- push edi\r
-\r
-;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
- mov eax, ss\r
- push eax\r
- movzx eax, word ptr [ebp + 4 * 4]\r
- push eax\r
- mov eax, ds\r
- push eax\r
- mov eax, es\r
- push eax\r
- mov eax, fs\r
- push eax\r
- mov eax, gs\r
- push eax\r
-\r
-;; UINT32 Eip;\r
- mov eax, [ebp + 3 * 4]\r
- push eax\r
-\r
-;; UINT32 Gdtr[2], Idtr[2];\r
- sub esp, 8\r
- sidt [esp]\r
- mov eax, [esp + 2]\r
- xchg eax, [esp]\r
- and eax, 0FFFFh\r
- mov [esp+4], eax\r
-\r
- sub esp, 8\r
- sgdt [esp]\r
- mov eax, [esp + 2]\r
- xchg eax, [esp]\r
- and eax, 0FFFFh\r
- mov [esp+4], eax\r
-\r
-;; UINT32 Ldtr, Tr;\r
- xor eax, eax\r
- str ax\r
- push eax\r
- sldt ax\r
- push eax\r
-\r
-;; UINT32 EFlags;\r
- mov eax, [ebp + 5 * 4]\r
- push eax\r
-\r
-;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- mov eax, 1\r
- push ebx ; temporarily save value of ebx on stack\r
- cpuid ; use CPUID to determine if FXSAVE/FXRESTOR and DE\r
- ; are supported\r
- pop ebx ; retore value of ebx that was overwritten by CPUID\r
- mov eax, cr4\r
- push eax ; push cr4 firstly\r
- test edx, BIT24 ; Test for FXSAVE/FXRESTOR support\r
- jz @F\r
- or eax, BIT9 ; Set CR4.OSFXSR\r
-@@:\r
- test edx, BIT2 ; Test for Debugging Extensions support\r
- jz @F\r
- or eax, BIT3 ; Set CR4.DE\r
-@@:\r
- mov cr4, eax\r
- mov eax, cr3\r
- push eax\r
- mov eax, cr2\r
- push eax\r
- xor eax, eax\r
- push eax\r
- mov eax, cr0\r
- push eax\r
-\r
-;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
- mov eax, dr7\r
- push eax\r
- mov eax, dr6\r
- push eax\r
- mov eax, dr3\r
- push eax\r
- mov eax, dr2\r
- push eax\r
- mov eax, dr1\r
- push eax\r
- mov eax, dr0\r
- push eax\r
-\r
-;; FX_SAVE_STATE_IA32 FxSaveState;\r
- sub esp, 512\r
- mov edi, esp\r
- test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.\r
- ; edx still contains result from CPUID above\r
- jz @F\r
- db 0fh, 0aeh, 07h ;fxsave [edi]\r
-@@:\r
-\r
-;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
- cld\r
-\r
-;; UINT32 ExceptionData;\r
- push dword ptr [ebp + 2 * 4]\r
-\r
-;; Prepare parameter and call\r
- mov edx, esp\r
- push edx\r
- mov edx, dword ptr [ebp + 1 * 4]\r
- push edx\r
-\r
- ;\r
- ; Call External Exception Handler\r
- ;\r
- mov eax, CommonExceptionHandler\r
- call eax\r
- add esp, 8\r
-\r
- cli\r
-;; UINT32 ExceptionData;\r
- add esp, 4\r
-\r
-;; FX_SAVE_STATE_IA32 FxSaveState;\r
- mov esi, esp\r
- mov eax, 1\r
- cpuid ; use CPUID to determine if FXSAVE/FXRESTOR\r
- ; are supported\r
- test edx, BIT24 ; Test for FXSAVE/FXRESTOR support\r
- jz @F\r
- db 0fh, 0aeh, 0eh ; fxrstor [esi]\r
-@@:\r
- add esp, 512\r
-\r
-;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
-;; Skip restoration of DRx registers to support in-circuit emualators\r
-;; or debuggers set breakpoint in interrupt/exception context\r
- add esp, 4 * 6\r
-\r
-;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- pop eax\r
- mov cr0, eax\r
- add esp, 4 ; not for Cr1\r
- pop eax\r
- mov cr2, eax\r
- pop eax\r
- mov cr3, eax\r
- pop eax\r
- mov cr4, eax\r
-\r
-;; UINT32 EFlags;\r
- pop dword ptr [ebp + 5 * 4]\r
-\r
-;; UINT32 Ldtr, Tr;\r
-;; UINT32 Gdtr[2], Idtr[2];\r
-;; Best not let anyone mess with these particular registers...\r
- add esp, 24\r
-\r
-;; UINT32 Eip;\r
- pop dword ptr [ebp + 3 * 4]\r
-\r
-;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
-;; NOTE - modified segment registers could hang the debugger... We\r
-;; could attempt to insulate ourselves against this possibility,\r
-;; but that poses risks as well.\r
-;;\r
- pop gs\r
- pop fs\r
- pop es\r
- pop ds\r
- pop dword ptr [ebp + 4 * 4]\r
- pop ss\r
-\r
-;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- pop edi\r
- pop esi\r
- add esp, 4 ; not for ebp\r
- add esp, 4 ; not for esp\r
- pop ebx\r
- pop edx\r
- pop ecx\r
- pop eax\r
-\r
- pop dword ptr [ebp - 8]\r
- pop dword ptr [ebp - 4]\r
- mov esp, ebp\r
- pop ebp\r
- add esp, 8\r
- cmp dword ptr [esp - 16], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler\r
- jz DoReturn\r
- cmp dword ptr [esp - 20], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag\r
- jz ErrorCode\r
- jmp dword ptr [esp - 16]\r
-ErrorCode:\r
- sub esp, 4\r
- jmp dword ptr [esp - 12]\r
-\r
-DoReturn:\r
- cmp mDoFarReturnFlag, 0 ; Check if need to do far return instead of IRET\r
- jz DoIret\r
- push [esp + 8] ; save EFLAGS\r
- add esp, 16\r
- push [esp - 8] ; save CS in new location\r
- push [esp - 8] ; save EIP in new location\r
- push [esp - 8] ; save EFLAGS in new location\r
- popfd ; restore EFLAGS\r
- retf ; far return\r
-\r
-DoIret:\r
- iretd\r
-\r
-CommonInterruptEntry ENDP\r
-\r
-;---------------------------------------;\r
-; _AsmGetTemplateAddressMap ;\r
-;----------------------------------------------------------------------------;\r
-;\r
-; Protocol prototype\r
-; AsmGetTemplateAddressMap (\r
-; EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap\r
-; );\r
-;\r
-; Routine Description:\r
-;\r
-; Return address map of interrupt handler template so that C code can generate\r
-; interrupt table.\r
-;\r
-; Arguments:\r
-;\r
-;\r
-; Returns:\r
-;\r
-; Nothing\r
-;\r
-;\r
-; Input: [ebp][0] = Original ebp\r
-; [ebp][4] = Return address\r
-;\r
-; Output: Nothing\r
-;\r
-; Destroys: Nothing\r
-;-----------------------------------------------------------------------------;\r
-AsmGetTemplateAddressMap proc near public\r
- push ebp ; C prolog\r
- mov ebp, esp\r
- pushad\r
-\r
- mov ebx, dword ptr [ebp + 08h]\r
- mov dword ptr [ebx], AsmIdtVectorBegin\r
- mov dword ptr [ebx + 4h], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32\r
- mov dword ptr [ebx + 8h], HookAfterStubBegin\r
-\r
- popad\r
- pop ebp\r
- ret\r
-AsmGetTemplateAddressMap ENDP\r
-\r
-;-------------------------------------------------------------------------------------\r
-; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);\r
-;-------------------------------------------------------------------------------------\r
-AsmVectorNumFixup proc near public\r
- mov eax, dword ptr [esp + 8]\r
- mov ecx, [esp + 4]\r
- mov [ecx + (VectorNum - HookAfterStubBegin)], al\r
- ret\r
-AsmVectorNumFixup ENDP\r
-END\r
## @file\r
# CPU Exception Handler library instance for PEI module.\r
#\r
-# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
#\r
\r
[Sources.Ia32]\r
- Ia32/ExceptionHandlerAsm.asm\r
Ia32/ExceptionHandlerAsm.nasm\r
Ia32/ExceptionTssEntryAsm.nasm\r
Ia32/ExceptionHandlerAsm.S\r
Ia32/ArchInterruptDefs.h\r
\r
[Sources.X64]\r
- X64/ExceptionHandlerAsm.asm\r
X64/ExceptionHandlerAsm.nasm\r
X64/ExceptionHandlerAsm.S\r
X64/ArchExceptionHandler.c\r
## @file\r
# CPU Exception Handler library instance for SEC/PEI modules.\r
#\r
-# Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
#\r
\r
[Sources.Ia32]\r
- Ia32/ExceptionHandlerAsm.asm\r
Ia32/ExceptionHandlerAsm.nasm\r
Ia32/ExceptionTssEntryAsm.nasm\r
Ia32/ExceptionHandlerAsm.S\r
Ia32/ArchInterruptDefs.h\r
\r
[Sources.X64]\r
- X64/ExceptionHandlerAsm.asm\r
X64/ExceptionHandlerAsm.nasm\r
X64/ExceptionHandlerAsm.S\r
X64/ArchExceptionHandler.c\r
## @file\r
# CPU Exception Handler library instance for SMM modules.\r
#\r
-# Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
#\r
\r
[Sources.Ia32]\r
- Ia32/ExceptionHandlerAsm.asm\r
Ia32/ExceptionHandlerAsm.nasm\r
Ia32/ExceptionTssEntryAsm.nasm\r
Ia32/ExceptionHandlerAsm.S\r
Ia32/ArchInterruptDefs.h\r
\r
[Sources.X64]\r
- X64/ExceptionHandlerAsm.asm\r
X64/ExceptionHandlerAsm.nasm\r
X64/ExceptionHandlerAsm.S\r
X64/ArchExceptionHandler.c\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; ExceptionHandlerAsm.Asm\r
-;\r
-; Abstract:\r
-;\r
-; x64 CPU Exception Handler\r
-;\r
-; Notes:\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-;\r
-; CommonExceptionHandler()\r
-;\r
-externdef CommonExceptionHandler:near\r
-\r
-EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions\r
-EXTRN mDoFarReturnFlag:QWORD ; Do far return flag\r
-\r
-data SEGMENT\r
-\r
-.code\r
-\r
-ALIGN 8\r
-\r
-AsmIdtVectorBegin:\r
-REPEAT 32\r
- db 6ah ; push #VectorNum\r
- db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum\r
- push rax\r
- mov rax, CommonInterruptEntry\r
- jmp rax\r
-ENDM\r
-AsmIdtVectorEnd:\r
-\r
-HookAfterStubHeaderBegin:\r
- db 6ah ; push\r
-@VectorNum:\r
- db 0 ; 0 will be fixed\r
- push rax\r
- mov rax, HookAfterStubHeaderEnd\r
- jmp rax\r
-HookAfterStubHeaderEnd:\r
- mov rax, rsp\r
- and sp, 0fff0h ; make sure 16-byte aligned for exception context\r
- sub rsp, 18h ; reserve room for filling exception data later\r
- push rcx\r
- mov rcx, [rax + 8]\r
- bt mErrorCodeFlag, ecx\r
- jnc @F\r
- push [rsp] ; push additional rcx to make stack alignment\r
-@@:\r
- xchg rcx, [rsp] ; restore rcx, save Exception Number in stack\r
- push [rax] ; push rax into stack to keep code consistence\r
-\r
-;---------------------------------------;\r
-; CommonInterruptEntry ;\r
-;---------------------------------------;\r
-; The follow algorithm is used for the common interrupt routine.\r
-; Entry from each interrupt with a push eax and eax=interrupt number\r
-; Stack frame would be as follows as specified in IA32 manuals:\r
-;\r
-; +---------------------+ <-- 16-byte aligned ensured by processor\r
-; + Old SS +\r
-; +---------------------+\r
-; + Old RSP +\r
-; +---------------------+\r
-; + RFlags +\r
-; +---------------------+\r
-; + CS +\r
-; +---------------------+\r
-; + RIP +\r
-; +---------------------+\r
-; + Error Code +\r
-; +---------------------+\r
-; + Vector Number +\r
-; +---------------------+\r
-; + RBP +\r
-; +---------------------+ <-- RBP, 16-byte aligned\r
-; The follow algorithm is used for the common interrupt routine.\r
-CommonInterruptEntry PROC PUBLIC\r
- cli\r
- pop rax\r
- ;\r
- ; All interrupt handlers are invoked through interrupt gates, so\r
- ; IF flag automatically cleared at the entry point\r
- ;\r
- xchg rcx, [rsp] ; Save rcx into stack and save vector number into rcx\r
- and rcx, 0FFh\r
- cmp ecx, 32 ; Intel reserved vector for exceptions?\r
- jae NoErrorCode\r
- bt mErrorCodeFlag, ecx\r
- jc @F\r
-\r
-NoErrorCode:\r
-\r
- ;\r
- ; Push a dummy error code on the stack\r
- ; to maintain coherent stack map\r
- ;\r
- push [rsp]\r
- mov qword ptr [rsp + 8], 0\r
-@@:\r
- push rbp\r
- mov rbp, rsp\r
- push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler\r
- push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag\r
-\r
- ;\r
- ; Stack:\r
- ; +---------------------+ <-- 16-byte aligned ensured by processor\r
- ; + Old SS +\r
- ; +---------------------+\r
- ; + Old RSP +\r
- ; +---------------------+\r
- ; + RFlags +\r
- ; +---------------------+\r
- ; + CS +\r
- ; +---------------------+\r
- ; + RIP +\r
- ; +---------------------+\r
- ; + Error Code +\r
- ; +---------------------+\r
- ; + RCX / Vector Number +\r
- ; +---------------------+\r
- ; + RBP +\r
- ; +---------------------+ <-- RBP, 16-byte aligned\r
- ;\r
-\r
-\r
- ;\r
- ; Since here the stack pointer is 16-byte aligned, so\r
- ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64\r
- ; is 16-byte aligned\r
- ;\r
-\r
-;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
-;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
- push r15\r
- push r14\r
- push r13\r
- push r12\r
- push r11\r
- push r10\r
- push r9\r
- push r8\r
- push rax\r
- push qword ptr [rbp + 8] ; RCX\r
- push rdx\r
- push rbx\r
- push qword ptr [rbp + 48] ; RSP\r
- push qword ptr [rbp] ; RBP\r
- push rsi\r
- push rdi\r
-\r
-;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero\r
- movzx rax, word ptr [rbp + 56]\r
- push rax ; for ss\r
- movzx rax, word ptr [rbp + 32]\r
- push rax ; for cs\r
- mov rax, ds\r
- push rax\r
- mov rax, es\r
- push rax\r
- mov rax, fs\r
- push rax\r
- mov rax, gs\r
- push rax\r
-\r
- mov [rbp + 8], rcx ; save vector number\r
-\r
-;; UINT64 Rip;\r
- push qword ptr [rbp + 24]\r
-\r
-;; UINT64 Gdtr[2], Idtr[2];\r
- xor rax, rax\r
- push rax\r
- push rax\r
- sidt [rsp]\r
- xchg rax, [rsp + 2]\r
- xchg rax, [rsp]\r
- xchg rax, [rsp + 8]\r
-\r
- xor rax, rax\r
- push rax\r
- push rax\r
- sgdt [rsp]\r
- xchg rax, [rsp + 2]\r
- xchg rax, [rsp]\r
- xchg rax, [rsp + 8]\r
-\r
-;; UINT64 Ldtr, Tr;\r
- xor rax, rax\r
- str ax\r
- push rax\r
- sldt ax\r
- push rax\r
-\r
-;; UINT64 RFlags;\r
- push qword ptr [rbp + 40]\r
-\r
-;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
- mov rax, cr8\r
- push rax\r
- mov rax, cr4\r
- or rax, 208h\r
- mov cr4, rax\r
- push rax\r
- mov rax, cr3\r
- push rax\r
- mov rax, cr2\r
- push rax\r
- xor rax, rax\r
- push rax\r
- mov rax, cr0\r
- push rax\r
-\r
-;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
- mov rax, dr7\r
- push rax\r
- mov rax, dr6\r
- push rax\r
- mov rax, dr3\r
- push rax\r
- mov rax, dr2\r
- push rax\r
- mov rax, dr1\r
- push rax\r
- mov rax, dr0\r
- push rax\r
-\r
-;; FX_SAVE_STATE_X64 FxSaveState;\r
- sub rsp, 512\r
- mov rdi, rsp\r
- db 0fh, 0aeh, 07h ;fxsave [rdi]\r
-\r
-;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear\r
- cld\r
-\r
-;; UINT32 ExceptionData;\r
- push qword ptr [rbp + 16]\r
-\r
-;; Prepare parameter and call\r
- mov rcx, [rbp + 8]\r
- mov rdx, rsp\r
- ;\r
- ; Per X64 calling convention, allocate maximum parameter stack space\r
- ; and make sure RSP is 16-byte aligned\r
- ;\r
- sub rsp, 4 * 8 + 8\r
- mov rax, CommonExceptionHandler\r
- call rax\r
- add rsp, 4 * 8 + 8\r
-\r
- cli\r
-;; UINT64 ExceptionData;\r
- add rsp, 8\r
-\r
-;; FX_SAVE_STATE_X64 FxSaveState;\r
-\r
- mov rsi, rsp\r
- db 0fh, 0aeh, 0Eh ; fxrstor [rsi]\r
- add rsp, 512\r
-\r
-;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
-;; Skip restoration of DRx registers to support in-circuit emualators\r
-;; or debuggers set breakpoint in interrupt/exception context\r
- add rsp, 8 * 6\r
-\r
-;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
- pop rax\r
- mov cr0, rax\r
- add rsp, 8 ; not for Cr1\r
- pop rax\r
- mov cr2, rax\r
- pop rax\r
- mov cr3, rax\r
- pop rax\r
- mov cr4, rax\r
- pop rax\r
- mov cr8, rax\r
-\r
-;; UINT64 RFlags;\r
- pop qword ptr [rbp + 40]\r
-\r
-;; UINT64 Ldtr, Tr;\r
-;; UINT64 Gdtr[2], Idtr[2];\r
-;; Best not let anyone mess with these particular registers...\r
- add rsp, 48\r
-\r
-;; UINT64 Rip;\r
- pop qword ptr [rbp + 24]\r
-\r
-;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;\r
- pop rax\r
- ; mov gs, rax ; not for gs\r
- pop rax\r
- ; mov fs, rax ; not for fs\r
- ; (X64 will not use fs and gs, so we do not restore it)\r
- pop rax\r
- mov es, rax\r
- pop rax\r
- mov ds, rax\r
- pop qword ptr [rbp + 32] ; for cs\r
- pop qword ptr [rbp + 56] ; for ss\r
-\r
-;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
-;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
- pop rdi\r
- pop rsi\r
- add rsp, 8 ; not for rbp\r
- pop qword ptr [rbp + 48] ; for rsp\r
- pop rbx\r
- pop rdx\r
- pop rcx\r
- pop rax\r
- pop r8\r
- pop r9\r
- pop r10\r
- pop r11\r
- pop r12\r
- pop r13\r
- pop r14\r
- pop r15\r
-\r
- mov rsp, rbp\r
- pop rbp\r
- add rsp, 16\r
- cmp qword ptr [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler\r
- jz DoReturn\r
- cmp qword ptr [rsp - 40], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag\r
- jz ErrorCode\r
- jmp qword ptr [rsp - 32]\r
-ErrorCode:\r
- sub rsp, 8\r
- jmp qword ptr [rsp - 24]\r
-\r
-DoReturn:\r
- cmp mDoFarReturnFlag, 0 ; Check if need to do far return instead of IRET\r
- jz DoIret\r
- push rax\r
- mov rax, rsp ; save old RSP to rax\r
- mov rsp, [rsp + 20h]\r
- push [rax + 10h] ; save CS in new location\r
- push [rax + 8h] ; save EIP in new location\r
- push [rax + 18h] ; save EFLAGS in new location\r
- mov rax, [rax] ; restore rax\r
- popfq ; restore EFLAGS\r
- DB 48h ; prefix to composite "retq" with next "retf"\r
- retf ; far return\r
-DoIret:\r
- iretq\r
-\r
-CommonInterruptEntry ENDP\r
-\r
-;-------------------------------------------------------------------------------------\r
-; GetTemplateAddressMap (&AddressMap);\r
-;-------------------------------------------------------------------------------------\r
-; comments here for definition of address map\r
-AsmGetTemplateAddressMap PROC\r
- mov rax, offset AsmIdtVectorBegin\r
- mov qword ptr [rcx], rax\r
- mov qword ptr [rcx + 8h], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32\r
- mov rax, offset HookAfterStubHeaderBegin\r
- mov qword ptr [rcx + 10h], rax\r
- ret\r
-AsmGetTemplateAddressMap ENDP\r
-\r
-;-------------------------------------------------------------------------------------\r
-; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);\r
-;-------------------------------------------------------------------------------------\r
-AsmVectorNumFixup PROC\r
- mov rax, rdx\r
- mov [rcx + (@VectorNum - HookAfterStubHeaderBegin)], al\r
- ret\r
-AsmVectorNumFixup ENDP\r
-\r
-END\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; SmiEntry.asm\r
-;\r
-; Abstract:\r
-;\r
-; Code template of the SMI handler for a particular processor\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
- .686p\r
- .model flat,C\r
- .xmm\r
-\r
-MSR_IA32_MISC_ENABLE EQU 1A0h\r
-MSR_EFER EQU 0c0000080h\r
-MSR_EFER_XD EQU 0800h\r
-\r
-;\r
-; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR\r
-;\r
-DSC_OFFSET EQU 0fb00h\r
-DSC_GDTPTR EQU 48h\r
-DSC_GDTSIZ EQU 50h\r
-DSC_CS EQU 14h\r
-DSC_DS EQU 16h\r
-DSC_SS EQU 18h\r
-DSC_OTHERSEG EQU 1Ah\r
-\r
-PROTECT_MODE_CS EQU 08h\r
-PROTECT_MODE_DS EQU 20h\r
-TSS_SEGMENT EQU 40h\r
-\r
-SmiRendezvous PROTO C\r
-CpuSmmDebugEntry PROTO C\r
-CpuSmmDebugExit PROTO C\r
-\r
-EXTERNDEF gcStmSmiHandlerTemplate:BYTE\r
-EXTERNDEF gcStmSmiHandlerSize:WORD\r
-EXTERNDEF gcStmSmiHandlerOffset:WORD\r
-EXTERNDEF gStmSmiCr3:DWORD\r
-EXTERNDEF gStmSmiStack:DWORD\r
-EXTERNDEF gStmSmbase:DWORD\r
-EXTERNDEF gStmXdSupported:BYTE\r
-EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE\r
-EXTERNDEF gStmSmiHandlerIdtr:FWORD\r
-\r
- .code\r
-\r
-gcStmSmiHandlerTemplate LABEL BYTE\r
-\r
-_StmSmiEntryPoint:\r
- DB 0bbh ; mov bx, imm16\r
- DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h\r
- DB 2eh, 0a1h ; mov ax, cs:[offset16]\r
- DW DSC_OFFSET + DSC_GDTSIZ\r
- dec eax\r
- mov cs:[edi], eax ; mov cs:[bx], ax\r
- DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]\r
- DW DSC_OFFSET + DSC_GDTPTR\r
- mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax\r
- mov bp, ax ; ebp = GDT base\r
- DB 66h\r
- lgdt fword ptr cs:[edi] ; lgdt fword ptr cs:[bx]\r
-; Patch ProtectedMode Segment\r
- DB 0b8h ; mov ax, imm16\r
- DW PROTECT_MODE_CS ; set AX for segment directly\r
- mov cs:[edi - 2], eax ; mov cs:[bx - 2], ax\r
-; Patch ProtectedMode entry\r
- DB 66h, 0bfh ; mov edi, SMBASE\r
-gStmSmbase DD ?\r
- DB 67h\r
- lea ax, [edi + (@32bit - _StmSmiEntryPoint) + 8000h]\r
- mov cs:[edi - 6], ax ; mov cs:[bx - 6], eax\r
- mov ebx, cr0\r
- DB 66h\r
- and ebx, 9ffafff3h\r
- DB 66h\r
- or ebx, 23h\r
- mov cr0, ebx\r
- DB 66h, 0eah\r
- DD ?\r
- DW ?\r
-_StmGdtDesc FWORD ?\r
-\r
-@32bit:\r
- mov ax, PROTECT_MODE_DS\r
- mov ds, ax\r
- mov es, ax\r
- mov fs, ax\r
- mov gs, ax\r
- mov ss, ax\r
- DB 0bch ; mov esp, imm32\r
-gStmSmiStack DD ?\r
- mov eax, offset gStmSmiHandlerIdtr\r
- lidt fword ptr [eax]\r
- jmp ProtFlatMode\r
-\r
-ProtFlatMode:\r
- DB 0b8h ; mov eax, imm32\r
-gStmSmiCr3 DD ?\r
- mov cr3, eax\r
-;\r
-; Need to test for CR4 specific bit support\r
-;\r
- mov eax, 1\r
- cpuid ; use CPUID to determine if specific CR4 bits are supported\r
- xor eax, eax ; Clear EAX\r
- test edx, BIT2 ; Check for DE capabilities\r
- jz @f\r
- or eax, BIT3\r
-@@:\r
- test edx, BIT6 ; Check for PAE capabilities\r
- jz @f\r
- or eax, BIT5\r
-@@:\r
- test edx, BIT7 ; Check for MCE capabilities\r
- jz @f\r
- or eax, BIT6\r
-@@:\r
- test edx, BIT24 ; Check for FXSR capabilities\r
- jz @f\r
- or eax, BIT9\r
-@@:\r
- test edx, BIT25 ; Check for SSE capabilities\r
- jz @f\r
- or eax, BIT10\r
-@@: ; as cr4.PGE is not set here, refresh cr3\r
- mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r
-\r
- cmp FeaturePcdGet (PcdCpuSmmStackGuard), 0\r
- jz @F\r
-; Load TSS\r
- mov byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag\r
- mov eax, TSS_SEGMENT\r
- ltr ax\r
-@@:\r
-\r
-; enable NXE if supported\r
- DB 0b0h ; mov al, imm8\r
-gStmXdSupported DB 1\r
- cmp al, 0\r
- jz @SkipXd\r
-;\r
-; Check XD disable bit\r
-;\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- push edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
- jmp @XdDone\r
-@SkipXd:\r
- sub esp, 4\r
-@XdDone:\r
-\r
- mov ebx, cr0\r
- or ebx, 080010023h ; enable paging + WP + NE + MP + PE\r
- mov cr0, ebx\r
- lea ebx, [edi + DSC_OFFSET]\r
- mov ax, [ebx + DSC_DS]\r
- mov ds, eax\r
- mov ax, [ebx + DSC_OTHERSEG]\r
- mov es, eax\r
- mov fs, eax\r
- mov gs, eax\r
- mov ax, [ebx + DSC_SS]\r
- mov ss, eax\r
-\r
-CommonHandler:\r
- mov ebx, [esp + 4] ; CPU Index\r
- push ebx\r
- mov eax, CpuSmmDebugEntry\r
- call eax\r
- add esp, 4\r
-\r
- push ebx\r
- mov eax, SmiRendezvous\r
- call eax\r
- add esp, 4\r
-\r
- push ebx\r
- mov eax, CpuSmmDebugExit\r
- call eax\r
- add esp, 4\r
-\r
- mov eax, offset gStmXdSupported\r
- mov al, [eax]\r
- cmp al, 0\r
- jz @f\r
- pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2\r
- jz @f\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
- wrmsr\r
-\r
-@@:\r
- rsm\r
-\r
-_StmSmiHandler:\r
-;\r
-; Check XD disable bit\r
-;\r
- xor esi, esi\r
- mov eax, offset gStmXdSupported\r
- mov al, [eax]\r
- cmp al, 0\r
- jz @StmXdDone\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
-@StmXdDone:\r
- push esi\r
-\r
- ; below step is needed, because STM does not run above code.\r
- ; we have to run below code to set IDT/CR0/CR4\r
- mov eax, offset gStmSmiHandlerIdtr\r
- lidt fword ptr [eax]\r
-\r
-\r
- mov eax, cr0\r
- or eax, 80010023h ; enable paging + WP + NE + MP + PE\r
- mov cr0, eax\r
-;\r
-; Need to test for CR4 specific bit support\r
-;\r
- mov eax, 1\r
- cpuid ; use CPUID to determine if specific CR4 bits are supported\r
- mov eax, cr4 ; init EAX\r
- test edx, BIT2 ; Check for DE capabilities\r
- jz @f\r
- or eax, BIT3\r
-@@:\r
- test edx, BIT6 ; Check for PAE capabilities\r
- jz @f\r
- or eax, BIT5\r
-@@:\r
- test edx, BIT7 ; Check for MCE capabilities\r
- jz @f\r
- or eax, BIT6\r
-@@:\r
- test edx, BIT24 ; Check for FXSR capabilities\r
- jz @f\r
- or eax, BIT9\r
-@@:\r
- test edx, BIT25 ; Check for SSE capabilities\r
- jz @f\r
- or eax, BIT10\r
-@@: ; as cr4.PGE is not set here, refresh cr3\r
- mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r
- ; STM init finish\r
- jmp CommonHandler\r
-\r
-gcStmSmiHandlerSize DW $ - _StmSmiEntryPoint\r
-gcStmSmiHandlerOffset DW _StmSmiHandler - _StmSmiEntryPoint\r
-\r
- END\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; SmiException.asm\r
-;\r
-; Abstract:\r
-;\r
-; Exception handlers used in SM mode\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
- .686p\r
- .model flat,C\r
-\r
-EXTERNDEF gcStmPsd:BYTE\r
-\r
-EXTERNDEF SmmStmExceptionHandler:PROC\r
-EXTERNDEF SmmStmSetup:PROC\r
-EXTERNDEF SmmStmTeardown:PROC\r
-EXTERNDEF gStmXdSupported:BYTE\r
-\r
-CODE_SEL = 08h\r
-DATA_SEL = 20h\r
-TSS_SEL = 40h\r
-\r
-MSR_IA32_MISC_ENABLE EQU 1A0h\r
-MSR_EFER EQU 0c0000080h\r
-MSR_EFER_XD EQU 0800h\r
-\r
- .data\r
-\r
-gcStmPsd LABEL BYTE\r
- DB 'TXTPSSIG'\r
- DW PSD_SIZE\r
- DW 1 ; Version\r
- DD 0 ; LocalApicId\r
- DB 05h ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r
- DB 0 ; BIOS to STM\r
- DB 0 ; STM to BIOS\r
- DB 0\r
- DW CODE_SEL\r
- DW DATA_SEL\r
- DW DATA_SEL\r
- DW DATA_SEL\r
- DW TSS_SEL\r
- DW 0\r
- DQ 0 ; SmmCr3\r
- DQ _OnStmSetup\r
- DQ _OnStmTeardown\r
- DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint\r
- DQ 0 ; SmmSmiHandlerRsp\r
- DQ 0\r
- DD 0\r
- DD 80010100h ; RequiredStmSmmRevId\r
- DQ _OnException\r
- DQ 0 ; ExceptionStack\r
- DW DATA_SEL\r
- DW 01Fh ; ExceptionFilter\r
- DD 0\r
- DQ 0\r
- DQ 0 ; BiosHwResourceRequirementsPtr\r
- DQ 0 ; AcpiRsdp\r
- DB 0 ; PhysicalAddressBits\r
-PSD_SIZE = $ - offset gcStmPsd\r
-\r
- .code\r
-;------------------------------------------------------------------------------\r
-; SMM Exception handlers\r
-;------------------------------------------------------------------------------\r
-_OnException PROC\r
- mov ecx, esp\r
- push ecx\r
- call SmmStmExceptionHandler\r
- add esp, 4\r
-\r
- mov ebx, eax\r
- mov eax, 4\r
- DB 0fh, 01h, 0c1h ; VMCALL\r
- jmp $\r
-_OnException ENDP\r
-\r
-_OnStmSetup PROC\r
-;\r
-; Check XD disable bit\r
-;\r
- xor esi, esi\r
- mov eax, offset gStmXdSupported\r
- mov al, [eax]\r
- cmp al, 0\r
- jz @StmXdDone1\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
-@StmXdDone1:\r
- push esi\r
-\r
- call SmmStmSetup\r
-\r
- mov eax, offset gStmXdSupported\r
- mov al, [eax]\r
- cmp al, 0\r
- jz @f\r
- pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2\r
- jz @f\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
- wrmsr\r
-@@:\r
-\r
- rsm\r
-_OnStmSetup ENDP\r
-\r
-_OnStmTeardown PROC\r
-;\r
-; Check XD disable bit\r
-;\r
- xor esi, esi\r
- mov eax, offset gStmXdSupported\r
- mov al, [eax]\r
- cmp al, 0\r
- jz @StmXdDone2\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
-@StmXdDone2:\r
- push esi\r
-\r
- call SmmStmTeardown\r
-\r
- mov eax, offset gStmXdSupported\r
- mov al, [eax]\r
- cmp al, 0\r
- jz @f\r
- pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2\r
- jz @f\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
- wrmsr\r
-@@:\r
-\r
- rsm\r
-_OnStmTeardown ENDP\r
-\r
- END\r
# The CPU specific programming for PiSmmCpuDxeSmm module when STM support\r
# is included.\r
#\r
-# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
[Sources.Ia32]\r
Ia32/SmmStmSupport.c\r
\r
- Ia32/SmiEntry.asm\r
- Ia32/SmiException.asm\r
\r
Ia32/SmiEntry.nasm\r
Ia32/SmiException.nasm\r
[Sources.X64]\r
X64/SmmStmSupport.c\r
\r
- X64/SmiEntry.asm\r
- X64/SmiException.asm\r
\r
X64/SmiEntry.nasm\r
X64/SmiException.nasm\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; SmiEntry.asm\r
-;\r
-; Abstract:\r
-;\r
-; Code template of the SMI handler for a particular processor\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-;\r
-; Variables referenced by C code\r
-;\r
-EXTERNDEF SmiRendezvous:PROC\r
-EXTERNDEF CpuSmmDebugEntry:PROC\r
-EXTERNDEF CpuSmmDebugExit:PROC\r
-EXTERNDEF gcStmSmiHandlerTemplate:BYTE\r
-EXTERNDEF gcStmSmiHandlerSize:WORD\r
-EXTERNDEF gcStmSmiHandlerOffset:WORD\r
-EXTERNDEF gStmSmiCr3:DWORD\r
-EXTERNDEF gStmSmiStack:DWORD\r
-EXTERNDEF gStmSmbase:DWORD\r
-EXTERNDEF gStmXdSupported:BYTE\r
-EXTERNDEF gStmSmiHandlerIdtr:FWORD\r
-\r
-MSR_IA32_MISC_ENABLE EQU 1A0h\r
-MSR_EFER EQU 0c0000080h\r
-MSR_EFER_XD EQU 0800h\r
-\r
-;\r
-; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR\r
-;\r
-DSC_OFFSET EQU 0fb00h\r
-DSC_GDTPTR EQU 48h\r
-DSC_GDTSIZ EQU 50h\r
-DSC_CS EQU 14h\r
-DSC_DS EQU 16h\r
-DSC_SS EQU 18h\r
-DSC_OTHERSEG EQU 1ah\r
-;\r
-; Constants relating to CPU State Save Area\r
-;\r
-SSM_DR6 EQU 0ffd0h\r
-SSM_DR7 EQU 0ffc8h\r
-\r
-PROTECT_MODE_CS EQU 08h\r
-PROTECT_MODE_DS EQU 20h\r
-LONG_MODE_CS EQU 38h\r
-TSS_SEGMENT EQU 40h\r
-GDT_SIZE EQU 50h\r
-\r
- .code\r
-\r
-gcStmSmiHandlerTemplate LABEL BYTE\r
-\r
-_StmSmiEntryPoint:\r
- ;\r
- ; The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-\r
- ; bit addressing mode. And that coincidence has been used in the following\r
- ; "64-bit like" 16-bit code. Be aware that once RDI is referenced as a\r
- ; base address register, it is actually BX that is referenced.\r
- ;\r
- DB 0bbh ; mov bx, imm16\r
- DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc offset\r
-; fix GDT descriptor\r
- DB 2eh, 0a1h ; mov ax, cs:[offset16]\r
- DW DSC_OFFSET + DSC_GDTSIZ\r
- DB 48h ; dec ax\r
- DB 2eh\r
- mov [rdi], eax ; mov cs:[bx], ax\r
- DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]\r
- DW DSC_OFFSET + DSC_GDTPTR\r
- DB 2eh\r
- mov [rdi + 2], ax ; mov cs:[bx + 2], eax\r
- DB 66h, 2eh\r
- lgdt fword ptr [rdi] ; lgdt fword ptr cs:[bx]\r
-; Patch ProtectedMode Segment\r
- DB 0b8h ; mov ax, imm16\r
- DW PROTECT_MODE_CS ; set AX for segment directly\r
- DB 2eh\r
- mov [rdi - 2], eax ; mov cs:[bx - 2], ax\r
-; Patch ProtectedMode entry\r
- DB 66h, 0bfh ; mov edi, SMBASE\r
-gStmSmbase DD ?\r
- lea ax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 8000h]\r
- DB 2eh\r
- mov [rdi - 6], ax ; mov cs:[bx - 6], eax\r
-; Switch into @ProtectedMode\r
- mov rbx, cr0\r
- DB 66h\r
- and ebx, 9ffafff3h\r
- DB 66h\r
- or ebx, 00000023h\r
-\r
- mov cr0, rbx\r
- DB 66h, 0eah\r
- DD ?\r
- DW ?\r
-\r
-_StmGdtDesc FWORD ?\r
-@ProtectedMode:\r
- mov ax, PROTECT_MODE_DS\r
- mov ds, ax\r
- mov es, ax\r
- mov fs, ax\r
- mov gs, ax\r
- mov ss, ax\r
- DB 0bch ; mov esp, imm32\r
-gStmSmiStack DD ?\r
- jmp ProtFlatMode\r
-\r
-ProtFlatMode:\r
- DB 0b8h ; mov eax, offset gStmSmiCr3\r
-gStmSmiCr3 DD ?\r
- mov cr3, rax\r
- mov eax, 668h ; as cr4.PGE is not set here, refresh cr3\r
- mov cr4, rax ; in PreModifyMtrrs() to flush TLB.\r
-; Load TSS\r
- sub esp, 8 ; reserve room in stack\r
- sgdt fword ptr [rsp]\r
- mov eax, [rsp + 2] ; eax = GDT base\r
- add esp, 8\r
- mov dl, 89h\r
- mov [rax + TSS_SEGMENT + 5], dl ; clear busy flag\r
- mov eax, TSS_SEGMENT\r
- ltr ax\r
-\r
-; enable NXE if supported\r
- DB 0b0h ; mov al, imm8\r
-gStmXdSupported DB 1\r
- cmp al, 0\r
- jz @SkipXd\r
-;\r
-; Check XD disable bit\r
-;\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- sub esp, 4\r
- push rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
- jmp @XdDone\r
-@SkipXd:\r
- sub esp, 8\r
-@XdDone:\r
-\r
-; Switch into @LongMode\r
- push LONG_MODE_CS ; push cs hardcore here\r
- call Base ; push return address for retf later\r
-Base:\r
- add dword ptr [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg\r
-\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ah, 1 ; enable LME\r
- wrmsr\r
- mov rbx, cr0\r
- or ebx, 080010023h ; enable paging + WP + NE + MP + PE\r
- mov cr0, rbx\r
- retf\r
-@LongMode: ; long mode (64-bit code) starts here\r
- mov rax, offset gStmSmiHandlerIdtr\r
- lidt fword ptr [rax]\r
- lea ebx, [rdi + DSC_OFFSET]\r
- mov ax, [rbx + DSC_DS]\r
- mov ds, eax\r
- mov ax, [rbx + DSC_OTHERSEG]\r
- mov es, eax\r
- mov fs, eax\r
- mov gs, eax\r
- mov ax, [rbx + DSC_SS]\r
- mov ss, eax\r
-\r
-CommonHandler:\r
- mov rbx, [rsp + 0x08] ; rbx <- CpuIndex\r
-\r
- ;\r
- ; Save FP registers\r
- ;\r
- sub rsp, 200h\r
- DB 48h ; FXSAVE64\r
- fxsave [rsp]\r
-\r
- add rsp, -20h\r
-\r
- mov rcx, rbx\r
- mov rax, CpuSmmDebugEntry\r
- call rax\r
-\r
- mov rcx, rbx\r
- mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous\r
- call rax\r
-\r
- mov rcx, rbx\r
- mov rax, CpuSmmDebugExit\r
- call rax\r
-\r
- add rsp, 20h\r
-\r
- ;\r
- ; Restore FP registers\r
- ;\r
- DB 48h ; FXRSTOR64\r
- fxrstor [rsp]\r
-\r
- add rsp, 200h\r
-\r
- mov rax, offset ASM_PFX(gStmXdSupported)\r
- mov al, [rax]\r
- cmp al, 0\r
- jz @f\r
- pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2\r
- jz @f\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
- wrmsr\r
-\r
-@@:\r
- rsm\r
-\r
-_StmSmiHandler:\r
-;\r
-; Check XD disable bit\r
-;\r
- xor r8, r8\r
- mov rax, offset ASM_PFX(gStmXdSupported)\r
- mov al, [rax]\r
- cmp al, 0\r
- jz @StmXdDone\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
-@StmXdDone:\r
- push r8\r
-\r
- ; below step is needed, because STM does not run above code.\r
- ; we have to run below code to set IDT/CR0/CR4\r
- mov rax, offset gStmSmiHandlerIdtr\r
- lidt fword ptr [rax]\r
-\r
- mov rax, cr0\r
- or eax, 80010023h ; enable paging + WP + NE + MP + PE\r
- mov cr0, rax\r
- mov rax, cr4\r
- mov eax, 668h ; as cr4.PGE is not set here, refresh cr3\r
- mov cr4, rax ; in PreModifyMtrrs() to flush TLB.\r
- ; STM init finish\r
- jmp CommonHandler\r
-\r
-gcStmSmiHandlerSize DW $ - _StmSmiEntryPoint\r
-gcStmSmiHandlerOffset DW _StmSmiHandler - _StmSmiEntryPoint\r
-\r
- END\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; SmiException.asm\r
-;\r
-; Abstract:\r
-;\r
-; Exception handlers used in SM mode\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-EXTERNDEF gcStmPsd:BYTE\r
-\r
-EXTERNDEF SmmStmExceptionHandler:PROC\r
-EXTERNDEF SmmStmSetup:PROC\r
-EXTERNDEF SmmStmTeardown:PROC\r
-EXTERNDEF gStmXdSupported:BYTE\r
-\r
-CODE_SEL EQU 38h\r
-DATA_SEL EQU 20h\r
-TR_SEL EQU 40h\r
-\r
-MSR_IA32_MISC_ENABLE EQU 1A0h\r
-MSR_EFER EQU 0c0000080h\r
-MSR_EFER_XD EQU 0800h\r
-\r
- .data\r
-\r
-;\r
-; This structure serves as a template for all processors.\r
-;\r
-gcStmPsd LABEL BYTE\r
- DB 'TXTPSSIG'\r
- DW PSD_SIZE\r
- DW 1 ; Version\r
- DD 0 ; LocalApicId\r
- DB 0Fh ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r
- DB 0 ; BIOS to STM\r
- DB 0 ; STM to BIOS\r
- DB 0\r
- DW CODE_SEL\r
- DW DATA_SEL\r
- DW DATA_SEL\r
- DW DATA_SEL\r
- DW TR_SEL\r
- DW 0\r
- DQ 0 ; SmmCr3\r
- DQ _OnStmSetup\r
- DQ _OnStmTeardown\r
- DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint\r
- DQ 0 ; SmmSmiHandlerRsp\r
- DQ 0\r
- DD 0\r
- DD 80010100h ; RequiredStmSmmRevId\r
- DQ _OnException\r
- DQ 0 ; ExceptionStack\r
- DW DATA_SEL\r
- DW 01Fh ; ExceptionFilter\r
- DD 0\r
- DQ 0\r
- DQ 0 ; BiosHwResourceRequirementsPtr\r
- DQ 0 ; AcpiRsdp\r
- DB 0 ; PhysicalAddressBits\r
-PSD_SIZE = $ - offset gcStmPsd\r
-\r
- .code\r
-;------------------------------------------------------------------------------\r
-; SMM Exception handlers\r
-;------------------------------------------------------------------------------\r
-_OnException PROC\r
- mov rcx, rsp\r
- add rsp, -28h\r
- call SmmStmExceptionHandler\r
- add rsp, 28h\r
- mov ebx, eax\r
- mov eax, 4\r
- DB 0fh, 01h, 0c1h ; VMCALL\r
- jmp $\r
-_OnException ENDP\r
-\r
-_OnStmSetup PROC\r
-;\r
-; Check XD disable bit\r
-;\r
- xor r8, r8\r
- mov rax, offset ASM_PFX(gStmXdSupported)\r
- mov al, [rax]\r
- cmp al, 0\r
- jz @StmXdDone1\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
-@StmXdDone1:\r
- push r8\r
-\r
- add rsp, -20h\r
- call SmmStmSetup\r
- add rsp, 20h\r
-\r
- mov rax, offset ASM_PFX(gStmXdSupported)\r
- mov al, [rax]\r
- cmp al, 0\r
- jz @f\r
- pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2\r
- jz @f\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
- wrmsr\r
-@@:\r
-\r
- rsm\r
-_OnStmSetup ENDP\r
-\r
-_OnStmTeardown PROC\r
-;\r
-; Check XD disable bit\r
-;\r
- xor r8, r8\r
- mov rax, offset ASM_PFX(gStmXdSupported)\r
- mov al, [rax]\r
- cmp al, 0\r
- jz @StmXdDone2\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz @f\r
- and dx, 0FFFBh ; clear XD Disable bit if it is set\r
- wrmsr\r
-@@:\r
- mov ecx, MSR_EFER\r
- rdmsr\r
- or ax, MSR_EFER_XD ; enable NXE\r
- wrmsr\r
-@StmXdDone2:\r
- push r8\r
-\r
- add rsp, -20h\r
- call SmmStmTeardown\r
- add rsp, 20h\r
-\r
- mov rax, offset ASM_PFX(gStmXdSupported)\r
- mov al, [rax]\r
- cmp al, 0\r
- jz @f\r
- pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
- test edx, BIT2\r
- jz @f\r
- mov ecx, MSR_IA32_MISC_ENABLE\r
- rdmsr\r
- or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
- wrmsr\r
-@@:\r
-\r
- rsm\r
-_OnStmTeardown ENDP\r
-\r
- END\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#*\r
-#* Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>\r
-#* This program and the accompanying materials\r
-#* are licensed and made available under the terms and conditions of the BSD License\r
-#* which accompanies this distribution. The full text of the license may be found at\r
-#* http://opensource.org/licenses/bsd-license.php\r
-#*\r
-#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#*\r
-#* AsmFuncs.S\r
-#*\r
-#* Abstract:\r
-#*\r
-#* Assembly function to set segment selectors.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-.text\r
-\r
-#------------------------------------------------------------------------------\r
-# \r
-# VOID\r
-# EFIAPI\r
-# AsmSetDataSelectors (\r
-# IN UINT16 SelectorValue\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(AsmSetDataSelectors)\r
-ASM_PFX(AsmSetDataSelectors):\r
- movl 4(%esp), %eax\r
- movw %ax, %ss\r
- movw %ax, %ds\r
- movw %ax, %es\r
- movw %ax, %fs\r
- movw %ax, %gs \r
- ret\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; AsmFuncs.Asm\r
-;\r
-; Abstract:\r
-;\r
-; Assembly function to set segment selectors.\r
-;\r
-; Notes:\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-.686\r
-.model flat,C\r
-\r
-.code\r
-\r
-;------------------------------------------------------------------------------\r
-; VOID\r
-; EFIAPI\r
-; AsmSetDataSelectors (\r
-; IN UINT16 SelectorValue\r
-; );\r
-;------------------------------------------------------------------------------\r
-AsmSetDataSelectors PROC near public\r
- mov eax, [esp + 4]\r
- mov ds, ax\r
- mov es, ax\r
- mov fs, ax\r
- mov gs, ax\r
- mov ss, ax \r
- ret\r
-AsmSetDataSelectors ENDP\r
-\r
-END\r
S3Resume.c\r
\r
[Sources.IA32]\r
- Ia32/AsmFuncs.asm\r
Ia32/AsmFuncs.nasm\r
- Ia32/AsmFuncs.S\r
\r
[Sources.X64]\r
- X64/AsmFuncs.asm\r
X64/AsmFuncs.nasm\r
- X64/AsmFuncs.S\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#*\r
-#* Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>\r
-#* This program and the accompanying materials\r
-#* are licensed and made available under the terms and conditions of the BSD License\r
-#* which accompanies this distribution. The full text of the license may be found at\r
-#* http://opensource.org/licenses/bsd-license.php\r
-#*\r
-#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#*\r
-#* AsmFuncs.S\r
-#*\r
-#* Abstract:\r
-#*\r
-#* Assembly function to set segment selectors.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-.text\r
-\r
-#------------------------------------------------------------------------------\r
-# \r
-# VOID\r
-# EFIAPI\r
-# AsmSetDataSelectors (\r
-# IN UINT16 SelectorValue\r
-# );\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(AsmSetDataSelectors)\r
-ASM_PFX(AsmSetDataSelectors):\r
- movw %cx, %ss\r
- movw %cx, %ds\r
- movw %cx, %es\r
- movw %cx, %fs\r
- movw %cx, %gs \r
- ret\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; AsmFuncs.Asm\r
-;\r
-; Abstract:\r
-;\r
-; Assembly function to set segment selectors.\r
-;\r
-; Notes:\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-.code\r
-\r
-;------------------------------------------------------------------------------\r
-; VOID\r
-; EFIAPI\r
-; AsmSetDataSelectors (\r
-; IN UINT16 SelectorValue\r
-; );\r
-;------------------------------------------------------------------------------\r
-AsmSetDataSelectors PROC\r
- mov ds, cx\r
- mov es, cx\r
- mov fs, cx\r
- mov gs, cx\r
- mov ss, cx \r
- ret\r
-AsmSetDataSelectors ENDP\r
-\r
-END\r
projects / mirror_edk2.git / commitdiff