RefRefine soma code to make code run safely.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10885 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/PcAtChipsetPkg/8254TimerDxe/Timer.c b/PcAtChipsetPkg/8254TimerDxe/Timer.c
index b57ccda72774068b28f9685c10f3d485ddde2c89..da7d6af57806ff753a7010cc31949d53dedcb57f 100644 (file)
--- a/PcAtChipsetPkg/8254TimerDxe/Timer.c
+++ b/PcAtChipsetPkg/8254TimerDxe/Timer.c
@@ -69,7 +69,7 @@ SetPitCount (
 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  8254 Timer #0 Interrupt Handler\r
+  8254 Timer #0 Interrupt Handler.\r

 \r
   @param InterruptType    The type of interrupt that occured\r
   @param SystemContext    A pointer to the system context when the interrupt occured\r
 \r
   @param InterruptType    The type of interrupt that occured\r
   @param SystemContext    A pointer to the system context when the interrupt occured\r


@@ -87,9 +87,9 @@ TimerInterruptHandler (
 \r
   mLegacy8259->EndOfInterrupt (mLegacy8259, Efi8259Irq0);\r
 \r
 \r
   mLegacy8259->EndOfInterrupt (mLegacy8259, Efi8259Irq0);\r
 \r

-  if (mTimerNotifyFunction) {\r
+  if (mTimerNotifyFunction != NULL) {\r

     //\r
     //\r

-    // BUGBUG : This does not handle missed timer interrupts\r
+    // @bug : This does not handle missed timer interrupts\r

     //\r
     mTimerNotifyFunction (mTimerPeriod);\r
   }\r
     //\r
     mTimerNotifyFunction (mTimerPeriod);\r
   }\r


@@ -311,9 +311,9 @@ TimerDriverGenerateSoftInterrupt (
     //\r
     OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
 \r
     //\r
     OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
 \r

-    if (mTimerNotifyFunction) {\r
+    if (mTimerNotifyFunction != NULL) {\r

       //\r
       //\r

-      // BUGBUG : This does not handle missed timer interrupts\r
+      // @bug : This does not handle missed timer interrupts\r

       //\r
       mTimerNotifyFunction (mTimerPeriod);\r
     }\r
       //\r
       mTimerNotifyFunction (mTimerPeriod);\r
     }\r

diff --git a/PcAtChipsetPkg/8254TimerDxe/Timer.h b/PcAtChipsetPkg/8254TimerDxe/Timer.h
index 53de04fb7ecc8daa7237388e1a99a4b7a22c8f97..26935d8775416f28a9f1d618d6f21a6a24132ddc 100644 (file)
--- a/PcAtChipsetPkg/8254TimerDxe/Timer.h
+++ b/PcAtChipsetPkg/8254TimerDxe/Timer.h
@@ -78,7 +78,7 @@ TimerDriverInitialize (
 \r
 \r
   @param This            The EFI_TIMER_ARCH_PROTOCOL instance.\r
 \r
 \r
   @param This            The EFI_TIMER_ARCH_PROTOCOL instance.\r

-  @param TimerPeriod     The rate to program the timer interrupt in 100 nS units.  If\r
+  @param NotifyFunction  The rate to program the timer interrupt in 100 nS units.  If\r

                          the timer hardware is not programmable, then EFI_UNSUPPORTED is\r
                          returned.  If the timer is programmable, then the timer period\r
                          will be rounded up to the nearest timer period that is supported\r
                          the timer hardware is not programmable, then EFI_UNSUPPORTED is\r
                          returned.  If the timer is programmable, then the timer period\r
                          will be rounded up to the nearest timer period that is supported\r

diff --git a/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c b/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c
index 7b9067f89ad7d3603705d57955279f9f7cea7d03..3defe0ed08b9115045fad1074e7de3442434707d 100644 (file)
--- a/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c
+++ b/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c
@@ -17,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 //\r
 // Global for the Legacy 8259 Protocol that is produced by this driver\r
 //\r
 //\r
 // Global for the Legacy 8259 Protocol that is produced by this driver\r
 //\r

-EFI_LEGACY_8259_PROTOCOL  m8259 = {\r
+EFI_LEGACY_8259_PROTOCOL  mInterrupt8259 = {\r

   Interrupt8259SetVectorBase,\r
   Interrupt8259GetMask,\r
   Interrupt8259SetMask,\r
   Interrupt8259SetVectorBase,\r
   Interrupt8259GetMask,\r
   Interrupt8259SetMask,\r


@@ -592,13 +592,13 @@ Install8259 (
   // Clear all pending interrupt\r
   //\r
   for (Irq = Efi8259Irq0; Irq <= Efi8259Irq15; Irq++) {\r
   // Clear all pending interrupt\r
   //\r
   for (Irq = Efi8259Irq0; Irq <= Efi8259Irq15; Irq++) {\r

-    Interrupt8259EndOfInterrupt (&m8259, Irq);\r
+    Interrupt8259EndOfInterrupt (&mInterrupt8259, Irq);\r

   }\r
 \r
   //\r
   // Set the 8259 Master base to 0x68 and the 8259 Slave base to 0x70\r
   //\r
   }\r
 \r
   //\r
   // Set the 8259 Master base to 0x68 and the 8259 Slave base to 0x70\r
   //\r

-  Status = Interrupt8259SetVectorBase (&m8259, PROTECTED_MODE_BASE_VECTOR_MASTER, PROTECTED_MODE_BASE_VECTOR_SLAVE);\r
+  Status = Interrupt8259SetVectorBase (&mInterrupt8259, PROTECTED_MODE_BASE_VECTOR_MASTER, PROTECTED_MODE_BASE_VECTOR_SLAVE);\r

 \r
   //\r
   // Set all 8259 interrupts to edge triggered and disabled\r
 \r
   //\r
   // Set all 8259 interrupts to edge triggered and disabled\r


@@ -612,7 +612,7 @@ Install8259 (
                   &m8259Handle,\r
                   &gEfiLegacy8259ProtocolGuid,\r
                   EFI_NATIVE_INTERFACE,\r
                   &m8259Handle,\r
                   &gEfiLegacy8259ProtocolGuid,\r
                   EFI_NATIVE_INTERFACE,\r

-                  &m8259\r
+                  &mInterrupt8259\r

                   );\r
   return Status;\r
 }\r
                   );\r
   return Status;\r
 }\r

diff --git a/PcAtChipsetPkg/8259InterruptControllerDxe/8259.h b/PcAtChipsetPkg/8259InterruptControllerDxe/8259.h
index fff068a0dfad24e9fee025743573c38a2645c2b1..0d4c1e8223540244169c0cb1425ae45c2e04356a 100644 (file)
--- a/PcAtChipsetPkg/8259InterruptControllerDxe/8259.h
+++ b/PcAtChipsetPkg/8259InterruptControllerDxe/8259.h
@@ -47,7 +47,17 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 // Protocol Function Prototypes\r
 \r
 \r
 // Protocol Function Prototypes\r
 \r

+/**\r
+  Sets the base address for the 8259 master and slave PICs.\r

 \r
 \r

+  @param[in]  This        Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r
+  @param[in]  MasterBase  Interrupt vectors for IRQ0-IRQ7.\r
+  @param[in]  SlaveBase   Interrupt vectors for IRQ8-IRQ15.\r
+\r
+  @retval  EFI_SUCCESS       The 8259 PIC was programmed successfully.\r
+  @retval  EFI_DEVICE_ERROR  There was an error while writing to the 8259 PIC.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259SetVectorBase (\r
 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259SetVectorBase (\r


@@ -56,6 +66,19 @@ Interrupt8259SetVectorBase (
   IN UINT8                     SlaveBase\r
   );\r
 \r
   IN UINT8                     SlaveBase\r
   );\r
 \r

+/**\r
+  Gets the current 16-bit real mode and 32-bit protected-mode IRQ masks.\r
+\r
+  @param[in]   This                Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r
+  @param[out]  LegacyMask          16-bit mode interrupt mask for IRQ0-IRQ15.\r
+  @param[out]  LegacyEdgeLevel     16-bit mode edge/level mask for IRQ-IRQ15.\r
+  @param[out]  ProtectedMask       32-bit mode interrupt mask for IRQ0-IRQ15.\r
+  @param[out]  ProtectedEdgeLevel  32-bit mode edge/level mask for IRQ0-IRQ15.\r
+\r
+  @retval  EFI_SUCCESS       The 8259 PIC was programmed successfully.\r
+  @retval  EFI_DEVICE_ERROR  There was an error while reading the 8259 PIC.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259GetMask (\r
 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259GetMask (\r


@@ -66,6 +89,19 @@ Interrupt8259GetMask (
   OUT UINT16                    *ProtectedEdgeLevel OPTIONAL\r
   );\r
 \r
   OUT UINT16                    *ProtectedEdgeLevel OPTIONAL\r
   );\r
 \r

+/**\r
+  Sets the current 16-bit real mode and 32-bit protected-mode IRQ masks.\r
+\r
+  @param[in]  This                Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r
+  @param[in]  LegacyMask          16-bit mode interrupt mask for IRQ0-IRQ15.\r
+  @param[in]  LegacyEdgeLevel     16-bit mode edge/level mask for IRQ-IRQ15.\r
+  @param[in]  ProtectedMask       32-bit mode interrupt mask for IRQ0-IRQ15.\r
+  @param[in]  ProtectedEdgeLevel  32-bit mode edge/level mask for IRQ0-IRQ15.\r
+\r
+  @retval  EFI_SUCCESS       The 8259 PIC was programmed successfully.\r
+  @retval  EFI_DEVICE_ERROR  There was an error while writing the 8259 PIC.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259SetMask (\r
 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259SetMask (\r


@@ -76,6 +112,18 @@ Interrupt8259SetMask (
   IN UINT16                    *ProtectedEdgeLevel OPTIONAL\r
   );\r
 \r
   IN UINT16                    *ProtectedEdgeLevel OPTIONAL\r
   );\r
 \r

+/**\r
+  Sets the mode of the PICs.\r
+\r
+  @param[in]  This       Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r
+  @param[in]  Mode       16-bit real or 32-bit protected mode.\r
+  @param[in]  Mask       The value with which to set the interrupt mask.\r
+  @param[in]  EdgeLevel  The value with which to set the edge/level mask.\r
+\r
+  @retval  EFI_SUCCESS            The mode was set successfully.\r
+  @retval  EFI_INVALID_PARAMETER  The mode was not set.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259SetMode (\r
 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259SetMode (\r


@@ -85,6 +133,17 @@ Interrupt8259SetMode (
   IN UINT16                    *EdgeLevel OPTIONAL\r
   );\r
 \r
   IN UINT16                    *EdgeLevel OPTIONAL\r
   );\r
 \r

+/**\r
+  Translates the IRQ into a vector.\r
+\r
+  @param[in]   This    Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r
+  @param[in]   Irq     IRQ0-IRQ15.\r
+  @param[out]  Vector  The vector that is assigned to the IRQ.\r
+\r
+  @retval  EFI_SUCCESS            The Vector that matches Irq was returned.\r
+  @retval  EFI_INVALID_PARAMETER  Irq is not valid.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259GetVector (\r
 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259GetVector (\r


@@ -93,6 +152,17 @@ Interrupt8259GetVector (
   OUT UINT8                     *Vector\r
   );\r
 \r
   OUT UINT8                     *Vector\r
   );\r
 \r

+/**\r
+  Enables the specified IRQ.\r
+\r
+  @param[in]  This            Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r
+  @param[in]  Irq             IRQ0-IRQ15.\r
+  @param[in]  LevelTriggered  0 = Edge triggered; 1 = Level triggered.\r
+\r
+  @retval  EFI_SUCCESS            The Irq was enabled on the 8259 PIC.\r
+  @retval  EFI_INVALID_PARAMETER  The Irq is not valid.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259EnableIrq (\r
 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259EnableIrq (\r


@@ -101,6 +171,16 @@ Interrupt8259EnableIrq (
   IN BOOLEAN                   LevelTriggered\r
   );\r
 \r
   IN BOOLEAN                   LevelTriggered\r
   );\r
 \r

+/**\r
+  Disables the specified IRQ.\r
+\r
+  @param[in]  This  Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r
+  @param[in]  Irq   IRQ0-IRQ15.\r
+\r
+  @retval  EFI_SUCCESS            The Irq was disabled on the 8259 PIC.\r
+  @retval  EFI_INVALID_PARAMETER  The Irq is not valid.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259DisableIrq (\r
 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259DisableIrq (\r


@@ -108,6 +188,16 @@ Interrupt8259DisableIrq (
   IN EFI_8259_IRQ              Irq\r
   );\r
 \r
   IN EFI_8259_IRQ              Irq\r
   );\r
 \r

+/**\r
+  Reads the PCI configuration space to get the interrupt number that is assigned to the card.\r
+\r
+  @param[in]   This       Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r
+  @param[in]   PciHandle  PCI function for which to return the vector.\r
+  @param[out]  Vector     IRQ number that corresponds to the interrupt line.\r
+\r
+  @retval  EFI_SUCCESS  The interrupt line value was read successfully.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259GetInterruptLine (\r
 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259GetInterruptLine (\r


@@ -116,6 +206,16 @@ Interrupt8259GetInterruptLine (
   OUT UINT8                     *Vector\r
   );\r
 \r
   OUT UINT8                     *Vector\r
   );\r
 \r

+/**\r
+  Issues the End of Interrupt (EOI) commands to PICs.\r
+\r
+  @param[in]  This  Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r
+  @param[in]  Irq   The interrupt for which to issue the EOI command.\r
+\r
+  @retval  EFI_SUCCESS            The EOI command was issued.\r
+  @retval  EFI_INVALID_PARAMETER  The Irq is not valid.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259EndOfInterrupt (\r
 EFI_STATUS\r
 EFIAPI\r
 Interrupt8259EndOfInterrupt (\r

diff --git a/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/ComponentName.c b/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/ComponentName.c
index 5e56a62f4730031c2c133ff2d0c12f056acbbef7..a78bed7572ef3305ddcac39a42d3af4b0c5d55c9 100644 (file)
--- a/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/ComponentName.c
+++ b/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/ComponentName.c
@@ -107,7 +107,7 @@ IdeControllerComponentNameGetDriverName (
   @param ControllerHandle       The handle of a controller that the driver specified by\r
                                 This is managing.  This handle specifies the controller\r
                                 whose name is to be returned.\r
   @param ControllerHandle       The handle of a controller that the driver specified by\r
                                 This is managing.  This handle specifies the controller\r
                                 whose name is to be returned.\r

-  @param OPTIONAL               The handle of the child controller to retrieve the name\r
+  @param ChildHandle OPTIONAL   The handle of the child controller to retrieve the name\r

                                 of.  This is an optional parameter that may be NULL.  It\r
                                 will be NULL for device drivers.  It will also be NULL\r
                                 for a bus drivers that wish to retrieve the name of the\r
                                 of.  This is an optional parameter that may be NULL.  It\r
                                 will be NULL for device drivers.  It will also be NULL\r
                                 for a bus drivers that wish to retrieve the name of the\r

diff --git a/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeController.h b/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeController.h
index 581361d24f3b8f08449177ee4e9811d23873a4b0..79763496ee7df9fc991066a652e6a9798866cf3f 100644 (file)
--- a/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeController.h
+++ b/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeController.h
@@ -12,8 +12,8 @@
 \r
 **/\r
 \r
 \r
 **/\r
 \r

-#ifndef _IDE_CONTROLLER_H\r
-#define _IDE_CONTROLLER_H\r
+#ifndef _IDE_CONTROLLER_H_\r
+#define _IDE_CONTROLLER_H_\r

 \r
 #include <Uefi.h>\r
 #include <Protocol/ComponentName.h>\r
 \r
 #include <Uefi.h>\r
 #include <Protocol/ComponentName.h>\r


@@ -155,7 +155,7 @@ EFIAPI
 IdeInitNotifyPhase (\r
   IN  EFI_IDE_CONTROLLER_INIT_PROTOCOL  *This,\r
   IN  EFI_IDE_CONTROLLER_ENUM_PHASE     Phase,\r
 IdeInitNotifyPhase (\r
   IN  EFI_IDE_CONTROLLER_INIT_PROTOCOL  *This,\r
   IN  EFI_IDE_CONTROLLER_ENUM_PHASE     Phase,\r

-  OUT UINT8                             Channel\r
+  IN  UINT8                             Channel\r

   )\r
 ;\r
 \r
   )\r
 ;\r
 \r


@@ -219,7 +219,7 @@ IdeInitCalculateMode (
   IN  EFI_IDE_CONTROLLER_INIT_PROTOCOL  *This,\r
   IN  UINT8                             Channel,\r
   IN  UINT8                             Device,\r
   IN  EFI_IDE_CONTROLLER_INIT_PROTOCOL  *This,\r
   IN  UINT8                             Channel,\r
   IN  UINT8                             Device,\r

-  IN  EFI_ATA_COLLECTIVE_MODE           **SupportedModes\r
+  OUT EFI_ATA_COLLECTIVE_MODE           **SupportedModes\r

   )\r
 ;\r
 \r
   )\r
 ;\r
 \r


@@ -285,7 +285,7 @@ IdeControllerComponentNameGetDriverName (
   @param ControllerHandle       The handle of a controller that the driver specified by\r
                                 This is managing.  This handle specifies the controller\r
                                 whose name is to be returned.\r
   @param ControllerHandle       The handle of a controller that the driver specified by\r
                                 This is managing.  This handle specifies the controller\r
                                 whose name is to be returned.\r

-  @param OPTIONAL               The handle of the child controller to retrieve the name\r
+  @param OPTIONAL   ChildHandle The handle of the child controller to retrieve the name\r

                                 of.  This is an optional parameter that may be NULL.  It\r
                                 will be NULL for device drivers.  It will also be NULL\r
                                 for a bus drivers that wish to retrieve the name of the\r
                                 of.  This is an optional parameter that may be NULL.  It\r
                                 will be NULL for device drivers.  It will also be NULL\r
                                 for a bus drivers that wish to retrieve the name of the\r

diff --git a/PcAtChipsetPkg/IsaAcpiDxe/PcatIsaAcpi.c b/PcAtChipsetPkg/IsaAcpiDxe/PcatIsaAcpi.c
index 468f193955b23392dfd5a860021802903ce469aa..8e6d8b7f828f03ed8553b9d1bfe531d4602a5dfe 100644 (file)
--- a/PcAtChipsetPkg/IsaAcpiDxe/PcatIsaAcpi.c
+++ b/PcAtChipsetPkg/IsaAcpiDxe/PcatIsaAcpi.c
@@ -242,7 +242,7 @@ PcatIsaAcpiDriverBindingStart (
 \r
 Done:\r
   if (EFI_ERROR (Status)) {\r
 \r
 Done:\r
   if (EFI_ERROR (Status)) {\r

-    if (PciIo) {\r
+    if (PciIo != NULL) {\r

       PciIo->Attributes (\r
                PciIo, \r
                EfiPciIoAttributeOperationDisable, \r
       PciIo->Attributes (\r
                PciIo, \r
                EfiPciIoAttributeOperationDisable, \r

diff --git a/PcAtChipsetPkg/KbcResetDxe/ResetEntry.c b/PcAtChipsetPkg/KbcResetDxe/ResetEntry.c
index 0457fe63b541b05dff37c2f24259be78e9da2af2..03b425019d511ce7818b9d324b836472d6c7c78f 100644 (file)
--- a/PcAtChipsetPkg/KbcResetDxe/ResetEntry.c
+++ b/PcAtChipsetPkg/KbcResetDxe/ResetEntry.c
@@ -63,7 +63,7 @@ KbcResetSystem (
 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Initialize the state information for the Reset Architectural Protocol\r
+  Initialize the state information for the Reset Architectural Protocol.\r

 \r
   @param ImageHandle     Handle of the loaded driver \r
   @param SystemTable     Pointer to the System Table\r
 \r
   @param ImageHandle     Handle of the loaded driver \r
   @param SystemTable     Pointer to the System Table\r

diff --git a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c b/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c
index 3c39f37432e3c42f646239175d2f518fbfbf810e..6bf705312d88fd6f9624f954053575e1f7b21e3f 100644 (file)
--- a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c
+++ b/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c
@@ -137,7 +137,7 @@ SerialPortWrite (
 \r
   Result = NumberOfBytes;\r
 \r
 \r
   Result = NumberOfBytes;\r
 \r

-  while (NumberOfBytes--) {\r
+  while ((NumberOfBytes--) != 0) {\r

     //\r
     // Wait for the serail port to be ready.\r
     //\r
     //\r
     // Wait for the serail port to be ready.\r
     //\r


@@ -178,7 +178,7 @@ SerialPortRead (
 \r
   Result = NumberOfBytes;\r
 \r
 \r
   Result = NumberOfBytes;\r
 \r

-  while (NumberOfBytes--) {\r
+  while ((NumberOfBytes--) != 0) {\r

     //\r
     // Wait for the serail port to be ready.\r
     //\r
     //\r
     // Wait for the serail port to be ready.\r
     //\r

diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
index 659c01e57a7f0a464c2e872c81812e5d81bd7da9..6c7e0ca6d77517f33efaa4d9f233ae99766fa7c4 100644 (file)
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
@@ -382,7 +382,7 @@ PcRtcSetTime (
   // Read Register B, and inhibit updates of the RTC\r
   //\r
   RegisterB.Data      = RtcRead (RTC_ADDRESS_REGISTER_B);\r
   // Read Register B, and inhibit updates of the RTC\r
   //\r
   RegisterB.Data      = RtcRead (RTC_ADDRESS_REGISTER_B);\r

-  RegisterB.Bits.SET  = 1;\r
+  RegisterB.Bits.Set  = 1;\r

   RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data);\r
 \r
   ConvertEfiTimeToRtcTime (&RtcTime, RegisterB, &Century);\r
   RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data);\r
 \r
   ConvertEfiTimeToRtcTime (&RtcTime, RegisterB, &Century);\r


@@ -398,7 +398,7 @@ PcRtcSetTime (
   //\r
   // Allow updates of the RTC registers\r
   //\r
   //\r
   // Allow updates of the RTC registers\r
   //\r

-  RegisterB.Bits.SET = 0;\r
+  RegisterB.Bits.Set = 0;\r

   RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data);\r
 \r
   //\r
   RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data);\r
 \r
   //\r


@@ -488,7 +488,7 @@ PcRtcGetWakeupTime (
   //\r
   // Get the Time/Date/Daylight Savings values.\r
   //\r
   //\r
   // Get the Time/Date/Daylight Savings values.\r
   //\r

-  *Enabled = RegisterB.Bits.AIE;\r
+  *Enabled = RegisterB.Bits.Aie;\r

   if (*Enabled) {\r
     Time->Second  = RtcRead (RTC_ADDRESS_SECONDS_ALARM);\r
     Time->Minute  = RtcRead (RTC_ADDRESS_MINUTES_ALARM);\r
   if (*Enabled) {\r
     Time->Second  = RtcRead (RTC_ADDRESS_SECONDS_ALARM);\r
     Time->Minute  = RtcRead (RTC_ADDRESS_MINUTES_ALARM);\r


@@ -531,7 +531,7 @@ PcRtcGetWakeupTime (
     return EFI_DEVICE_ERROR;\r
   }\r
 \r
     return EFI_DEVICE_ERROR;\r
   }\r
 \r

-  *Pending = RegisterC.Bits.AF;\r
+  *Pending = RegisterC.Bits.Af;\r

 \r
   return EFI_SUCCESS;\r
 }\r
 \r
   return EFI_SUCCESS;\r
 }\r


@@ -614,7 +614,7 @@ PcRtcSetWakeupTime (
   //\r
   RegisterB.Data      = RtcRead (RTC_ADDRESS_REGISTER_B);\r
 \r
   //\r
   RegisterB.Data      = RtcRead (RTC_ADDRESS_REGISTER_B);\r
 \r

-  RegisterB.Bits.SET  = 1;\r
+  RegisterB.Bits.Set  = 1;\r

   RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data);\r
 \r
   if (Enable) {\r
   RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data);\r
 \r
   if (Enable) {\r


@@ -627,15 +627,15 @@ PcRtcSetWakeupTime (
     RtcWrite (RTC_ADDRESS_MINUTES_ALARM, RtcTime.Minute);\r
     RtcWrite (RTC_ADDRESS_HOURS_ALARM, RtcTime.Hour);\r
 \r
     RtcWrite (RTC_ADDRESS_MINUTES_ALARM, RtcTime.Minute);\r
     RtcWrite (RTC_ADDRESS_HOURS_ALARM, RtcTime.Hour);\r
 \r

-    RegisterB.Bits.AIE = 1;\r
+    RegisterB.Bits.Aie = 1;\r

 \r
   } else {\r
 \r
   } else {\r

-    RegisterB.Bits.AIE = 0;\r
+    RegisterB.Bits.Aie = 0;\r

   }\r
   //\r
   // Allow updates of the RTC registers\r
   //\r
   }\r
   //\r
   // Allow updates of the RTC registers\r
   //\r

-  RegisterB.Bits.SET = 0;\r
+  RegisterB.Bits.Set = 0;\r

   RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data);\r
 \r
   //\r
   RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data);\r
 \r
   //\r


@@ -707,7 +707,7 @@ ConvertRtcTimeToEfiTime (
 \r
   Time->Hour = (UINT8) (Time->Hour & 0x7f);\r
 \r
 \r
   Time->Hour = (UINT8) (Time->Hour & 0x7f);\r
 \r

-  if (RegisterB.Bits.DM == 0) {\r
+  if (RegisterB.Bits.Dm == 0) {\r

     Time->Year    = CheckAndConvertBcd8ToDecimal8 ((UINT8) Time->Year);\r
     Time->Month   = CheckAndConvertBcd8ToDecimal8 (Time->Month);\r
     Time->Day     = CheckAndConvertBcd8ToDecimal8 (Time->Day);\r
     Time->Year    = CheckAndConvertBcd8ToDecimal8 ((UINT8) Time->Year);\r
     Time->Month   = CheckAndConvertBcd8ToDecimal8 (Time->Month);\r
     Time->Day     = CheckAndConvertBcd8ToDecimal8 (Time->Day);\r


@@ -728,7 +728,7 @@ ConvertRtcTimeToEfiTime (
   //\r
   // If time is in 12 hour format, convert it to 24 hour format\r
   //\r
   //\r
   // If time is in 12 hour format, convert it to 24 hour format\r
   //\r

-  if (RegisterB.Bits.MIL == 0) {\r
+  if (RegisterB.Bits.Mil == 0) {\r

     if (IsPM && Time->Hour < 12) {\r
       Time->Hour = (UINT8) (Time->Hour + 12);\r
     }\r
     if (IsPM && Time->Hour < 12) {\r
       Time->Hour = (UINT8) (Time->Hour + 12);\r
     }\r


@@ -764,7 +764,7 @@ RtcWaitToUpdate (
   //\r
   RegisterD.Data = RtcRead (RTC_ADDRESS_REGISTER_D);\r
 \r
   //\r
   RegisterD.Data = RtcRead (RTC_ADDRESS_REGISTER_D);\r
 \r

-  if (RegisterD.Bits.VRT == 0) {\r
+  if (RegisterD.Bits.Vrt == 0) {\r

     return EFI_DEVICE_ERROR;\r
   }\r
   //\r
     return EFI_DEVICE_ERROR;\r
   }\r
   //\r


@@ -772,14 +772,14 @@ RtcWaitToUpdate (
   //\r
   Timeout         = (Timeout / 10) + 1;\r
   RegisterA.Data  = RtcRead (RTC_ADDRESS_REGISTER_A);\r
   //\r
   Timeout         = (Timeout / 10) + 1;\r
   RegisterA.Data  = RtcRead (RTC_ADDRESS_REGISTER_A);\r

-  while (RegisterA.Bits.UIP == 1 && Timeout > 0) {\r
+  while (RegisterA.Bits.Uip == 1 && Timeout > 0) {\r

     MicroSecondDelay (10);\r
     RegisterA.Data = RtcRead (RTC_ADDRESS_REGISTER_A);\r
     Timeout--;\r
   }\r
 \r
   RegisterD.Data = RtcRead (RTC_ADDRESS_REGISTER_D);\r
     MicroSecondDelay (10);\r
     RegisterA.Data = RtcRead (RTC_ADDRESS_REGISTER_A);\r
     Timeout--;\r
   }\r
 \r
   RegisterD.Data = RtcRead (RTC_ADDRESS_REGISTER_D);\r

-  if (Timeout == 0 || RegisterD.Bits.VRT == 0) {\r
+  if (Timeout == 0 || RegisterD.Bits.Vrt == 0) {\r

     return EFI_DEVICE_ERROR;\r
   }\r
 \r
     return EFI_DEVICE_ERROR;\r
   }\r
 \r


@@ -914,7 +914,7 @@ ConvertEfiTimeToRtcTime (
   //\r
   // Adjust hour field if RTC is in 12 hour mode\r
   //\r
   //\r
   // Adjust hour field if RTC is in 12 hour mode\r
   //\r

-  if (RegisterB.Bits.MIL == 0) {\r
+  if (RegisterB.Bits.Mil == 0) {\r

     if (Time->Hour < 12) {\r
       IsPM = FALSE;\r
     }\r
     if (Time->Hour < 12) {\r
       IsPM = FALSE;\r
     }\r


@@ -932,7 +932,7 @@ ConvertEfiTimeToRtcTime (
 \r
   Time->Year  = (UINT16) (Time->Year % 100);\r
 \r
 \r
   Time->Year  = (UINT16) (Time->Year % 100);\r
 \r

-  if (RegisterB.Bits.DM == 0) {\r
+  if (RegisterB.Bits.Dm == 0) {\r

     Time->Year    = DecimalToBcd8 ((UINT8) Time->Year);\r
     Time->Month   = DecimalToBcd8 (Time->Month);\r
     Time->Day     = DecimalToBcd8 (Time->Day);\r
     Time->Year    = DecimalToBcd8 ((UINT8) Time->Year);\r
     Time->Month   = DecimalToBcd8 (Time->Month);\r
     Time->Day     = DecimalToBcd8 (Time->Day);\r


@@ -943,7 +943,7 @@ ConvertEfiTimeToRtcTime (
   //\r
   // If we are in 12 hour mode and PM is set, then set bit 7 of the Hour field.\r
   //\r
   //\r
   // If we are in 12 hour mode and PM is set, then set bit 7 of the Hour field.\r
   //\r

-  if (RegisterB.Bits.MIL == 0 && IsPM) {\r
+  if (RegisterB.Bits.Mil == 0 && IsPM) {\r

     Time->Hour = (UINT8) (Time->Hour | 0x80);\r
   }\r
 }\r
     Time->Hour = (UINT8) (Time->Hour | 0x80);\r
   }\r
 }\r

diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
index 85492f7b5972a861cebeca9c78f025dac5dd4042..d38c8e1464a4e88c644f57a19e99b87347b24c95 100644 (file)
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
@@ -84,9 +84,9 @@ typedef struct {
 // Register A\r
 //\r
 typedef struct {\r
 // Register A\r
 //\r
 typedef struct {\r

-  UINT8 RS : 4;   // Rate Selection Bits\r
-  UINT8 DV : 3;   // Divisor\r
-  UINT8 UIP : 1;  // Update in progress\r
+  UINT8 Rs : 4;   // Rate Selection Bits\r
+  UINT8 Dv : 3;   // Divisor\r
+  UINT8 Uip : 1;  // Update in progress\r

 } RTC_REGISTER_A_BITS;\r
 \r
 typedef union {\r
 } RTC_REGISTER_A_BITS;\r
 \r
 typedef union {\r


@@ -98,14 +98,14 @@ typedef union {
 // Register B\r
 //\r
 typedef struct {\r
 // Register B\r
 //\r
 typedef struct {\r

-  UINT8 DSE : 1;  // 0 - Daylight saving disabled  1 - Daylight savings enabled\r
-  UINT8 MIL : 1;  // 0 - 12 hour mode              1 - 24 hour mode\r
-  UINT8 DM : 1;   // 0 - BCD Format                1 - Binary Format\r
-  UINT8 SQWE : 1; // 0 - Disable SQWE output       1 - Enable SQWE output\r
-  UINT8 UIE : 1;  // 0 - Update INT disabled       1 - Update INT enabled\r
-  UINT8 AIE : 1;  // 0 - Alarm INT disabled        1 - Alarm INT Enabled\r
-  UINT8 PIE : 1;  // 0 - Periodic INT disabled     1 - Periodic INT Enabled\r
-  UINT8 SET : 1;  // 0 - Normal operation.         1 - Updates inhibited\r
+  UINT8 Dse : 1;  // 0 - Daylight saving disabled  1 - Daylight savings enabled\r
+  UINT8 Mil : 1;  // 0 - 12 hour mode              1 - 24 hour mode\r
+  UINT8 Dm : 1;   // 0 - BCD Format                1 - Binary Format\r
+  UINT8 Sqwe : 1; // 0 - Disable SQWE output       1 - Enable SQWE output\r
+  UINT8 Uie : 1;  // 0 - Update INT disabled       1 - Update INT enabled\r
+  UINT8 Aie : 1;  // 0 - Alarm INT disabled        1 - Alarm INT Enabled\r
+  UINT8 Pie : 1;  // 0 - Periodic INT disabled     1 - Periodic INT Enabled\r
+  UINT8 Set : 1;  // 0 - Normal operation.         1 - Updates inhibited\r

 } RTC_REGISTER_B_BITS;\r
 \r
 typedef union {\r
 } RTC_REGISTER_B_BITS;\r
 \r
 typedef union {\r


@@ -118,10 +118,10 @@ typedef union {
 //\r
 typedef struct {\r
   UINT8 Reserved : 4; // Read as zero.  Can not be written.\r
 //\r
 typedef struct {\r
   UINT8 Reserved : 4; // Read as zero.  Can not be written.\r

-  UINT8 UF : 1;       // Update End Interrupt Flag\r
-  UINT8 AF : 1;       // Alarm Interrupt Flag\r
-  UINT8 PF : 1;       // Periodic Interrupt Flag\r
-  UINT8 IRQF : 1;     // Iterrupt Request Flag = PF & PIE | AF & AIE | UF & UIE\r
+  UINT8 Uf : 1;       // Update End Interrupt Flag\r
+  UINT8 Af : 1;       // Alarm Interrupt Flag\r
+  UINT8 Pf : 1;       // Periodic Interrupt Flag\r
+  UINT8 Irqf : 1;     // Iterrupt Request Flag = PF & PIE | AF & AIE | UF & UIE\r

 } RTC_REGISTER_C_BITS;\r
 \r
 typedef union {\r
 } RTC_REGISTER_C_BITS;\r
 \r
 typedef union {\r


@@ -134,7 +134,7 @@ typedef union {
 //\r
 typedef struct {\r
   UINT8 Reserved : 7; // Read as zero.  Can not be written.\r
 //\r
 typedef struct {\r
   UINT8 Reserved : 7; // Read as zero.  Can not be written.\r

-  UINT8 VRT : 1;      // Valid RAM and Time\r
+  UINT8 Vrt : 1;      // Valid RAM and Time\r

 } RTC_REGISTER_D_BITS;\r
 \r
 typedef union {\r
 } RTC_REGISTER_D_BITS;\r
 \r
 typedef union {\r

diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
index b05b4153492ce2b1be5055a72414bd595bf3d217..27a54461cde281d9c4df6670678ed6b093b39239 100644 (file)
--- a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
+++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
@@ -67,6 +67,7 @@ PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
 //\r
 // Implementation\r
 //\r
 //\r
 // Implementation\r
 //\r

+\r

 /**\r
   Entry point of this driver\r
 \r
 /**\r
   Entry point of this driver\r
 \r


@@ -200,7 +201,7 @@ InitializePciHostBridge (
                                           required here. This notification can be used to perform any chipsetspecific\r
                                           programming.\r
 \r
                                           required here. This notification can be used to perform any chipsetspecific\r
                                           programming.\r
 \r

-   @param[in] PciResAlloc         The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+   @param[in] This                The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r

    @param[in] Phase               The phase during enumeration\r
 \r
    @retval EFI_NOT_READY          This phase cannot be entered at this time. For example, this error\r
    @param[in] Phase               The phase during enumeration\r
 \r
    @retval EFI_NOT_READY          This phase cannot be entered at this time. For example, this error\r


@@ -309,7 +310,7 @@ NotifyPhase(
             //\r
             // Get the number of '1' in Alignment.\r
             //\r
             //\r
             // Get the number of '1' in Alignment.\r
             //\r

-            BitsOfAlignment = HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1;\r
+            BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);\r

                                   \r
             switch (Index) {\r
 \r
                                   \r
             switch (Index) {\r
 \r


@@ -485,7 +486,7 @@ NotifyPhase(
    For D945 implementation, there is only one root bridge in PCI host bridge.\r
 \r
    @param[in]       This              The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
    For D945 implementation, there is only one root bridge in PCI host bridge.\r
 \r
    @param[in]       This              The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r

-   @param[in][out]  RootBridgeHandle  Returns the device handle of the next PCI root bridge.\r
+   @param[in, out]  RootBridgeHandle  Returns the device handle of the next PCI root bridge.\r

    \r
    @retval EFI_SUCCESS            If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
                                   specific Host bridge and return EFI_SUCCESS. \r
    \r
    @retval EFI_SUCCESS            If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
                                   specific Host bridge and return EFI_SUCCESS. \r


@@ -835,7 +836,7 @@ SubmitResources(
   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
   UINT8                                 *Temp;\r
   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
   UINT8                                 *Temp;\r

-  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *ptr;\r
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;\r

   UINT64                                AddrLen;\r
   UINT64                                Alignment;\r
   \r
   UINT64                                AddrLen;\r
   UINT64                                Alignment;\r
   \r


@@ -862,30 +863,30 @@ SubmitResources(
     RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
     if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
       while ( *Temp == 0x8A) {\r
     RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
     if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
       while ( *Temp == 0x8A) {\r

-        ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
+        Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r

 \r
         //\r
         // Check Address Length\r
         //\r
 \r
         //\r
         // Check Address Length\r
         //\r

-        if (ptr->AddrLen > 0xffffffff) {\r
+        if (Ptr->AddrLen > 0xffffffff) {\r

           return EFI_INVALID_PARAMETER;\r
         }\r
 \r
         //\r
         // Check address range alignment\r
         //\r
           return EFI_INVALID_PARAMETER;\r
         }\r
 \r
         //\r
         // Check address range alignment\r
         //\r

-        if (ptr->AddrRangeMax >= 0xffffffff || ptr->AddrRangeMax != (GetPowerOfTwo64 (ptr->AddrRangeMax + 1) - 1)) {\r
+        if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {\r

           return EFI_INVALID_PARAMETER;\r
         }\r
         \r
           return EFI_INVALID_PARAMETER;\r
         }\r
         \r

-        switch (ptr->ResType) {\r
+        switch (Ptr->ResType) {\r

 \r
         case 0:\r
             \r
           //\r
           // Check invalid Address Sapce Granularity\r
           //\r
 \r
         case 0:\r
             \r
           //\r
           // Check invalid Address Sapce Granularity\r
           //\r

-          if (ptr->AddrSpaceGranularity != 32) {\r
+          if (Ptr->AddrSpaceGranularity != 32) {\r

             return EFI_INVALID_PARAMETER;\r
           }\r
             \r
             return EFI_INVALID_PARAMETER;\r
           }\r
             \r


@@ -893,14 +894,14 @@ SubmitResources(
           // check the memory resource request is supported by PCI root bridge\r
           //\r
           if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&\r
           // check the memory resource request is supported by PCI root bridge\r
           //\r
           if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&\r

-               ptr->SpecificFlag == 0x06) {\r
+               Ptr->SpecificFlag == 0x06) {\r

             return EFI_INVALID_PARAMETER;\r
           }\r
             \r
             return EFI_INVALID_PARAMETER;\r
           }\r
             \r

-          AddrLen = ptr->AddrLen;\r
-          Alignment = ptr->AddrRangeMax;\r
-          if (ptr->AddrSpaceGranularity == 32) {\r
-            if (ptr->SpecificFlag == 0x06) {\r
+          AddrLen = Ptr->AddrLen;\r
+          Alignment = Ptr->AddrRangeMax;\r
+          if (Ptr->AddrSpaceGranularity == 32) {\r
+            if (Ptr->SpecificFlag == 0x06) {\r

               //\r
               // Apply from GCD\r
               //\r
               //\r
               // Apply from GCD\r
               //\r


@@ -913,8 +914,8 @@ SubmitResources(
             }\r
           }\r
 \r
             }\r
           }\r
 \r

-          if (ptr->AddrSpaceGranularity == 64) {\r
-            if (ptr->SpecificFlag == 0x06) {\r
+          if (Ptr->AddrSpaceGranularity == 64) {\r
+            if (Ptr->SpecificFlag == 0x06) {\r

               RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;\r
             } else {\r
               RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;\r
               RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;\r
             } else {\r
               RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;\r


@@ -923,8 +924,8 @@ SubmitResources(
           break;\r
 \r
         case 1:\r
           break;\r
 \r
         case 1:\r

-          AddrLen = (UINTN)ptr->AddrLen;\r
-          Alignment = (UINTN)ptr->AddrRangeMax;\r
+          AddrLen = (UINTN) Ptr->AddrLen;\r
+          Alignment = (UINTN) Ptr->AddrRangeMax;\r

           RootBridgeInstance->ResAllocNode[TypeIo].Length  = AddrLen;\r
           RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r
           RootBridgeInstance->ResAllocNode[TypeIo].Status  = ResRequested;\r
           RootBridgeInstance->ResAllocNode[TypeIo].Length  = AddrLen;\r
           RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r
           RootBridgeInstance->ResAllocNode[TypeIo].Status  = ResRequested;\r


@@ -982,7 +983,7 @@ GetProposedResources(
   UINTN                                 Number; \r
   VOID                                  *Buffer; \r
   UINT8                                 *Temp;\r
   UINTN                                 Number; \r
   VOID                                  *Buffer; \r
   UINT8                                 *Temp;\r

-  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *ptr;\r
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;\r

   UINT64                                ResStatus;\r
     \r
   Buffer = NULL;\r
   UINT64                                ResStatus;\r
     \r
   Buffer = NULL;\r


@@ -1017,7 +1018,7 @@ GetProposedResources(
       Temp = Buffer;\r
       for (Index = 0; Index < TypeBus; Index ++) {\r
         if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
       Temp = Buffer;\r
       for (Index = 0; Index < TypeBus; Index ++) {\r
         if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r

-          ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
+          Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r

           ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r
           \r
           switch (Index) {\r
           ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r
           \r
           switch (Index) {\r


@@ -1026,81 +1027,81 @@ GetProposedResources(
             //\r
             // Io\r
             //\r
             //\r
             // Io\r
             //\r

-            ptr->Desc = 0x8A;\r
-            ptr->Len  = 0x2B;\r
-            ptr->ResType = 1;\r
-            ptr->GenFlag = 0; \r
-            ptr->SpecificFlag = 0;\r
-            ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
-            ptr->AddrRangeMax = 0;\r
-            ptr->AddrTranslationOffset = \\r
+            Ptr->Desc = 0x8A;\r
+            Ptr->Len  = 0x2B;\r
+            Ptr->ResType = 1;\r
+            Ptr->GenFlag = 0; \r
+            Ptr->SpecificFlag = 0;\r
+            Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+            Ptr->AddrRangeMax = 0;\r
+            Ptr->AddrTranslationOffset = \\r

                  (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
                  (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r

-            ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+            Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r

             break;\r
 \r
           case TypeMem32:\r
             //\r
             // Memory 32\r
             // \r
             break;\r
 \r
           case TypeMem32:\r
             //\r
             // Memory 32\r
             // \r

-            ptr->Desc = 0x8A;\r
-            ptr->Len  = 0x2B;\r
-            ptr->ResType = 0;\r
-            ptr->GenFlag = 0; \r
-            ptr->SpecificFlag = 0;\r
-            ptr->AddrSpaceGranularity = 32;\r
-            ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
-            ptr->AddrRangeMax = 0;\r
-            ptr->AddrTranslationOffset = \\r
+            Ptr->Desc = 0x8A;\r
+            Ptr->Len  = 0x2B;\r
+            Ptr->ResType = 0;\r
+            Ptr->GenFlag = 0; \r
+            Ptr->SpecificFlag = 0;\r
+            Ptr->AddrSpaceGranularity = 32;\r
+            Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+            Ptr->AddrRangeMax = 0;\r
+            Ptr->AddrTranslationOffset = \\r

                  (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;              \r
                  (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;              \r

-            ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+            Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r

             break;\r
 \r
           case TypePMem32:\r
             //\r
             // Prefetch memory 32\r
             //\r
             break;\r
 \r
           case TypePMem32:\r
             //\r
             // Prefetch memory 32\r
             //\r

-            ptr->Desc = 0x8A;\r
-            ptr->Len  = 0x2B;\r
-            ptr->ResType = 0;\r
-            ptr->GenFlag = 0; \r
-            ptr->SpecificFlag = 6;\r
-            ptr->AddrSpaceGranularity = 32;\r
-            ptr->AddrRangeMin = 0;\r
-            ptr->AddrRangeMax = 0;\r
-            ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;       \r
-            ptr->AddrLen = 0;\r
+            Ptr->Desc = 0x8A;\r
+            Ptr->Len  = 0x2B;\r
+            Ptr->ResType = 0;\r
+            Ptr->GenFlag = 0; \r
+            Ptr->SpecificFlag = 6;\r
+            Ptr->AddrSpaceGranularity = 32;\r
+            Ptr->AddrRangeMin = 0;\r
+            Ptr->AddrRangeMax = 0;\r
+            Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;       \r
+            Ptr->AddrLen = 0;\r

             break;\r
 \r
           case TypeMem64:\r
             //\r
             // Memory 64\r
             //\r
             break;\r
 \r
           case TypeMem64:\r
             //\r
             // Memory 64\r
             //\r

-            ptr->Desc = 0x8A;\r
-            ptr->Len  = 0x2B;\r
-            ptr->ResType = 0;\r
-            ptr->GenFlag = 0; \r
-            ptr->SpecificFlag = 0;\r
-            ptr->AddrSpaceGranularity = 64;\r
-            ptr->AddrRangeMin = 0;\r
-            ptr->AddrRangeMax = 0;\r
-            ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;       \r
-            ptr->AddrLen = 0;\r
+            Ptr->Desc = 0x8A;\r
+            Ptr->Len  = 0x2B;\r
+            Ptr->ResType = 0;\r
+            Ptr->GenFlag = 0; \r
+            Ptr->SpecificFlag = 0;\r
+            Ptr->AddrSpaceGranularity = 64;\r
+            Ptr->AddrRangeMin = 0;\r
+            Ptr->AddrRangeMax = 0;\r
+            Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;       \r
+            Ptr->AddrLen = 0;\r

             break;\r
 \r
           case TypePMem64:\r
             //\r
             // Prefetch memory 64\r
             //\r
             break;\r
 \r
           case TypePMem64:\r
             //\r
             // Prefetch memory 64\r
             //\r

-            ptr->Desc = 0x8A;\r
-            ptr->Len  = 0x2B;\r
-            ptr->ResType = 0;\r
-            ptr->GenFlag = 0; \r
-            ptr->SpecificFlag = 6;\r
-            ptr->AddrSpaceGranularity = 64;\r
-            ptr->AddrRangeMin = 0;\r
-            ptr->AddrRangeMax = 0;\r
-            ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;       \r
-            ptr->AddrLen = 0;\r
+            Ptr->Desc = 0x8A;\r
+            Ptr->Len  = 0x2B;\r
+            Ptr->ResType = 0;\r
+            Ptr->GenFlag = 0; \r
+            Ptr->SpecificFlag = 6;\r
+            Ptr->AddrSpaceGranularity = 64;\r
+            Ptr->AddrRangeMin = 0;\r
+            Ptr->AddrRangeMax = 0;\r
+            Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;       \r
+            Ptr->AddrLen = 0;\r

             break;\r
           };\r
           \r
             break;\r
           };\r
           \r


@@ -1128,7 +1129,6 @@ GetProposedResources(
   @param RootBridge      Point to PCI root bridge.\r
   @param PciAddress      The specific device PCI address\r
 **/\r
   @param RootBridge      Point to PCI root bridge.\r
   @param PciAddress      The specific device PCI address\r
 **/\r

-STATIC\r

 VOID\r
 UpdateRootBridgeAttributes (\r
   IN  PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge,\r
 VOID\r
 UpdateRootBridgeAttributes (\r
   IN  PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge,\r


@@ -1256,7 +1256,7 @@ UpdateRootBridgeAttributes (
 EFI_STATUS\r
 EFIAPI\r
 PreprocessController (\r
 EFI_STATUS\r
 EFIAPI\r
 PreprocessController (\r

-  IN  struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *This,\r
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL          *This,\r

   IN  EFI_HANDLE                                                RootBridgeHandle,\r
   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS               PciAddress,\r
   IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE              Phase\r
   IN  EFI_HANDLE                                                RootBridgeHandle,\r
   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS               PciAddress,\r
   IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE              Phase\r

diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h
index 42a3d591c00b53c43d7240eefb0b5d8e916e5594..f81982985a08ad91c6ac0a79caa7a7b7bee3f199 100644 (file)
--- a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h
+++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h
@@ -66,20 +66,75 @@ typedef struct {
 \r
 #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r
   CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r
 \r
 #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r
   CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r

-\r
-//\r
-// Driver Entry Point\r
-//\r
-EFI_STATUS\r
-EFIAPI\r
-EfiMain (\r
-  IN EFI_HANDLE       ImageHandle,\r
-  IN EFI_SYSTEM_TABLE *SystemTable\r
-  );\r

   \r
 //\r
 //  HostBridge Resource Allocation interface\r
 //\r
   \r
 //\r
 //  HostBridge Resource Allocation interface\r
 //\r

+\r
+/**\r
+   These are the notifications from the PCI bus driver that it is about to enter a certain\r
+   phase of the PCI enumeration process.\r
+\r
+   This member function can be used to notify the host bridge driver to perform specific actions,\r
+   including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
+   Eight notification points are defined at this time. See belows:\r
+   EfiPciHostBridgeBeginEnumeration       Resets the host bridge PCI apertures and internal data\r
+                                          structures. The PCI enumerator should issue this notification\r
+                                          before starting a fresh enumeration process. Enumeration cannot\r
+                                          be restarted after sending any other notification such as\r
+                                          EfiPciHostBridgeBeginBusAllocation.\r
+   EfiPciHostBridgeBeginBusAllocation     The bus allocation phase is about to begin. No specific action is\r
+                                          required here. This notification can be used to perform any\r
+                                          chipset-specific programming.\r
+   EfiPciHostBridgeEndBusAllocation       The bus allocation and bus programming phase is complete. No\r
+                                          specific action is required here. This notification can be used to\r
+                                          perform any chipset-specific programming.\r
+   EfiPciHostBridgeBeginResourceAllocation\r
+                                          The resource allocation phase is about to begin. No specific\r
+                                          action is required here. This notification can be used to perform\r
+                                          any chipset-specific programming.\r
+   EfiPciHostBridgeAllocateResources      Allocates resources per previously submitted requests for all the PCI\r
+                                          root bridges. These resource settings are returned on the next call to\r
+                                          GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
+                                          EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
+                                          for gathering I/O and memory requests for\r
+                                          all the PCI root bridges and submitting these requests using\r
+                                          SubmitResources(). This function pads the resource amount\r
+                                          to suit the root bridge hardware, takes care of dependencies between\r
+                                          the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
+                                          with the allocation request. In the case of padding, the allocated range\r
+                                          could be bigger than what was requested.\r
+   EfiPciHostBridgeSetResources           Programs the host bridge hardware to decode previously allocated\r
+                                          resources (proposed resources) for all the PCI root bridges. After the\r
+                                          hardware is programmed, reassigning resources will not be supported.\r
+                                          The bus settings are not affected.\r
+   EfiPciHostBridgeFreeResources          Deallocates resources that were previously allocated for all the PCI\r
+                                          root bridges and resets the I/O and memory apertures to their initial\r
+                                          state. The bus settings are not affected. If the request to allocate\r
+                                          resources fails, the PCI enumerator can use this notification to\r
+                                          deallocate previous resources, adjust the requests, and retry\r
+                                          allocation.\r
+   EfiPciHostBridgeEndResourceAllocation  The resource allocation phase is completed. No specific action is\r
+                                          required here. This notification can be used to perform any chipsetspecific\r
+                                          programming.\r
+\r
+   @param[in] This                The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+   @param[in] Phase               The phase during enumeration\r
+\r
+   @retval EFI_NOT_READY          This phase cannot be entered at this time. For example, this error\r
+                                  is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
+                                  SubmitResources() has not been called for one or more\r
+                                  PCI root bridges before this call\r
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error. This error is valid\r
+                                  for a Phase of EfiPciHostBridgeSetResources.\r
+   @retval EFI_INVALID_PARAMETER  Invalid phase parameter\r
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
+                                  This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
+                                  previously submitted resource requests cannot be fulfilled or\r
+                                  were only partially fulfilled.\r
+   @retval EFI_SUCCESS            The notification was accepted without any errors.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 NotifyPhase(\r
 EFI_STATUS\r
 EFIAPI\r
 NotifyPhase(\r


@@ -87,6 +142,28 @@ NotifyPhase(
   IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase\r
   );\r
 \r
   IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase\r
   );\r
 \r

+/**\r
+   Return the device handle of the next PCI root bridge that is associated with this Host Bridge.\r
+\r
+   This function is called multiple times to retrieve the device handles of all the PCI root bridges that\r
+   are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI\r
+   root bridges. On each call, the handle that was returned by the previous call is passed into the\r
+   interface, and on output the interface returns the device handle of the next PCI root bridge. The\r
+   caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+   for that root bridge. When there are no more PCI root bridges to report, the interface returns\r
+   EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they\r
+   are returned by this function.\r
+   For D945 implementation, there is only one root bridge in PCI host bridge.\r
+\r
+   @param[in]       This              The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+   @param[in, out]  RootBridgeHandle  Returns the device handle of the next PCI root bridge.\r
+   \r
+   @retval EFI_SUCCESS            If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
+                                  specific Host bridge and return EFI_SUCCESS. \r
+   @retval EFI_NOT_FOUND          Can not find the any more root bridge in specific host bridge.\r
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not an EFI_HANDLE that was\r
+                                  returned on a previous call to GetNextRootBridge().\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 GetNextRootBridge(\r
 EFI_STATUS\r
 EFIAPI\r
 GetNextRootBridge(\r


@@ -94,6 +171,44 @@ GetNextRootBridge(
   IN OUT   EFI_HANDLE                                       *RootBridgeHandle\r
   );\r
   \r
   IN OUT   EFI_HANDLE                                       *RootBridgeHandle\r
   );\r
   \r

+/**\r
+   Returns the allocation attributes of a PCI root bridge.\r
+\r
+   The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary\r
+   from one PCI root bridge to another. These attributes are different from the decode-related\r
+   attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
+   RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device\r
+   handles of all the root bridges that are associated with this host bridge must be obtained by calling\r
+   GetNextRootBridge(). The attributes are static in the sense that they do not change during or\r
+   after the enumeration process. The hardware may provide mechanisms to change the attributes on\r
+   the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is \r
+   installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
+   "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.\r
+   For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to \r
+   include requests for the prefetchable memory in the nonprefetchable memory pool and not request any \r
+   prefetchable memory.\r
+      Attribute                                 Description\r
+   ------------------------------------         ----------------------------------------------------------------------\r
+   EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM         If this bit is set, then the PCI root bridge does not support separate\r
+                                                windows for nonprefetchable and prefetchable memory. A PCI bus\r
+                                                driver needs to include requests for prefetchable memory in the\r
+                                                nonprefetchable memory pool.\r
+\r
+   EFI_PCI_HOST_BRIDGE_MEM64_DECODE             If this bit is set, then the PCI root bridge supports 64-bit memory\r
+                                                windows. If this bit is not set, the PCI bus driver needs to include\r
+                                                requests for a 64-bit memory address in the corresponding 32-bit\r
+                                                memory pool.\r
+\r
+   @param[in]   This               The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+   @param[in]   RootBridgeHandle   The device handle of the PCI root bridge in which the caller is interested. Type\r
+                                   EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
+   @param[out]  Attributes         The pointer to attribte of root bridge, it is output parameter\r
+   \r
+   @retval EFI_INVALID_PARAMETER   Attribute pointer is NULL\r
+   @retval EFI_INVALID_PARAMETER   RootBridgehandle is invalid.\r
+   @retval EFI_SUCCESS             Success to get attribute of interested root bridge.\r
+\r
+**/  \r

 EFI_STATUS\r
 EFIAPI\r
 GetAttributes(\r
 EFI_STATUS\r
 EFIAPI\r
 GetAttributes(\r


@@ -102,6 +217,21 @@ GetAttributes(
   OUT UINT64                                           *Attributes\r
   );\r
   \r
   OUT UINT64                                           *Attributes\r
   );\r
   \r

+/**\r
+   Sets up the specified PCI root bridge for the bus enumeration process.\r
+\r
+   This member function sets up the root bridge for bus enumeration and returns the PCI bus range\r
+   over which the search should be performed in ACPI 2.0 resource descriptor format.\r
+\r
+   @param[in]   This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+   @param[in]   RootBridgeHandle  The PCI Root Bridge to be set up.\r
+   @param[out]  Configuration     Pointer to the pointer to the PCI bus resource descriptor.\r
+   \r
+   @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
+   @retval EFI_OUT_OF_RESOURCES  Fail to allocate ACPI resource descriptor tag.\r
+   @retval EFI_SUCCESS           Sucess to allocate ACPI resource descriptor.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 StartBusEnumeration(\r
 EFI_STATUS\r
 EFIAPI\r
 StartBusEnumeration(\r


@@ -110,6 +240,30 @@ StartBusEnumeration(
   OUT VOID                                             **Configuration\r
   );\r
   \r
   OUT VOID                                             **Configuration\r
   );\r
   \r

+/**\r
+   Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
+\r
+   This member function programs the specified PCI root bridge to decode the bus range that is\r
+   specified by the input parameter Configuration.\r
+   The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.\r
+\r
+   @param[in] This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
+   @param[in] RootBridgeHandle  The PCI Root Bridge whose bus range is to be programmed\r
+   @param[in] Configuration     The pointer to the PCI bus resource descriptor\r
+   \r
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.\r
+   @retval EFI_INVALID_PARAMETER  Configuration is NULL.\r
+   @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
+   @retval EFI_INVALID_PARAMETER  Configuration does not include a valid ACPI 2.0 bus resource descriptor.\r
+   @retval EFI_INVALID_PARAMETER  Configuration includes valid ACPI 2.0 resource descriptors other than \r
+                                  bus descriptors.\r
+   @retval EFI_INVALID_PARAMETER  Configuration contains one or more invalid ACPI resource descriptors.\r
+   @retval EFI_INVALID_PARAMETER  "Address Range Minimum" is invalid for this root bridge.\r
+   @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this root bridge.\r
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.\r
+   @retval EFI_SUCCESS            The bus range for the PCI root bridge was programmed.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 SetBusNumbers(\r
 EFI_STATUS\r
 EFIAPI\r
 SetBusNumbers(\r


@@ -118,6 +272,31 @@ SetBusNumbers(
   IN VOID                                             *Configuration\r
   );\r
   \r
   IN VOID                                             *Configuration\r
   );\r
   \r

+/**\r
+   Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
+\r
+   This function is used to submit all the I/O and memory resources that are required by the specified\r
+   PCI root bridge. The input parameter Configuration is used to specify the following:\r
+   - The various types of resources that are required\r
+   - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+   @param[in] This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+   @param[in] RootBridgeHandle  The PCI root bridge whose I/O and memory resource requirements are being submitted.\r
+   @param[in] Configuration     The pointer to the PCI I/O and PCI memory resource descriptor.\r
+   \r
+   @retval EFI_SUCCESS            The I/O and memory resource requests for a PCI root bridge were accepted.\r
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.\r
+   @retval EFI_INVALID_PARAMETER  Configuration is NULL.\r
+   @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
+   @retval EFI_INVALID_PARAMETER  Configuration includes requests for one or more resource types that are \r
+                                  not supported by this PCI root bridge. This error will happen if the caller \r
+                                  did not combine resources according to Attributes that were returned by\r
+                                  GetAllocAttributes().\r
+   @retval EFI_INVALID_PARAMETER  Address Range Maximum" is invalid.\r
+   @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this PCI root bridge.\r
+   @retval EFI_INVALID_PARAMETER  "Address Space Granularity" is invalid for this PCI root bridge.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 SubmitResources(\r
 EFI_STATUS\r
 EFIAPI\r
 SubmitResources(\r


@@ -126,6 +305,26 @@ SubmitResources(
   IN VOID                                             *Configuration\r
   );\r
   \r
   IN VOID                                             *Configuration\r
   );\r
   \r

+/**\r
+   Returns the proposed resource settings for the specified PCI root bridge.\r
+\r
+   This member function returns the proposed resource settings for the specified PCI root bridge. The\r
+   proposed resource settings are prepared when NotifyPhase() is called with a Phase of\r
+   EfiPciHostBridgeAllocateResources. The output parameter Configuration\r
+   specifies the following:\r
+   - The various types of resources, excluding bus resources, that are allocated\r
+   - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+   @param[in]  This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+   @param[in]  RootBridgeHandle  The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
+   @param[out] Configuration     The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
+   \r
+   @retval EFI_SUCCESS            The requested parameters were returned.\r
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.\r
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.\r
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 GetProposedResources(\r
 EFI_STATUS\r
 EFIAPI\r
 GetProposedResources(\r


@@ -134,6 +333,33 @@ GetProposedResources(
   OUT VOID                                             **Configuration\r
   );\r
 \r
   OUT VOID                                             **Configuration\r
   );\r
 \r

+/**\r
+   Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
+   stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
+   PCI controllers before enumeration.\r
+\r
+   This function is called during the PCI enumeration process. No specific action is expected from this\r
+   member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
+   enumeration.\r
+\r
+   @param This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+   @param RootBridgeHandle  The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r
+                            InstallProtocolInterface() in the UEFI 2.0 Specification.\r
+   @param PciAddress        The address of the PCI device on the PCI bus. This address can be passed to the\r
+                            EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r
+                            configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r
+                            the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
+   @param Phase             The phase of the PCI device enumeration. \r
+   \r
+   @retval EFI_SUCCESS              The requested parameters were returned.\r
+   @retval EFI_INVALID_PARAMETER    RootBridgeHandle is not a valid root bridge handle.\r
+   @retval EFI_INVALID_PARAMETER    Phase is not a valid phase that is defined in\r
+                                    EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+   @retval EFI_DEVICE_ERROR         Programming failed due to a hardware error. The PCI enumerator should\r
+                                    not enumerate this device, including its child devices if it is a PCI-to-PCI\r
+                                    bridge.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 PreprocessController (\r
 EFI_STATUS\r
 EFIAPI\r
 PreprocessController (\r


@@ -249,7 +475,18 @@ typedef struct {
 #define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r
   CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r
 \r
 #define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r
   CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r
 \r

+/**\r
+\r
+  Construct the Pci Root Bridge Io protocol\r
+\r
+  @param Protocol         Point to protocol instance\r
+  @param HostBridgeHandle Handle of host bridge\r
+  @param Attri            Attribute of host bridge\r
+  @param ResAppeture      ResourceAppeture for host bridge\r
+\r
+  @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r

 \r
 \r

+**/\r

 EFI_STATUS\r
 RootBridgeConstructor (\r
   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,\r
 EFI_STATUS\r
 RootBridgeConstructor (\r
   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,\r

diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
index a33836569b2a47f0858df203e73a391669cbdf53..cd39f2bbf71e421d05445f20dbe39246a88b5e28 100644 (file)
--- a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -145,7 +145,7 @@ RootBridgeIoMemRead (
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r

-  IN OUT VOID                                   *Buffer\r
+  OUT    VOID                                   *Buffer\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -162,7 +162,7 @@ RootBridgeIoMemRead (
                           responsible for aligning the Address if required.\r
    @param[in]   Count     The number of memory operations to perform. Bytes moved is\r
                           Width size * Count, starting at Address.\r
                           responsible for aligning the Address if required.\r
    @param[in]   Count     The number of memory operations to perform. Bytes moved is\r
                           Width size * Count, starting at Address.\r

-   @param[out]  Buffer    For read operations, the destination buffer to store the results. For\r
+   @param[in]   Buffer    For read operations, the destination buffer to store the results. For\r

                           write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
                           write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r


@@ -177,7 +177,7 @@ RootBridgeIoMemWrite (
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r

-  IN OUT VOID                                   *Buffer\r
+  IN     VOID                                   *Buffer\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -185,11 +185,11 @@ RootBridgeIoMemWrite (
 \r
    @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
    @param[in]   Width       Signifies the width of the memory operations.\r
 \r
    @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
    @param[in]   Width       Signifies the width of the memory operations.\r

-   @param[in]   Address     The base address of the I/O operation. The caller is responsible for\r
+   @param[in]   UserAddress The base address of the I/O operation. The caller is responsible for\r

                             aligning the Address if required.\r
    @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                             size * Count, starting at Address.\r
                             aligning the Address if required.\r
    @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                             size * Count, starting at Address.\r

-   @param[out]  Buffer      For read operations, the destination buffer to store the results. For\r
+   @param[out]  UserBuffer  For read operations, the destination buffer to store the results. For\r

                             write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r
                             write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r


@@ -205,7 +205,7 @@ RootBridgeIoIoRead (
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 UserAddress,\r
   IN     UINTN                                  Count,\r
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 UserAddress,\r
   IN     UINTN                                  Count,\r

-  IN OUT VOID                                   *UserBuffer\r
+  OUT    VOID                                   *UserBuffer\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -213,11 +213,11 @@ RootBridgeIoIoRead (
 \r
    @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
    @param[in]   Width       Signifies the width of the memory operations.\r
 \r
    @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
    @param[in]   Width       Signifies the width of the memory operations.\r

-   @param[in]   Address     The base address of the I/O operation. The caller is responsible for\r
+   @param[in]   UserAddress The base address of the I/O operation. The caller is responsible for\r

                             aligning the Address if required.\r
    @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                             size * Count, starting at Address.\r
                             aligning the Address if required.\r
    @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                             size * Count, starting at Address.\r

-   @param[out]  Buffer      For read operations, the destination buffer to store the results. For\r
+   @param[in]   UserBuffer  For read operations, the destination buffer to store the results. For\r

                             write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r
                             write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r


@@ -233,7 +233,7 @@ RootBridgeIoIoWrite (
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 UserAddress,\r
   IN     UINTN                                  Count,\r
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 UserAddress,\r
   IN     UINTN                                  Count,\r

-  IN OUT VOID                                   *UserBuffer\r
+  IN     VOID                                   *UserBuffer\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -300,7 +300,7 @@ RootBridgeIoPciRead (
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r

-  IN OUT VOID                                   *Buffer\r
+  OUT    VOID                                   *Buffer\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -317,7 +317,7 @@ RootBridgeIoPciRead (
    @param[in]   Address   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count     The number of PCI configuration operations to perform. Bytes\r
                           moved is Width size * Count, starting at Address.\r
    @param[in]   Address   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count     The number of PCI configuration operations to perform. Bytes\r
                           moved is Width size * Count, starting at Address.\r

-   @param[out]  Buffer    For read operations, the destination buffer to store the results. For\r
+   @param[in]   Buffer    For read operations, the destination buffer to store the results. For\r

                           write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
                           write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r


@@ -333,7 +333,7 @@ RootBridgeIoPciWrite (
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r

-  IN OUT VOID                                   *Buffer\r
+  IN     VOID                                   *Buffer\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -346,7 +346,7 @@ RootBridgeIoPciWrite (
    @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
    @param[in]       Operation       Indicates if the bus master is going to read or write to system memory.\r
    @param[in]       HostAddress     The system memory address to map to the PCI controller.\r
    @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
    @param[in]       Operation       Indicates if the bus master is going to read or write to system memory.\r
    @param[in]       HostAddress     The system memory address to map to the PCI controller.\r

-   @param[in][out]  NumberOfBytes   On input the number of bytes to map. On output the number of bytes that were mapped.\r
+   @param[in, out]  NumberOfBytes   On input the number of bytes to map. On output the number of bytes that were mapped.\r

    @param[out]      DeviceAddress   The resulting map address for the bus master PCI controller to use\r
                                     to access the system memory's HostAddress.\r
    @param[out]      Mapping         The value to pass to Unmap() when the bus master DMA operation is complete.\r
    @param[out]      DeviceAddress   The resulting map address for the bus master PCI controller to use\r
                                     to access the system memory's HostAddress.\r
    @param[out]      Mapping         The value to pass to Unmap() when the bus master DMA operation is complete.\r


@@ -523,9 +523,9 @@ RootBridgeIoGetAttributes (
                                     MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
                                     MEMORY_DISABLE are not set, then ResourceBase and\r
                                     ResourceLength are ignored, and may be NULL.\r
                                     MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
                                     MEMORY_DISABLE are not set, then ResourceBase and\r
                                     ResourceLength are ignored, and may be NULL.\r

-   @param[in][out]  ResourceBase    A pointer to the base address of the resource range to be modified\r
+   @param[in, out]  ResourceBase    A pointer to the base address of the resource range to be modified\r

                                     by the attributes specified by Attributes.\r
                                     by the attributes specified by Attributes.\r

-   @param[in][out]  ResourceLength  A pointer to the length of the resource range to be modified by the\r
+   @param[in, out]  ResourceLength  A pointer to the length of the resource range to be modified by the\r

                                     attributes specified by Attributes.\r
    \r
    @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.\r
                                     attributes specified by Attributes.\r
    \r
    @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.\r


@@ -866,7 +866,7 @@ RootBridgeIoCheckParameter (
    @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count         The number of PCI configuration operations to perform. Bytes\r
                               moved is Width size * Count, starting at Address.\r
    @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count         The number of PCI configuration operations to perform. Bytes\r
                               moved is Width size * Count, starting at Address.\r

-   @param[out]  UserBuffer    For read operations, the destination buffer to store the results. For\r
+   @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r

                               write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
                               write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r


@@ -958,7 +958,7 @@ RootBridgeIoMemRW (
    @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count         The number of PCI configuration operations to perform. Bytes\r
                               moved is Width size * Count, starting at Address.\r
    @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count         The number of PCI configuration operations to perform. Bytes\r
                               moved is Width size * Count, starting at Address.\r

-   @param[out]  UserBuffer    For read operations, the destination buffer to store the results. For\r
+   @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r

                               write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
                               write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r


@@ -1044,7 +1044,7 @@ RootBridgeIoIoRW (
    @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count         The number of PCI configuration operations to perform. Bytes\r
                               moved is Width size * Count, starting at Address.\r
    @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count         The number of PCI configuration operations to perform. Bytes\r
                               moved is Width size * Count, starting at Address.\r

-   @param[out]  UserBuffer    For read operations, the destination buffer to store the results. For\r
+   @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r

                               write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
                               write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r


@@ -1219,7 +1219,7 @@ RootBridgeIoPollMem (
     }\r
     NumberOfTicks += 1;\r
   \r
     }\r
     NumberOfTicks += 1;\r
   \r

-    while (NumberOfTicks) {\r
+    while (NumberOfTicks != 0) {\r

 \r
       mMetronome->WaitForTick (mMetronome, 1);\r
     \r
 \r
       mMetronome->WaitForTick (mMetronome, 1);\r
     \r


@@ -1320,7 +1320,7 @@ RootBridgeIoPollIo (
     }\r
     NumberOfTicks += 1;\r
   \r
     }\r
     NumberOfTicks += 1;\r
   \r

-    while (NumberOfTicks) {\r
+    while (NumberOfTicks != 0) {\r

 \r
       mMetronome->WaitForTick (mMetronome, 1);\r
     \r
 \r
       mMetronome->WaitForTick (mMetronome, 1);\r
     \r


@@ -1369,7 +1369,7 @@ RootBridgeIoMemRead (
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r

-  IN OUT VOID                                   *Buffer\r
+  OUT    VOID                                   *Buffer\r

   )\r
 {\r
   return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);\r
   )\r
 {\r
   return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);\r


@@ -1389,7 +1389,7 @@ RootBridgeIoMemRead (
                           responsible for aligning the Address if required.\r
    @param[in]   Count     The number of memory operations to perform. Bytes moved is\r
                           Width size * Count, starting at Address.\r
                           responsible for aligning the Address if required.\r
    @param[in]   Count     The number of memory operations to perform. Bytes moved is\r
                           Width size * Count, starting at Address.\r

-   @param[out]  Buffer    For read operations, the destination buffer to store the results. For\r
+   @param[in]   Buffer    For read operations, the destination buffer to store the results. For\r

                           write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
                           write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r


@@ -1404,7 +1404,7 @@ RootBridgeIoMemWrite (
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r

-  IN OUT VOID                                   *Buffer\r
+  IN     VOID                                   *Buffer\r

   )\r
 {\r
   return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);  \r
   )\r
 {\r
   return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);  \r


@@ -1435,7 +1435,7 @@ RootBridgeIoIoRead (
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r
   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN     UINT64                                 Address,\r
   IN     UINTN                                  Count,\r

-  IN OUT VOID                                   *Buffer\r
+  OUT    VOID                                   *Buffer\r

   )\r
 {\r
   return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);  \r
   )\r
 {\r
   return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);  \r


@@ -1450,7 +1450,7 @@ RootBridgeIoIoRead (
                             aligning the Address if required.\r
    @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                             size * Count, starting at Address.\r
                             aligning the Address if required.\r
    @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                             size * Count, starting at Address.\r

-   @param[out]  Buffer      For read operations, the destination buffer to store the results. For\r
+   @param[in]   Buffer       For read operations, the destination buffer to store the results. For\r

                             write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r
                             write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r


@@ -1466,7 +1466,7 @@ RootBridgeIoIoWrite (
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,\r
   IN       UINT64                                  Address,\r
   IN       UINTN                                   Count,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,\r
   IN       UINT64                                  Address,\r
   IN       UINTN                                   Count,\r

-  IN OUT   VOID                                    *Buffer\r
+  IN       VOID                                    *Buffer\r

   )\r
 {\r
   return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);  \r
   )\r
 {\r
   return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);  \r


@@ -1499,7 +1499,7 @@ RootBridgeIoIoWrite (
 EFI_STATUS\r
 EFIAPI\r
 RootBridgeIoCopyMem (\r
 EFI_STATUS\r
 EFIAPI\r
 RootBridgeIoCopyMem (\r

-  IN struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL      *This,\r
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r

   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        Width,\r
   IN UINT64                                       DestAddress,\r
   IN UINT64                                       SrcAddress,\r
   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        Width,\r
   IN UINT64                                       DestAddress,\r
   IN UINT64                                       SrcAddress,\r


@@ -1591,7 +1591,7 @@ RootBridgeIoPciRead (
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN       UINT64                                 Address,\r
   IN       UINTN                                  Count,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN       UINT64                                 Address,\r
   IN       UINTN                                  Count,\r

-  IN OUT   VOID                                   *Buffer\r
+  OUT      VOID                                   *Buffer\r

   )\r
 {\r
   return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
   )\r
 {\r
   return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r


@@ -1611,7 +1611,7 @@ RootBridgeIoPciRead (
    @param[in]   Address   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count     The number of PCI configuration operations to perform. Bytes\r
                           moved is Width size * Count, starting at Address.\r
    @param[in]   Address   The address within the PCI configuration space for the PCI controller.\r
    @param[in]   Count     The number of PCI configuration operations to perform. Bytes\r
                           moved is Width size * Count, starting at Address.\r

-   @param[out]  Buffer    For read operations, the destination buffer to store the results. For\r
+   @param[in]   Buffer    For read operations, the destination buffer to store the results. For\r

                           write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
                           write operations, the source buffer to write data from.\r
    \r
    @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r


@@ -1627,7 +1627,7 @@ RootBridgeIoPciWrite (
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN       UINT64                                 Address,\r
   IN       UINTN                                  Count,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN       UINT64                                 Address,\r
   IN       UINTN                                  Count,\r

-  IN OUT   VOID                                   *Buffer\r
+  IN       VOID                                   *Buffer\r

   )\r
 {\r
   return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
   )\r
 {\r
   return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r


@@ -1643,7 +1643,7 @@ RootBridgeIoPciWrite (
    @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
    @param[in]       Operation       Indicates if the bus master is going to read or write to system memory.\r
    @param[in]       HostAddress     The system memory address to map to the PCI controller.\r
    @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
    @param[in]       Operation       Indicates if the bus master is going to read or write to system memory.\r
    @param[in]       HostAddress     The system memory address to map to the PCI controller.\r

-   @param[in][out]  NumberOfBytes   On input the number of bytes to map. On output the number of bytes that were mapped.\r
+   @param[in, out]  NumberOfBytes   On input the number of bytes to map. On output the number of bytes that were mapped.\r

    @param[out]      DeviceAddress   The resulting map address for the bus master PCI controller to use\r
                                     to access the system memory's HostAddress.\r
    @param[out]      Mapping         The value to pass to Unmap() when the bus master DMA operation is complete.\r
    @param[out]      DeviceAddress   The resulting map address for the bus master PCI controller to use\r
                                     to access the system memory's HostAddress.\r
    @param[out]      Mapping         The value to pass to Unmap() when the bus master DMA operation is complete.\r


@@ -1872,7 +1872,7 @@ RootBridgeIoAllocateBuffer (
   //\r
   // Validate Attributes\r
   //\r
   //\r
   // Validate Attributes\r
   //\r

-  if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {\r
+  if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r

     return EFI_UNSUPPORTED;\r
   }\r
 \r
     return EFI_UNSUPPORTED;\r
   }\r
 \r


@@ -2000,11 +2000,11 @@ RootBridgeIoGetAttributes (
   //\r
   // Set the return value for Supported and Attributes\r
   //\r
   //\r
   // Set the return value for Supported and Attributes\r
   //\r

-  if (Supported) {\r
+  if (Supported != NULL) {\r

     *Supported  = PrivateData->Supports; \r
   }\r
 \r
     *Supported  = PrivateData->Supports; \r
   }\r
 \r

-  if (Attributes) {\r
+  if (Attributes != NULL) {\r

     *Attributes = PrivateData->Attributes;\r
   }\r
   \r
     *Attributes = PrivateData->Attributes;\r
   }\r
   \r


@@ -2031,9 +2031,9 @@ RootBridgeIoGetAttributes (
                                     MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
                                     MEMORY_DISABLE are not set, then ResourceBase and\r
                                     ResourceLength are ignored, and may be NULL.\r
                                     MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
                                     MEMORY_DISABLE are not set, then ResourceBase and\r
                                     ResourceLength are ignored, and may be NULL.\r

-   @param[in][out]  ResourceBase    A pointer to the base address of the resource range to be modified\r
+   @param[in, out]  ResourceBase    A pointer to the base address of the resource range to be modified\r

                                     by the attributes specified by Attributes.\r
                                     by the attributes specified by Attributes.\r

-   @param[in][out]  ResourceLength  A pointer to the length of the resource range to be modified by the\r
+   @param[in, out]  ResourceLength  A pointer to the length of the resource range to be modified by the\r

                                     attributes specified by Attributes.\r
    \r
    @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.\r
                                     attributes specified by Attributes.\r
    \r
    @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.\r


@@ -2054,7 +2054,7 @@ RootBridgeIoSetAttributes (
   \r
   PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
   \r
   \r
   PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
   \r

-  if (Attributes) {\r
+  if (Attributes != 0) {\r

     if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
       return EFI_UNSUPPORTED;\r
     }\r
     if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
       return EFI_UNSUPPORTED;\r
     }\r