UINT32 max_entries;\r
UINT32 num_entries;\r
UINT32 flags;\r
- UINT32 entry_align; \r
+ UINT32 entry_align;
UINT32 max_offset;\r
struct imd_entry entries[0];\r
};\r
UINT32 type;\r
UINT32 baseaddr;\r
UINT32 baud;\r
+ UINT32 regwidth;
+
+ // Crystal or input frequency to the chip containing the UART.
+ // Provide the board specific details to allow the payload to
+ // initialize the chip containing the UART and make independent
+ // decisions as to which dividers to select and their values
+ // to eventually arrive at the desired console baud-rate.
+ UINT32 input_hertz;
+
+ // UART PCI address: bus, device, function
+ // 1 << 31 - Valid bit, PCI UART in use
+ // Bus << 20
+ // Device << 15
+ // Function << 12
+ UINT32 uart_pci_addr;
};\r
\r
#define CB_TAG_CONSOLE 0x00010\r
IN UINT64* pLowMemorySize,\r
IN UINT64* pHighMemorySize\r
);\r
- \r
+
/**\r
Acquire the coreboot memory table with the given table id\r
\r
**/\r
RETURN_STATUS\r
CbParseCbMemTable (\r
- IN UINT32 TableId, \r
+ IN UINT32 TableId,
IN VOID** pMemTable,\r
IN UINT32* pMemTableSize\r
);\r
- \r
+
/**\r
Acquire the acpi table from coreboot\r
\r
IN VOID** pMemTable,\r
IN UINT32* pMemTableSize\r
);\r
- \r
+
/**\r
Acquire the smbios table from coreboot\r
\r
IN VOID** pMemTable,\r
IN UINT32* pMemTableSize\r
);\r
- \r
+
/**\r
Find the required fadt information\r
\r
IN UINTN* pPmEvtReg,\r
IN UINTN* pPmGpeEnReg\r
);\r
- \r
+
/**\r
Find the serial port information\r
\r
@param pRegBase Pointer to the base address of serial port registers\r
@param pRegAccessType Pointer to the access type of serial port registers\r
+ @param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate\r
+ @param pInputHertz Pointer to the input clock frequency
+ @param pUartPciAddr Pointer to the UART PCI bus, dev and func address
\r
@retval RETURN_SUCCESS Successfully find the serial port information.\r
@retval RETURN_NOT_FOUND Failed to find the serial port information .\r
**/\r
RETURN_STATUS\r
CbParseSerialInfo (\r
- IN UINT32* pRegBase,\r
- IN UINT32* pRegAccessType,\r
- IN UINT32* pBaudrate\r
+ OUT UINT32 *pRegBase,
+ OUT UINT32 *pRegAccessType,
+ OUT UINT32 *pRegWidth,
+ OUT UINT32 *pBaudrate,
+ OUT UINT32 *pInputHertz,
+ OUT UINT32 *pUartPciAddr
);\r
\r
/**\r
IN UINTN Level,\r
IN VOID** HeaderPtr\r
);\r
- \r
+
/**\r
Find the video frame buffer information\r
\r
@return the UNIT64 value after convertion.\r
\r
**/\r
-UINT64 \r
+UINT64
cb_unpack64 (\r
IN struct cbuint64 val\r
)\r
}\r
DEBUG ((EFI_D_INFO, "Reset Value 0x%x\n", Fadt->ResetValue));\r
\r
- if (pPmEvtReg != NULL) { \r
+ if (pPmEvtReg != NULL) {
*pPmEvtReg = Fadt->Pm1aEvtBlk;\r
DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk));\r
}\r
\r
- if (pPmGpeEnReg != NULL) { \r
+ if (pPmGpeEnReg != NULL) {
*pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;\r
DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg));\r
}\r
*pResetValue = Fadt->ResetValue;\r
DEBUG ((EFI_D_ERROR, "Reset Value 0x%x\n", Fadt->ResetValue));\r
\r
- if (pPmEvtReg != NULL) { \r
+ if (pPmEvtReg != NULL) {
*pPmEvtReg = Fadt->Pm1aEvtBlk;\r
DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk));\r
}\r
\r
- if (pPmGpeEnReg != NULL) { \r
+ if (pPmGpeEnReg != NULL) {
*pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;\r
DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg));\r
- } \r
+ }
return RETURN_SUCCESS;\r
}\r
}\r
\r
@param pRegBase Pointer to the base address of serial port registers\r
@param pRegAccessType Pointer to the access type of serial port registers\r
+ @param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate\r
+ @param pInputHertz Pointer to the input clock frequency
+ @param pUartPciAddr Pointer to the UART PCI bus, dev and func address
\r
@retval RETURN_SUCCESS Successfully find the serial port information.\r
@retval RETURN_NOT_FOUND Failed to find the serial port information .\r
CbParseSerialInfo (\r
OUT UINT32 *pRegBase,\r
OUT UINT32 *pRegAccessType,\r
- OUT UINT32 *pBaudrate\r
+ OUT UINT32 *pRegWidth,
+ OUT UINT32 *pBaudrate,
+ OUT UINT32 *pInputHertz,
+ OUT UINT32 *pUartPciAddr
)\r
{\r
struct cb_serial *CbSerial;\r
*pRegBase = CbSerial->baseaddr;\r
}\r
\r
+ if (pRegWidth != NULL) {
+ *pRegWidth = CbSerial->regwidth;
+ }
+
if (pRegAccessType != NULL) {\r
*pRegAccessType = CbSerial->type;\r
}\r
*pBaudrate = CbSerial->baud;\r
}\r
\r
+ if (pInputHertz != NULL) {
+ *pInputHertz = CbSerial->input_hertz;
+ }
+
+ if (pUartPciAddr != NULL) {
+ *pUartPciAddr = CbSerial->uart_pci_addr;
+ }
+
return RETURN_SUCCESS;\r
}\r
\r
VOID\r
)\r
{\r
+ gUartDeviceNode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
+ gUartDeviceNode.DataBits = PcdGet8 (PcdUartDefaultDataBits);
+ gUartDeviceNode.Parity = PcdGet8 (PcdUartDefaultParity);
+ gUartDeviceNode.StopBits = PcdGet8 (PcdUartDefaultStopBits);
}\r
\r
\r
\r
DEBUG ((EFI_D_INFO, "PlatformBdsPolicyBehavior\n"));\r
\r
+ PlatformBdsInit();
ConnectRootBridge ();\r
\r
//\r
DebugLib\r
PcdLib\r
GenericBdsLib\r
+ PlatformHookLib
+
[Pcd]\r
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut\r
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
\r
#include <Base.h>\r
#include <Uefi/UefiBaseType.h>\r
+#include <Library/PciLib.h>
#include <Library/PlatformHookLib.h>\r
#include <Library/CbParseLib.h>\r
#include <Library/PcdLib.h>\r
\r
+typedef struct {
+ UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
+ UINT16 DeviceId; ///< Device ID to match the PCI device
+ UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
+ UINT64 Offset; ///< The byte offset into to the BAR
+ UINT8 BarIndex; ///< Which BAR to get the UART base address
+ UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
+ UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
+ UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
+ UINT8 Reserved[2];
+} PCI_SERIAL_PARAMETER;
+
/**\r
Performs platform specific initialization required for the CPU to access\r
the hardware associated with a SerialPortLib instance. This function does\r
RETURN_STATUS Status;\r
UINT32 SerialRegBase;\r
UINT32 SerialRegAccessType;\r
+ UINT32 BaudRate;
+ UINT32 RegWidth;
+ UINT32 InputHertz;
+ UINT32 PayloadParam;
+ UINT32 DeviceVendor;
+ PCI_SERIAL_PARAMETER *SerialParam;
\r
- Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType, NULL);\r
+ Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType,
+ &RegWidth, &BaudRate, &InputHertz,
+ &PayloadParam);
if (RETURN_ERROR (Status)) {\r
return Status;\r
}\r
return Status;\r
}\r
\r
+ Status = PcdSet32S (PcdSerialRegisterStride, RegWidth);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PcdSet32S (PcdSerialBaudRate, BaudRate);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PcdSet64S (PcdUartDefaultBaudRate, BaudRate);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PcdSet32S (PcdSerialClockRate, InputHertz);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ if (PayloadParam >= 0x80000000) {
+ DeviceVendor = PciRead32 (PayloadParam & 0x0ffff000);
+ SerialParam = PcdGetPtr(PcdPciSerialParameters);
+ SerialParam->VendorId = (UINT16)DeviceVendor;
+ SerialParam->DeviceId = DeviceVendor >> 16;
+ SerialParam->ClockRate = InputHertz;
+ SerialParam->RegisterStride = (UINT8)RegWidth;
+ }
+
return RETURN_SUCCESS;\r
}\r
-\r
MODULE_TYPE = BASE\r
VERSION_STRING = 1.0\r
LIBRARY_CLASS = PlatformHookLib\r
+ CONSTRUCTOR = PlatformHookSerialPortInitialize
\r
[Sources]\r
PlatformHookLib.c\r
[LibraryClasses]\r
CbParseLib\r
PcdLib\r
+ PciLib
\r
[Packages]\r
MdePkg/MdePkg.dec\r
CorebootModulePkg/CorebootModulePkg.dec\r
\r
[Pcd]\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES\r
-\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCES
projects / mirror_edk2.git / commitdiff