/** @file\r
Differentiated System Description Table Fields (DSDT)\r
\r
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
// A57x2-A53x4 Processor declaration\r
//\r
- Device(CPU0) { // A57-0: Cluster 0, Cpu 0\r
+ Device(CPU0) { // A53-0: Cluster 1, Cpu 0\r
Name(_HID, "ACPI0007")\r
Name(_UID, 0)\r
}\r
- Device(CPU1) { // A57-1: Cluster 0, Cpu 1\r
+ Device(CPU1) { // A53-1: Cluster 1, Cpu 1\r
Name(_HID, "ACPI0007")\r
Name(_UID, 1)\r
}\r
- Device(CPU2) { // A53-0: Cluster 1, Cpu 0\r
+ Device(CPU2) { // A53-2: Cluster 1, Cpu 2\r
Name(_HID, "ACPI0007")\r
Name(_UID, 2)\r
}\r
- Device(CPU3) { // A53-1: Cluster 1, Cpu 1\r
+ Device(CPU3) { // A53-3: Cluster 1, Cpu 3\r
Name(_HID, "ACPI0007")\r
Name(_UID, 3)\r
}\r
- Device(CPU4) { // A53-2: Cluster 1, Cpu 2\r
+ Device(CPU4) { // A57-0: Cluster 0, Cpu 0\r
Name(_HID, "ACPI0007")\r
Name(_UID, 4)\r
}\r
- Device(CPU5) { // A53-3: Cluster 1, Cpu 3\r
+ Device(CPU5) { // A57-1: Cluster 0, Cpu 1\r
Name(_HID, "ACPI0007")\r
Name(_UID, 5)\r
}\r
//\r
Device(ETH0) {\r
Name(_HID, "ARMH9118")\r
+ Name(_UID, Zero)\r
Name(_CRS, ResourceTemplate() {\r
Memory32Fixed(ReadWrite, 0x1A000000, 0x1000)\r
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 192 }\r
})\r
}\r
\r
+ // UART PL011\r
+ Device(COM0) {\r
+ Name(_HID, "ARMH0011")\r
+ Name(_CID, "PL011")\r
+ Name(_UID, Zero)\r
+ Name(_CRS, ResourceTemplate() {\r
+ Memory32Fixed(ReadWrite, 0x7FF80000, 0x1000)\r
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 }\r
+ })\r
+ }\r
+\r
//\r
// USB Host Controller\r
//\r
#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)\r
#else\r
#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)\r
- #define SYSTEM_TIMER_BASE_ADDRESS 0\r
+ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
#endif\r
\r
-#define GTDT_TIMER_EDGE_TRIGGERED (1 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE)\r
-#define GTDT_TIMER_LEVEL_TRIGGERED (0 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE)\r
-#define GTDT_TIMER_ACTIVE_LOW (1 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY)\r
-#define GTDT_TIMER_ACTIVE_HIGH (0 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY)\r
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
\r
#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)\r
\r
-EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {\r
+#ifdef ARM_JUNO_ACPI_5_0\r
+ EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {\r
ARM_ACPI_HEADER(\r
EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,\r
EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE,\r
EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION\r
),\r
- SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress\r
- GTDT_GLOBAL_FLAGS, // UINT32 GlobalFlags\r
- FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags\r
- FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags\r
- FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags\r
- FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV\r
- GTDT_GTIMER_FLAGS // UINT32 NonSecurePL2TimerFlags\r
-};\r
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress\r
+ GTDT_GLOBAL_FLAGS, // UINT32 GlobalFlags\r
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV\r
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags\r
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV\r
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags\r
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV\r
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags\r
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV\r
+ GTDT_GTIMER_FLAGS // UINT32 NonSecurePL2TimerFlags\r
+ };\r
+#else\r
+ #pragma pack (1)\r
+\r
+ typedef struct {\r
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;\r
+ EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[JUNO_WATCHDOG_COUNT];\r
+ } EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;\r
\r
+ #pragma pack ()\r
+\r
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {\r
+ {\r
+ ARM_ACPI_HEADER(\r
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,\r
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE,\r
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION\r
+ ),\r
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress\r
+ 0, // UINT32 Reserved\r
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV\r
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags\r
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV\r
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags\r
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV\r
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags\r
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV\r
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags\r
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress\r
+ JUNO_WATCHDOG_COUNT, // UINT32 PlatformTimerCount\r
+ sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset\r
+ },\r
+ {\r
+ EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(\r
+ FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),\r
+ EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(\r
+ FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)\r
+ }\r
+ };\r
+#endif\r
\r
VOID*\r
ReferenceAcpiTable (\r
/** @file\r
* Multiple APIC Description Table (MADT)\r
*\r
-* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.\r
+* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
\r
#include "ArmPlatform.h"\r
#include <Library/AcpiLib.h>\r
+#include <Library/ArmLib.h>\r
#include <Library/PcdLib.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
-#pragma pack (1)\r
-\r
-typedef struct {\r
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
- EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
- EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
-} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
-\r
-#pragma pack ()\r
-\r
//\r
// Multiple APIC Description Table\r
//\r
-EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
- {\r
- ARM_ACPI_HEADER (\r
- EFI_ACPI_1_0_APIC_SIGNATURE,\r
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
- ),\r
- //\r
- // MADT specific fields\r
- //\r
- 0, // LocalApicAddress\r
- 0, // Flags\r
- },\r
- {\r
- // Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)\r
- // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of\r
- // ACPI v5.0).\r
- // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
- // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
- // For now we leave CPU2 (A53-0) at the first position.\r
- // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
- // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 2, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 3, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 4, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 5, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 0, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 1, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1\r
- },\r
- EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)\r
-};\r
+#ifdef ARM_JUNO_ACPI_5_0\r
+ #pragma pack (1)\r
+\r
+ typedef struct {\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+ EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
+ } EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+ #pragma pack ()\r
+\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
+ {\r
+ ARM_ACPI_HEADER (\r
+ EFI_ACPI_1_0_APIC_SIGNATURE,\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
+ ),\r
+ //\r
+ // MADT specific fields\r
+ //\r
+ 0, // LocalApicAddress\r
+ 0, // Flags\r
+ },\r
+ {\r
+ // Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)\r
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of\r
+ // ACPI v5.0).\r
+ // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
+ // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
+ // For now we leave CPU2 (A53-0) at the first position.\r
+ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
+ // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1\r
+ },\r
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)\r
+ };\r
+#else\r
+ #pragma pack (1)\r
+\r
+ typedef struct {\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+ EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
+ } EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+ #pragma pack ()\r
+\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
+ {\r
+ ARM_ACPI_HEADER (\r
+ EFI_ACPI_1_0_APIC_SIGNATURE,\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
+ ),\r
+ //\r
+ // MADT specific fields\r
+ //\r
+ 0, // LocalApicAddress\r
+ 0, // Flags\r
+ },\r
+ {\r
+ // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,\r
+ // GsivId, GicRBase, Mpidr)\r
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of\r
+ // ACPI v5.1).\r
+ // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
+ // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
+ // For now we leave CPU2 (A53-0) at the first position.\r
+ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
+ // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0\r
+ 2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1\r
+ 3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2\r
+ 4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3\r
+ 5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0\r
+ 0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1\r
+ 1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ },\r
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)\r
+ };\r
+#endif\r
\r
VOID*\r
ReferenceAcpiTable (\r
projects / mirror_edk2.git / commitdiff