gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023\r
\r
#\r
- # ARM Secure SEC PCDs\r
+ # ARM Secure Firmware PCDs\r
#\r
gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r
gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
\r
+ #\r
+ # ARM Normal (or Non Secure) Firmware PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0|UINT32|0x0000002B\r
+ gArmTokenSpaceGuid.PcdNormalFdSize|0|UINT32|0x0000002C\r
+\r
#\r
# ARM MPCore MailBox PCDs\r
#\r
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # Pei Services Ptr just above stack\r
\r
# Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase\r
+ gArmTokenSpaceGuid.PcdNormalFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
\r
gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms\r
\r
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # Pei Services Ptr just above stack
# Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
+ gArmTokenSpaceGuid.PcdNormalFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
gArmPlatformTokenSpaceGuid.PcdStandalone
[FixedPcd]
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress
+ gArmTokenSpaceGuid.PcdNormalFdSize
// Chunk between the EFI Memory region and the firmware\r
EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
- EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdBaseAddress) - MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdBaseAddress) - MemoryBase;\r
\r
// Chunk reserved by the firmware in DRAM\r
EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_PRESENT);\r
- EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdEmbeddedFdBaseAddress);\r
- EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdSize);\r
+ EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdNormalFdBaseAddress);\r
+ EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdSize);\r
\r
- MemoryBase = PcdGet32(PcdEmbeddedFdBaseAddress) + PcdGet32(PcdEmbeddedFdSize);\r
+ MemoryBase = PcdGet32(PcdNormalFdBaseAddress) + PcdGet32(PcdNormalFdSize);\r
}\r
\r
// We allocate all the remain memory as untested system memory\r
gArmPlatformTokenSpaceGuid.PcdStandalone\r
\r
[FixedPcd]\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
+ gArmTokenSpaceGuid.PcdNormalFdSize\r
[FD.ArmVExpress_EFI]
!if $(EDK2_ARMVE_STANDALONE) == 1
-BaseAddress = 0x45000000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress # The base address of the Firmware in NOR Flash.
+BaseAddress = 0x45000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress # The base address of the Firmware in NOR Flash.
!else
-BaseAddress = 0x80000000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress # The base address of the Firmware in remapped DRAM.
+BaseAddress = 0x80000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress # The base address of the Firmware in remapped DRAM.
!endif
-Size = 0x00200000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize # The size in bytes of the FLASH Device
+Size = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize # The size in bytes of the FLASH Device
ErasePolarity = 1
# This one is tricky, it must be: BlockSize * NumBlocks = Size
gArmPlatformTokenSpaceGuid.PcdStandalone
[FixedPcd]
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress
+ gArmTokenSpaceGuid.PcdNormalFdSize
gArmPlatformTokenSpaceGuid.PcdStandalone\r
\r
[FixedPcd]\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
+ gArmTokenSpaceGuid.PcdNormalFdSize\r
// Chunk between the EFI Memory region and the firmware\r
EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
- EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdBaseAddress) - MemoryBase;\r
+ EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdBaseAddress) - MemoryBase;\r
\r
// Chunk reserved by the firmware in DRAM\r
EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_PRESENT);\r
- EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdEmbeddedFdBaseAddress);\r
- EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdSize);\r
+ EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdNormalFdBaseAddress);\r
+ EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdSize);\r
\r
- MemoryBase = PcdGet32(PcdEmbeddedFdBaseAddress) + PcdGet32(PcdEmbeddedFdSize);\r
+ MemoryBase = PcdGet32(PcdNormalFdBaseAddress) + PcdGet32(PcdNormalFdSize);\r
}\r
\r
// We allocate all the remain memory as untested system memory\r
PCD Description\r
gArmTokenSpaceGuid.PcdSecureFdBaseAddress : Base address of your Secure Firmware \r
gArmTokenSpaceGuid.PcdSecureFdSize : Size in byte of your Secure Firmware gEmbeddedTokenSpaceGuid.\r
-PcdEmbeddedFdBaseAddress : Base Address of your Non-Secure Firmware gEmbeddedTokenSpaceGuid.\r
-PcdEmbeddedFdSize : Size in bytes of your Non-Secure Firmware \r
+gArmTokenSpaceGuid.PcdNormalFdBaseAddress : Base Address of your Non-Secure Firmware gEmbeddedTokenSpaceGuid.\r
+gArmTokenSpaceGuid.PcdNormalFdSize : Size in bytes of your Non-Secure Firmware \r
gArmTokenSpaceGuid.PcdL2x0ControllerBase : Base Address of your L2x0 controller \r
gArmTokenSpaceGuid.PcdGicDistributorBase : Base address of the Distributor of your General Interrupt Controller gArmTokenSpaceGuid.\r
PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller gArmVExpressTokenSpaceGuid.\r
[Packages]\r
MdePkg/MdePkg.dec\r
EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
\r
[LibraryClasses]\r
PeimEntryPoint\r
gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED\r
\r
[FixedPcd]\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress #The base address of the FLASH Device.\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize #The size in bytes of the FLASH Device\r
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress # The base address of the FLASH Device.\r
+ gArmTokenSpaceGuid.PcdNormalFdSize # The size in bytes of the FLASH Device\r
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase\r
gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize\r
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize\r
// Note also: HOBs (pei temp ram) MUST be above stack\r
//\r
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdEmbeddedFdBaseAddress);\r
- SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdEmbeddedFdSize);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFdBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFdSize);\r
SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
// Note also: HOBs (pei temp ram) MUST be above stack\r
//\r
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdEmbeddedFdBaseAddress);\r
- SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdEmbeddedFdSize);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFdBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFdSize);\r
SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
# lr points to area in reset vector block containing PEI core address. lr needs to
# be saved from the beginning as the _ModuleEntryPoint could call helper functions
# that will overwrite 'lr'
- LoadConstantToReg (FixedPcdGet32(PcdEmbeddedFdBaseAddress), r2)
+ LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
add r2, r2, #4
ldr r1, [r2]
# ensure we're jumping to FV version of the code (not boot remapped alias)
ldr r2, StartupAddr
- # jump to SEC C code
+ # jump to PrePeiCore C code
# r0 = core_id
# r1 = pei_core_address
blx r2
-#end of the file
.end
\r
StartupAddr DCD CEntryPoint\r
\r
-SCC_SYS_SW EQU 0x0004\r
-\r
_ModuleEntryPoint\r
// Identify CPU ID\r
mrc p15, 0, r0, c0, c0, 5\r
mov sp, r3\r
\r
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
- LoadConstantToReg (FixedPcdGet32(PcdEmbeddedFdBaseAddress), r2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)\r
add r2, r2, #4\r
ldr r1, [r2]\r
\r
// ensure we're jumping to FV version of the code (not boot remapped alias)\r
ldr r2, StartupAddr\r
\r
- // jump to SEC C code\r
+ // jump to PrePeiCore C code\r
// r0 = core_id\r
// r1 = pei_core_address\r
blx r2\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
ArmPkg/ArmPkg.dec\r
ArmPlatformPkg/ArmPlatformPkg.dec\r
\r
gArmPlatformTokenSpaceGuid.PcdStandalone\r
\r
[FixedPcd]\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
+ gArmTokenSpaceGuid.PcdNormalFdSize\r
\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
ArmPkg/ArmPkg.dec\r
ArmPlatformPkg/ArmPlatformPkg.dec\r
\r
gArmPlatformTokenSpaceGuid.PcdStandalone\r
\r
[FixedPcd]\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize\r
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
+ gArmTokenSpaceGuid.PcdNormalFdSize\r
\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize\r
// If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
if (FeaturePcdGet(PcdStandalone) == FALSE) {
if (CoreId == 0) {
- UINTN* StartAddress = (UINTN*)PcdGet32(PcdEmbeddedFdBaseAddress);
+ UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFdBaseAddress);
// Patch the DRAM to make an infinite loop at the start address
*StartAddress = 0xEAFFFFFE; // opcode for while(1)
SerialPortWrite ((UINT8 *) Buffer, CharCount);
// To enter into Non Secure state, we need to make a return from exception
- return_from_exception(PcdGet32(PcdEmbeddedFdBaseAddress));
+ return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
} else {
// When the primary core is stopped by the hardware debugger to copy the firmware
// into DRAM. The secondary cores are still running. As soon as the first bytes of
}
} else {
// To enter into Non Secure state, we need to make a return from exception
- return_from_exception(PcdGet32(PcdEmbeddedFdBaseAddress));
+ return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
}
//-------------------- Non Secure Mode ---------------------
VOID (*secondary_start)(VOID);
// The secondary cores will execute the fimrware once wake from WFI.
- secondary_start = (VOID (*)())PcdGet32(PcdEmbeddedFdBaseAddress);
+ secondary_start = (VOID (*)())PcdGet32(PcdNormalFdBaseAddress);
ArmCallWFI();
gArmTokenSpaceGuid.PcdVFPEnabled
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
- gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+ gArmTokenSpaceGuid.PcdNormalFdBaseAddress
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize