UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure

https://bugzilla.tianocore.org/show_bug.cgi?id=277

All CPUs use the same MTRR settings.  Move MTRR settings
from a field in the PROCESSOR_SMM_DESCRIPTOR structure into
a module global variable.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index a873b68c30022b3686076eec062c0cdd4a8d613a..01ddaee4e71bd7e8b9e4e66216d667100e87abc7 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -17,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 //\r
 // Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)\r
 //\r
-UINT64                                      gSmiMtrrs[MTRR_NUMBER_OF_FIXED_MTRR + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];\r
+MTRR_SETTINGS                               gSmiMtrrs;\r
 UINT64                                      gPhyMask;\r
 SMM_DISPATCHER_MP_SYNC_DATA                 *mSmmMpSyncData = NULL;\r
 UINTN                                       mSmmMpSyncDataSize;\r
@@ -283,20 +283,12 @@ ReplaceOSMtrrs (
   IN      UINTN                     CpuIndex\r
   )\r
 {\r
-  PROCESSOR_SMM_DESCRIPTOR       *Psd;\r
-  UINT64                         *SmiMtrrs;\r
-  MTRR_SETTINGS                  *BiosMtrr;\r
-\r
-  Psd = (PROCESSOR_SMM_DESCRIPTOR*)(mCpuHotPlugData.SmBase[CpuIndex] + SMM_PSD_OFFSET);\r
-  SmiMtrrs = (UINT64*)(UINTN)Psd->MtrrBaseMaskPtr;\r
-\r
   SmmCpuFeaturesDisableSmrr ();\r
 \r
   //\r
   // Replace all MTRRs registers\r
   //\r
-  BiosMtrr  = (MTRR_SETTINGS*)SmiMtrrs;\r
-  MtrrSetAllMtrrs(BiosMtrr);\r
+  MtrrSetAllMtrrs (&gSmiMtrrs);\r
 }\r
 \r
 /**\r
@@ -1379,7 +1371,6 @@ InitializeMpServiceData (
 {\r
   UINT32                    Cr3;\r
   UINTN                     Index;\r
-  MTRR_SETTINGS             *Mtrr;\r
   PROCESSOR_SMM_DESCRIPTOR  *Psd;\r
   UINT8                     *GdtTssTables;\r
   UINTN                     GdtTableStepSize;\r
@@ -1442,9 +1433,8 @@ InitializeMpServiceData (
   //\r
   // Record current MTRR settings\r
   //\r
-  ZeroMem(gSmiMtrrs, sizeof (gSmiMtrrs));\r
-  Mtrr =  (MTRR_SETTINGS*)gSmiMtrrs;\r
-  MtrrGetAllMtrrs (Mtrr);\r
+  ZeroMem (&gSmiMtrrs, sizeof (gSmiMtrrs));\r
+  MtrrGetAllMtrrs (&gSmiMtrrs);\r
 \r
   return Cr3;\r
 }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index abe5cc612b2055a453dddcccd5cfba1228ab9342..bd6abf28b5f27f138274c6dbe0efd601eae88a5e 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -380,7 +380,7 @@ typedef struct {
   UINT16                            Reserved11;             // Offset 0x50\r
   UINT16                            Reserved12;             // Offset 0x52\r
   UINT32                            Reserved13;             // Offset 0x54\r
-  UINT64                            MtrrBaseMaskPtr;        // Offset 0x58\r
+  UINT64                            Reserved14;             // Offset 0x58\r
 } PROCESSOR_SMM_DESCRIPTOR;\r
 \r
 \r