ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributor

Unlike SGIs and PPIs, which are private to the CPU and are managed at
the redistributor level (which is also a per-CPU construct), shared
interrupts (SPIs) are shared between all CPUs, and therefore managed at
the distributor level (just as on GICv2).

Reported-by: Narinder Dhillon <ndhillonv2@gmail.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 248e896c4b94a354f16a578a3fab826cc09b0904..73795ed4e56c41a67f7d3778b03bce20db908d10 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -19,6 +19,19 @@
 #include <Library/IoLib.h>\r
 #include <Library/PcdLib.h>\r
 \r
+/**\r
+ *\r
+ * Return whether the Source interrupt index refers to a shared interrupt (SPI)\r
+ */\r
+STATIC\r
+BOOLEAN\r
+SourceIsSpi (\r
+  IN UINTN  Source\r
+  )\r
+{\r
+  return Source >= 32 && Source < 1020;\r
+}\r
+\r
 /**\r
  * Return the base address of the GIC redistributor for the current CPU\r
  *\r
@@ -183,7 +196,9 @@ ArmGicEnableInterrupt (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
+      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
+      SourceIsSpi (Source)) {\r
     // Write set-enable register\r
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);\r
   } else {\r
@@ -216,7 +231,9 @@ ArmGicDisableInterrupt (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
+      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
+      SourceIsSpi (Source)) {\r
     // Write clear-enable register\r
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);\r
   } else {\r
@@ -249,7 +266,9 @@ ArmGicIsInterruptEnabled (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
+      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
+      SourceIsSpi (Source)) {\r
     Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);\r
   } else {\r
     GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);\r