MdePkg BaseLib: Convert Ia32/FlushCacheLine.asm to NASM

The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/FlushCacheLine.asm to Ia32/FlushCacheLine.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 94fe72d588b87d29b52340a41fcf9bb76805952c..52e82bd74dde8caad9843246c67cabe36908293b 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -313,6 +313,7 @@
   Ia32/FxRestore.asm | INTEL \r
   Ia32/FxSave.nasm| INTEL\r
   Ia32/FxSave.asm | INTEL \r
+  Ia32/FlushCacheLine.nasm| INTEL\r
   Ia32/FlushCacheLine.asm | INTEL \r
   Ia32/EnablePaging32.asm | INTEL \r
   Ia32/EnableInterrupts.asm | INTEL \r

diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm
new file mode 100644 (file)
index 0000000..ff6fb68
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm
@@ -0,0 +1,51 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   FlushCacheLine.Asm\r
+;\r
+; Abstract:\r
+;\r
+;   AsmFlushCacheLine function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID *\r
+; EFIAPI\r
+; AsmFlushCacheLine (\r
+;   IN      VOID                      *LinearAddress\r
+;   );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmFlushCacheLine)\r
+ASM_PFX(AsmFlushCacheLine):\r
+    ;\r
+    ; If the CPU does not support CLFLUSH instruction,\r
+    ; then promote flush range to flush entire cache.\r
+    ;\r
+    mov     eax, 1\r
+    push    ebx\r
+    cpuid\r
+    pop     ebx\r
+    mov     eax, [esp + 4]\r
+    test    edx, BIT19\r
+    jz      .0\r
+    clflush [eax]\r
+    ret\r
+.0:\r
+    wbinvd\r
+    ret\r
+\r