/** @file\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r
}\r
\r
-RETURN_STATUS\r
+UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicInterruptInterfaceBase,\r
- OUT UINTN *CoreId,\r
- OUT UINTN *InterruptId\r
+ IN UINTN GicInterruptInterfaceBase\r
)\r
{\r
- UINT32 Interrupt;\r
-\r
// Read the Interrupt Acknowledge Register\r
- Interrupt = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
-\r
- // Check if it is a valid interrupt ID\r
- if ((Interrupt & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {\r
- // Got a valid SGI number hence signal End of Interrupt by writing to ICCEOIR\r
- ArmGicEndOfInterrupt (GicInterruptInterfaceBase, Interrupt);\r
-\r
- if (CoreId) {\r
- *CoreId = (Interrupt >> 10) & 0x7;\r
- }\r
- if (InterruptId) {\r
- *InterruptId = Interrupt & 0x3FF;\r
- }\r
- return RETURN_SUCCESS;\r
- } else {\r
- return RETURN_INVALID_PARAMETER;\r
- }\r
+ return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
}\r
\r
VOID\r
UINT32 GicInterrupt;\r
HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
\r
- GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);\r
+ GicInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicInterruptInterfaceBase));\r
\r
// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r
- if (GicInterrupt >= mGicNumInterrupts) {\r
+ if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {\r
// The special interrupt do not need to be acknowledge\r
return;\r
}\r
#/** @file\r
# \r
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#define ARM_GIC_ICCIDR_GET_REVISION(IccIdr) (((IccIdr) >> 12) & 0xF)\r
#define ARM_GIC_ICCIDR_GET_IMPLEMENTER(IccIdr) ((IccIdr) & 0xFFF)\r
\r
+// Bit Mask for\r
+#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
+\r
//\r
// GIC Secure interfaces\r
//\r
IN INTN SgiId\r
);\r
\r
-RETURN_STATUS\r
+UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicInterruptInterfaceBase,\r
- OUT UINTN *CoreId,\r
- OUT UINTN *InterruptId\r
+ IN UINTN GicInterruptInterfaceBase\r
);\r
\r
VOID\r
)\r
{\r
VOID (*secondary_start)(VOID);\r
+ UINTN Interrupt;\r
\r
// The secondary cores will execute the firmware once wake from WFI.\r
secondary_start = (VOID (*)())PcdGet32(PcdFvBaseAddress);\r
ArmCallWFI();\r
\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);\r
+ Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));\r
+ // Check if it is a valid interrupt ID\r
+ if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {\r
+ // Got a valid SGI number hence signal End of Interrupt\r
+ ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);\r
+ }\r
\r
// Jump to secondary core entry point.\r
secondary_start ();\r
UINT32 CoreId;\r
VOID (*SecondaryStart)(VOID);\r
UINTN SecondaryEntryAddr;\r
+ UINTN Interrupt;\r
\r
ClusterId = GET_CLUSTER_ID(MpId);\r
CoreId = GET_CORE_ID(MpId);\r
SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);\r
+ Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));\r
+ // Check if it is a valid interrupt ID\r
+ if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {\r
+ // Got a valid SGI number hence signal End of Interrupt\r
+ ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);\r
+ }\r
} while (SecondaryEntryAddr == 0);\r
\r
// Jump to secondary core entry point.\r
UINT32 CoreId;\r
VOID (*SecondaryStart)(VOID);\r
UINTN SecondaryEntryAddr;\r
+ UINTN Interrupt;\r
\r
ClusterId = GET_CLUSTER_ID(MpId);\r
CoreId = GET_CORE_ID(MpId);\r
SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);\r
+ Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));\r
+ // Check if it is a valid interrupt ID\r
+ if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {\r
+ // Got a valid SGI number hence signal End of Interrupt\r
+ ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);\r
+ }\r
} while (SecondaryEntryAddr == 0);\r
\r
// Jump to secondary core entry point.\r