Revert "OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear"

This reverts commit 39b9a5ffe6618b7870be2a54fe7725000249c33a.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index ae73c63d27d544e58470ad3c502a1b2a5ec4339b..e890e36408a6ad7530581995e926e18968d4f38b 100644 (file)
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -42,8 +42,6 @@ STATIC UINT32 mS3AcpiReservedMemorySize;
 \r
 STATIC UINT16 mQ35TsegMbytes;\r
 \r
-UINT32 mQemuUc32Base;\r
-\r
 VOID\r
 Q35TsegMbytesInitialization (\r
   VOID\r
@@ -665,8 +663,6 @@ QemuInitializeRam (
   // cover it exactly.\r
   //\r
   if (IsMtrrSupported ()) {\r
-    UINT32 Uc32Size;\r
-\r
     MtrrGetAllMtrrs (&MtrrSettings);\r
 \r
     //\r
@@ -693,24 +689,11 @@ QemuInitializeRam (
 \r
     //\r
     // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as\r
-    // uncacheable. Make sure one variable MTRR suffices by truncating the size\r
-    // to a whole power of two. This will round the base *up*, and a gap (not\r
-    // used for either RAM or MMIO) may stay in the middle, marked as\r
-    // cacheable-by-default.\r
-    //\r
-    Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));\r
-    mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);\r
-    if (mQemuUc32Base != LowerMemorySize) {\r
-      DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for "\r
-        "an UC32 size of 0x%x\n", __FUNCTION__, (UINT32)LowerMemorySize,\r
-        mQemuUc32Base, Uc32Size));\r
-    }\r
-\r
-    Status = MtrrSetMemoryAttribute (mQemuUc32Base, Uc32Size,\r
-               CacheUncacheable);\r
+    // uncacheable\r
+    //\r
+    Status = MtrrSetMemoryAttribute (LowerMemorySize,\r
+               SIZE_4GB - LowerMemorySize, CacheUncacheable);\r
     ASSERT_EFI_ERROR (Status);\r
-  } else {\r
-    mQemuUc32Base = (UINT32)LowerMemorySize;\r
   }\r
 }\r
 \r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index c064b4ed9b8fb5e85ef3c9805a4dc4bcb40e1544..fd8eccaf3e50cc133cfc1acb3adb949afc324fa1 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -174,12 +174,14 @@ MemMapInitialization (
   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
 \r
   if (!mXen) {\r
+    UINT32  TopOfLowRam;\r
     UINT64  PciExBarBase;\r
     UINT32  PciBase;\r
     UINT32  PciSize;\r
 \r
+    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
     PciExBarBase = 0;\r
-    PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base;\r
+    PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
       //\r
       // The 32-bit PCI host aperture is expected to fall between the top of\r

diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h
index 4476ddd871cd60f738a8ea4dca9d18dc12ecdd98..81af8b71480f72190882679e37f639169733084b 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.h
+++ b/OvmfPkg/PlatformPei/Platform.h
@@ -114,6 +114,4 @@ extern UINT32 mMaxCpuCount;
 \r
 extern UINT16 mHostBridgeDevId;\r
 \r
-extern UINT32 mQemuUc32Base;\r
-\r
 #endif // _PLATFORM_PEI_H_INCLUDED_\r