--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2011, ARM Limited. All rights reserved.\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmCpuLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#include <Chipset/ArmV7.h>\r
+\r
+VOID\r
+ArmCpuSynchronizeWait (\r
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+ )\r
+{\r
+ // The CortexA8 is a Unicore CPU. We must not use Synchronization functions\r
+ ASSERT(0);\r
+}\r
+\r
+VOID\r
+ArmCpuSynchronizeSignal (\r
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+ )\r
+{\r
+ // The CortexA8 is a Unicore CPU. We must not use Synchronization functions\r
+ ASSERT(0);\r
+}\r
+\r
+VOID\r
+ArmCpuSetup (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ // Enable SWP instructions\r
+ ArmEnableSWPInstruction ();\r
+\r
+ // Enable program flow prediction, if supported.\r
+ ArmEnableBranchPrediction ();\r
+}\r
+\r
+VOID\r
+ArmCpuSetupSmpNonSecure (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ // The CortexA8 is a Unicore CPU. We must not initialize SMP for Non Secure Accesses\r
+ ASSERT(0);\r
+}\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmCortexA8Lib\r
+ FILE_GUID = 34b5745e-f575-44ce-ba2e-df0886807c16\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmCpuLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+\r
+[Sources.common]\r
+ ArmCortexA8Lib.c\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <Library/ArmCpuLib.h>\r
+#include <Chipset/ArmCortexA9.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmCpuSynchronizeWait)\r
+GCC_ASM_EXPORT(ArmGetScuBaseAddress)\r
+GCC_ASM_IMPORT(CArmCpuSynchronizeWait)\r
+\r
+// VOID\r
+// ArmCpuSynchronizeWait (\r
+// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+// );\r
+ASM_PFX(ArmCpuSynchronizeWait):\r
+ cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
+ // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
+ beq ArmWaitScuEnabled\r
+ b CArmCpuSynchronizeWait\r
+\r
+// IN None\r
+// OUT r0 = SCU Base Address\r
+ASM_PFX(ArmGetScuBaseAddress):\r
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ // offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ bx lr\r
+\r
+ASM_PFX(ArmWaitScuEnabled):\r
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ // offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ add r0, r0, #A9_SCU_CONTROL_OFFSET\r
+ ldr r0, [r0]\r
+ cmp r0, #1\r
+ bne ArmWaitScuEnabled\r
+ bx lr\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <Library/ArmCpuLib.h>\r
+#include <Chipset/ArmCortexA9.h>\r
+\r
+ EXPORT ArmCpuSynchronizeWait\r
+ EXPORT ArmGetScuBaseAddress\r
+ IMPORT CArmCpuSynchronizeWait\r
+\r
+ PRESERVE8\r
+ AREA ArmCortexA9Helper, CODE, READONLY\r
+\r
+// VOID\r
+// ArmCpuSynchronizeWait (\r
+// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+// );\r
+ArmCpuSynchronizeWait\r
+ cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
+ // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
+ beq ArmWaitScuEnabled\r
+ b CArmCpuSynchronizeWait\r
+\r
+// IN None\r
+// OUT r0 = SCU Base Address\r
+ArmGetScuBaseAddress\r
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ // offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ bx lr\r
+\r
+ArmWaitScuEnabled\r
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ // offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ add r0, r0, #A9_SCU_CONTROL_OFFSET\r
+ ldr r0, [r0]\r
+ cmp r0, #1\r
+ bne ArmWaitScuEnabled\r
+ bx lr\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2011, ARM Limited. All rights reserved.\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmCpuLib.h>\r
+#include <Library/ArmGicLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Chipset/ArmCortexA9.h>\r
+\r
+VOID\r
+ArmCpuSynchronizeSignal (\r
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+ )\r
+{\r
+ if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {\r
+ // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be\r
+ // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot\r
+ // Mem as been initialized\r
+ } else {\r
+ // Send SGI to all Secondary core to wake them up from WFI state.\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ }\r
+}\r
+\r
+VOID\r
+CArmCpuSynchronizeWait (\r
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+ )\r
+{\r
+ // Waiting for the SGI from the primary core\r
+ ArmCallWFI ();\r
+\r
+ // Acknowledge the interrupt and send End of Interrupt signal.\r
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
+}\r
+\r
+VOID\r
+ArmEnableScu (\r
+ VOID\r
+ )\r
+{\r
+ INTN ScuBase;\r
+\r
+ ScuBase = ArmGetScuBaseAddress();\r
+\r
+ // Invalidate all: write -1 to SCU Invalidate All register\r
+ MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);\r
+ // Enable SCU\r
+ MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);\r
+}\r
+\r
+VOID\r
+ArmCpuSetup (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ // Enable SWP instructions\r
+ ArmEnableSWPInstruction ();\r
+\r
+ // Enable program flow prediction, if supported.\r
+ ArmEnableBranchPrediction ();\r
+\r
+ // If MPCore then Enable the SCU\r
+ if (ArmIsMpCore()) {\r
+ ArmEnableScu ();\r
+ }\r
+}\r
+\r
+\r
+VOID\r
+ArmCpuSetupSmpNonSecure (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ INTN ScuBase;\r
+\r
+ ArmSetAuxCrBit (A9_FEATURE_SMP);\r
+\r
+ // Make the SCU accessible in Non Secure world\r
+ if (IS_PRIMARY_CORE(MpId)) {\r
+ ScuBase = ArmGetScuBaseAddress();\r
+\r
+ // Allow NS access to SCU register\r
+ MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r
+ // Allow NS access to Private Peripherals\r
+ MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r
+ }\r
+}\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmCortexA9Lib\r
+ FILE_GUID = c9709ea3-1beb-4806-889a-8a1d5e5e1697\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmCpuLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+\r
+[LibraryClasses]\r
+ ArmLib\r
+ ArmGicSecLib\r
+ IoLib\r
+ PcdLib\r
+\r
+[Sources.common]\r
+ ArmCortexA9Lib.c\r
+ ArmCortexA9Helper.asm | RVCT\r
+ ArmCortexA9Helper.S | GCC\r
+\r
+[FeaturePcd]\r
+\r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
+\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2011, ARM Limited. All rights reserved.\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __ARM_CORTEX_A9_H__\r
+#define __ARM_CORTEX_A9_H__\r
+\r
+#include <Chipset/ArmV7.h>\r
+\r
+//\r
+// Cortex A9 feature bit definitions\r
+//\r
+#define A9_FEATURE_PARITY (1<<9)\r
+#define A9_FEATURE_AOW (1<<8)\r
+#define A9_FEATURE_EXCL (1<<7)\r
+#define A9_FEATURE_SMP (1<<6)\r
+#define A9_FEATURE_FOZ (1<<3)\r
+#define A9_FEATURE_DPREF (1<<2)\r
+#define A9_FEATURE_HINT (1<<1)\r
+#define A9_FEATURE_FWD (1<<0)\r
+\r
+//\r
+// Cortex A9 Watchdog\r
+//\r
+#define ARM_A9_WATCHDOG_REGION 0x600\r
+\r
+#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20\r
+#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28\r
+\r
+#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)\r
+#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)\r
+#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)\r
+#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)\r
+#define ARM_A9_WATCHDOG_ENABLE 1\r
+\r
+//\r
+// SCU register offsets & masks\r
+//\r
+#define A9_SCU_CONTROL_OFFSET 0x0\r
+#define A9_SCU_CONFIG_OFFSET 0x4\r
+#define A9_SCU_INVALL_OFFSET 0xC\r
+#define A9_SCU_FILT_START_OFFSET 0x40\r
+#define A9_SCU_FILT_END_OFFSET 0x44\r
+#define A9_SCU_SACR_OFFSET 0x50\r
+#define A9_SCU_SSACR_OFFSET 0x54\r
+\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGetScuBaseAddress (\r
+ VOID\r
+ );\r
+\r
+#endif\r
+\r
--- /dev/null
+/** @file
+
+ Copyright (c) 2011, ARM Limited. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARMCPU_LIB__
+#define __ARMCPU_LIB__
+
+// These are #define and not enum to be used in assembly files
+#define ARM_CPU_EVENT_DEFAULT 0
+#define ARM_CPU_EVENT_BOOT_MEM_INIT 1
+#define ARM_CPU_EVENT_SECURE_INIT 2
+
+typedef UINTN ARM_CPU_SYNCHRONIZE_EVENT;
+
+
+VOID
+ArmCpuSynchronizeWait (
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event
+ );
+
+VOID
+ArmCpuSynchronizeSignal (
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event
+ );
+
+VOID
+ArmCpuSetup (
+ IN UINTN MpId
+ );
+
+VOID
+ArmCpuSetupSmpNonSecure (
+ IN UINTN MpId
+ );
+
+#endif // __ARMCPU_LIB__
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