Remove Pcat definition and these definition should be put into module itself.
authorklu2 <klu2@6f19259b-4bc3-4df7-8a09-765794883524>
Thu, 19 Jul 2007 03:28:14 +0000 (03:28 +0000)
committerklu2 <klu2@6f19259b-4bc3-4df7-8a09-765794883524>
Thu, 19 Jul 2007 03:28:14 +0000 (03:28 +0000)
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3346 6f19259b-4bc3-4df7-8a09-765794883524

IntelFrameworkModulePkg/Include/IndustryStandard/Pcat.h [deleted file]

diff --git a/IntelFrameworkModulePkg/Include/IndustryStandard/Pcat.h b/IntelFrameworkModulePkg/Include/IndustryStandard/Pcat.h
deleted file mode 100644 (file)
index 480d6c4..0000000
+++ /dev/null
@@ -1,105 +0,0 @@
-/** @file\r
-  Include file for PC-AT compatability.\r
-\r
-Copyright (c) 2006, Intel Corporation. All rights reserved. \r
-This software and associated documentation (if any) is furnished\r
-under a license and may only be used or copied in accordance\r
-with the terms of the license. Except as permitted by such\r
-license, no part of this software or documentation may be\r
-reproduced, stored in a retrieval system, or transmitted in any\r
-form or by any means without the express written consent of\r
-Intel Corporation.\r
-\r
-**/\r
-\r
-#ifndef _PC_AT_H_\r
-#define _PC_AT_H_\r
-\r
-//\r
-// 8254 Timer\r
-//\r
-#define TIMER0_COUNT_PORT                         0x40\r
-#define TIMER1_COUNT_PORT                         0x41\r
-#define TIMER2_COUNT_PORT                         0x42\r
-#define TIMER_CONTROL_PORT                        0x43\r
-\r
-//\r
-// 8259 PIC interrupt controller\r
-//\r
-\r
-#define PIC_CONTROL_REGISTER_MASTER               0x20\r
-#define PIC_MASK_REGISTER_MASTER                  0x21\r
-#define PIC_CONTROL_REGISTER_SLAVE                0xA0\r
-#define PIC_MASK_REGISTER_SLAVE                   0xA1\r
-#define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER  0x4D0\r
-#define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE   0x4D1\r
-\r
-#define PIC_EOI                                   0x20\r
-\r
-//\r
-// 8237 DMA registers\r
-//\r
-#define R_8237_DMA_BASE_CA_CH0                    0x00\r
-#define R_8237_DMA_BASE_CA_CH1                    0x02\r
-#define R_8237_DMA_BASE_CA_CH2                    0x04\r
-#define R_8237_DMA_BASE_CA_CH3                    0xd6\r
-#define R_8237_DMA_BASE_CA_CH5                    0xc4\r
-#define R_8237_DMA_BASE_CA_CH6                    0xc8\r
-#define R_8237_DMA_BASE_CA_CH7                    0xcc\r
-\r
-#define R_8237_DMA_BASE_CC_CH0                    0x01\r
-#define R_8237_DMA_BASE_CC_CH1                    0x03\r
-#define R_8237_DMA_BASE_CC_CH2                    0x05\r
-#define R_8237_DMA_BASE_CC_CH3                    0xd7\r
-#define R_8237_DMA_BASE_CC_CH5                    0xc6\r
-#define R_8237_DMA_BASE_CC_CH6                    0xca\r
-#define R_8237_DMA_BASE_CC_CH7                    0xce\r
-\r
-#define R_8237_DMA_MEM_LP_CH0                     0x87\r
-#define R_8237_DMA_MEM_LP_CH1                     0x83\r
-#define R_8237_DMA_MEM_LP_CH2                     0x81\r
-#define R_8237_DMA_MEM_LP_CH3                     0x82\r
-#define R_8237_DMA_MEM_LP_CH5                     0x8B\r
-#define R_8237_DMA_MEM_LP_CH6                     0x89\r
-#define R_8237_DMA_MEM_LP_CH7                     0x8A\r
-\r
-\r
-#define R_8237_DMA_COMMAND_CH0_3                  0x08\r
-#define R_8237_DMA_COMMAND_CH4_7                  0xd0\r
-#define   B_8237_DMA_COMMAND_GAP                  0x10\r
-#define   B_8237_DMA_COMMAND_CGE                  0x04\r
-\r
-\r
-#define R_8237_DMA_STA_CH0_3                      0xd8\r
-#define R_8237_DMA_STA_CH4_7                      0xd0\r
-\r
-#define R_8237_DMA_WRSMSK_CH0_3                   0x0a\r
-#define R_8237_DMA_WRSMSK_CH4_7                   0xd4\r
-#define   B_8237_DMA_WRSMSK_CMS                   0x04\r
-\r
-\r
-#define R_8237_DMA_CHMODE_CH0_3                   0x0b\r
-#define R_8237_DMA_CHMODE_CH4_7                   0xd6\r
-#define   V_8237_DMA_CHMODE_DEMAND                0x00\r
-#define   V_8237_DMA_CHMODE_SINGLE                0x40\r
-#define   V_8237_DMA_CHMODE_CASCADE               0xc0\r
-#define   B_8237_DMA_CHMODE_DECREMENT             0x20\r
-#define   B_8237_DMA_CHMODE_INCREMENT             0x00\r
-#define   B_8237_DMA_CHMODE_AE                    0x10\r
-#define   V_8237_DMA_CHMODE_VERIFY                0\r
-#define   V_8237_DMA_CHMODE_IO2MEM                0x04\r
-#define   V_8237_DMA_CHMODE_MEM2IO                0x08\r
-\r
-#define R_8237_DMA_CBPR_CH0_3                     0x0c\r
-#define R_8237_DMA_CBPR_CH4_7                     0xd8\r
-\r
-#define R_8237_DMA_MCR_CH0_3                      0x0d\r
-#define R_8237_DMA_MCR_CH4_7                      0xda\r
-\r
-#define R_8237_DMA_CLMSK_CH0_3                    0x0e\r
-#define R_8237_DMA_CLMSK_CH4_7                    0xdc\r
-\r
-#define R_8237_DMA_WRMSK_CH0_3                    0x0f\r
-#define R_8237_DMA_WRMSK_CH4_7                    0xde\r
-\r
-#endif\r