#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/MtrrLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Protocol/MpService.h>\r
#include <Guid/EventGroup.h>\r
\r
-#include <IndustryStandard/Q35MchIch9.h>\r
-#include <IndustryStandard/QemuCpuHotplug.h>\r
-\r
//\r
// Data structure used to allocate ACPI_CPU_DATA and its supporting structures\r
//\r
EFI_MP_SERVICES_PROTOCOL *MpServices;\r
UINTN NumberOfCpus;\r
VOID *Stack;\r
- UINTN TableSize;\r
- CPU_REGISTER_TABLE *RegisterTable;\r
- UINTN Index;\r
- EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;\r
UINTN GdtSize;\r
UINTN IdtSize;\r
VOID *Gdt;\r
VOID *Idt;\r
EFI_EVENT Event;\r
ACPI_CPU_DATA *OldAcpiCpuData;\r
- BOOLEAN FetchPossibleApicIds;\r
\r
if (!PcdGetBool (PcdAcpiS3Enable)) {\r
return EFI_UNSUPPORTED;\r
ASSERT (AcpiCpuDataEx != NULL);\r
AcpiCpuData = &AcpiCpuDataEx->AcpiCpuData;\r
\r
- //\r
- // The "SMRAM at default SMBASE" feature guarantees that\r
- // QEMU_CPUHP_CMD_GET_ARCH_ID too is available.\r
- //\r
- FetchPossibleApicIds = PcdGetBool (PcdQ35SmramAtDefaultSmbase);\r
-\r
- if (FetchPossibleApicIds) {\r
+ if (PcdGetBool (PcdQ35SmramAtDefaultSmbase)) {\r
NumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
} else {\r
UINTN NumberOfEnabledProcessors;\r
AcpiCpuData->PreSmmInitRegisterTable = OldAcpiCpuData->PreSmmInitRegisterTable;\r
AcpiCpuData->ApLocation = OldAcpiCpuData->ApLocation;\r
CopyMem (&AcpiCpuData->CpuStatus, &OldAcpiCpuData->CpuStatus, sizeof (CPU_STATUS_INFORMATION));\r
- } else {\r
- //\r
- // Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for all CPUs\r
- //\r
- TableSize = 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE);\r
- RegisterTable = (CPU_REGISTER_TABLE *)AllocateZeroPages (TableSize);\r
- ASSERT (RegisterTable != NULL);\r
-\r
- if (FetchPossibleApicIds) {\r
- //\r
- // Write a valid selector so that other hotplug registers can be\r
- // accessed.\r
- //\r
- IoWrite32 (ICH9_CPU_HOTPLUG_BASE + QEMU_CPUHP_W_CPU_SEL, 0);\r
- //\r
- // We'll be fetching the APIC IDs.\r
- //\r
- IoWrite8 (ICH9_CPU_HOTPLUG_BASE + QEMU_CPUHP_W_CMD,\r
- QEMU_CPUHP_CMD_GET_ARCH_ID);\r
- }\r
- for (Index = 0; Index < NumberOfCpus; Index++) {\r
- UINT32 InitialApicId;\r
-\r
- if (FetchPossibleApicIds) {\r
- IoWrite32 (ICH9_CPU_HOTPLUG_BASE + QEMU_CPUHP_W_CPU_SEL,\r
- (UINT32)Index);\r
- InitialApicId = IoRead32 (\r
- ICH9_CPU_HOTPLUG_BASE + QEMU_CPUHP_RW_CMD_DATA);\r
- } else {\r
- Status = MpServices->GetProcessorInfo (\r
- MpServices,\r
- Index,\r
- &ProcessorInfoBuffer\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- InitialApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;\r
- }\r
-\r
- DEBUG ((DEBUG_VERBOSE, "%a: Index=%05Lu ApicId=0x%08x\n", __FUNCTION__,\r
- (UINT64)Index, InitialApicId));\r
-\r
- RegisterTable[Index].InitialApicId = InitialApicId;\r
- RegisterTable[Index].TableLength = 0;\r
- RegisterTable[Index].AllocatedSize = 0;\r
- RegisterTable[Index].RegisterTableEntry = 0;\r
-\r
- RegisterTable[NumberOfCpus + Index].InitialApicId = InitialApicId;\r
- RegisterTable[NumberOfCpus + Index].TableLength = 0;\r
- RegisterTable[NumberOfCpus + Index].AllocatedSize = 0;\r
- RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;\r
- }\r
- AcpiCpuData->RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;\r
- AcpiCpuData->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);\r
}\r
\r
//\r