#/* @file\r
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#*/\r
\r
#/* @file\r
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#*/\r
\r
\r
[BuildOptions]\r
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7\r
- XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG \r
- \r
+ XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
+\r
GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -mfpu=neon\r
- GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG \r
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
\r
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8\r
- RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG \r
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
\r
[LibraryClasses.common]\r
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
\r
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf\r
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf\r
- \r
+\r
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
\r
[LibraryClasses.ARM]\r
#/* @file\r
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#*/\r
\r
#/* @file\r
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#*/\r
\r
#/* @file\r
# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#*/\r
\r
#/* @file\r
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#*/\r
\r
[Defines]\r
INF_VERSION = 0x00010005\r
BASE_NAME = ArmGicDxe\r
- FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882 \r
+ FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
\r
-#------------------------------------------------------------------------------ \r
+#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
#\r
stmfd SP!,{LR} @ Store the link register for the current mode\r
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
stmfd SP!,{R0-R12} @ Store the register state\r
- \r
+\r
mov R0,#0\r
ldr R1,ASM_PFX(CommonExceptionEntry)\r
bx R1\r
\r
ASM_PFX(AsmCommonExceptionEntry):\r
mrc p15, 0, R1, c6, c0, 2 @ Read IFAR\r
- str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR \r
- \r
+ str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR\r
+\r
mrc p15, 0, R1, c5, c0, 1 @ Read IFSR\r
str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r
- \r
+\r
mrc p15, 0, R1, c6, c0, 0 @ Read DFAR\r
str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r
- \r
+\r
mrc p15, 0, R1, c5, c0, 0 @ Read DFSR\r
str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r
- \r
- ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack \r
+\r
+ ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack\r
str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r
and r1, r1, #0x1f @ Check to see if User or System Mode\r
cmp r1, #0x1f\r
ldmneed r2, {lr}^ @ User or System mode, use unbanked register\r
ldmneed r2, {lr} @ All other modes used banked register\r
\r
- ldr R1, [SP, #0x58] @ PC is the LR pushed by srsdb \r
+ ldr R1, [SP, #0x58] @ PC is the LR pushed by srsdb\r
str R1, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r
- \r
- sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack \r
+\r
+ sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack\r
str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r
- \r
- @ R0 is exception type \r
+\r
+ @ R0 is exception type\r
mov R1,SP @ Prepare System Context pointer as an argument for the exception handler\r
blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler\r
- \r
+\r
ldr R2,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR\r
- str R2,[SP,#0x5c] @ Store it back to srsdb stack slot so it can be restored \r
+ str R2,[SP,#0x5c] @ Store it back to srsdb stack slot so it can be restored\r
\r
ldr R2,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC\r
- str R2,[SP,#0x58] @ Store it back to srsdb stack slot so it can be restored \r
+ str R2,[SP,#0x58] @ Store it back to srsdb stack slot so it can be restored\r
\r
ldmfd SP!,{R0-R12} @ Restore general purpose registers\r
@ Exception handler can not change SP or LR as we would blow chunks\r
- \r
+\r
add SP,SP,#0x20 @ Clear out the remaining stack space\r
ldmfd SP!,{LR} @ restore the link register for this context\r
rfefd SP! @ return from exception via srsdb stack slot\r
-//------------------------------------------------------------------------------ \r
+//------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
//\r
\r
PRESERVE8\r
AREA DxeExceptionHandlers, CODE, READONLY\r
- \r
+\r
ExceptionHandlersStart\r
\r
Reset\r
AsmCommonExceptionEntry\r
mrc p15, 0, r1, c6, c0, 2 ; Read IFAR\r
stmfd SP!,{R1} ; Store the IFAR\r
- \r
+\r
mrc p15, 0, r1, c5, c0, 1 ; Read IFSR\r
stmfd SP!,{R1} ; Store the IFSR\r
- \r
+\r
mrc p15, 0, r1, c6, c0, 0 ; Read DFAR\r
stmfd SP!,{R1} ; Store the DFAR\r
- \r
+\r
mrc p15, 0, r1, c5, c0, 0 ; Read DFSR\r
stmfd SP!,{R1} ; Store the DFSR\r
- \r
+\r
mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)\r
stmfd SP!,{R1} ; Store the SPSR\r
- \r
+\r
stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)\r
stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register\r
nop ; Required by ARM architecture\r
SUB SP,SP,#0x08 ; Adjust stack pointer\r
stmfd SP!,{R2-R12} ; Store general purpose registers\r
- \r
+\r
ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)\r
ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)\r
stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1\r
- \r
+\r
mov R1,SP ; Prepare System Context pointer as an argument for the exception handler\r
- \r
+\r
sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment\r
blx CommonCExceptionHandler ; Call exception handler\r
add SP,SP,#4 ; Adjust SP back to where we were\r
- \r
+\r
ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed\r
MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler\r
\r
ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)\r
add SP,SP,#0x1C ; Clear out the remaining stack space\r
movs PC,LR ; Return from exception\r
- \r
+\r
END\r
\r
\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Copyright (c) 2014, ARM Limited. All rights reserved.<BR>\r
- \r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
**/\r
\r
-#include "CpuDxe.h" \r
+#include "CpuDxe.h"\r
\r
//FIXME: Will not compile on non-ARMv7 builds\r
#include <Chipset/ArmV7.h>\r
\r
\r
/**\r
- This function registers and enables the handler specified by InterruptHandler for a processor \r
- interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
- handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
+ This function registers and enables the handler specified by InterruptHandler for a processor\r
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the\r
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.\r
The installed handler is called once for each processor interrupt or exception.\r
\r
@param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
DEBUG ((EFI_D_ERROR, "Unknown exception type %d from %08x\n", ExceptionType, SystemContext.SystemContextArm->PC));\r
ASSERT (FALSE);\r
}\r
- \r
+\r
if (ExceptionType == EXCEPT_ARM_SOFTWARE_INTERRUPT) {\r
//\r
// ARM JTAG debuggers some times use this vector, so it is not an error to get one\r
Cpu->DisableInterrupt (Cpu);\r
\r
//\r
- // EFI does not use the FIQ, but a debugger might so we must disable \r
- // as we take over the exception vectors. \r
+ // EFI does not use the FIQ, but a debugger might so we must disable\r
+ // as we take over the exception vectors.\r
//\r
FiqEnabled = ArmGetFiqState ();\r
ArmDisableFiq ();\r
}\r
\r
if (IrqEnabled) {\r
- // \r
+ //\r
// Restore interrupt state\r
//\r
Status = Cpu->EnableInterrupt (Cpu);\r
-#------------------------------------------------------------------------------ \r
+#------------------------------------------------------------------------------\r
#\r
# Use ARMv6 instruction to operate on a single stack\r
#\r
This is the stack constructed by the exception handler (low address to high address)\r
# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM\r
Reg Offset\r
- === ====== \r
+ === ======\r
R0 0x00 # stmfd SP!,{R0-R12}\r
R1 0x04\r
R2 0x08\r
DFAR 0x48\r
IFSR 0x4c\r
IFAR 0x50\r
- \r
+\r
LR 0x54 # SVC Link register (we need to restore it)\r
- \r
- LR 0x58 # pushed by srsfd \r
- CPSR 0x5c \r
+\r
+ LR 0x58 # pushed by srsfd\r
+ CPSR 0x5c\r
\r
*/\r
- \r
+\r
\r
GCC_ASM_EXPORT(ExceptionHandlersStart)\r
GCC_ASM_EXPORT(ExceptionHandlersEnd)\r
stmfd SP!,{LR} @ Store the link register for the current mode\r
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
stmfd SP!,{R0-R12} @ Store the register state\r
- \r
+\r
mov R0,#0 @ ExceptionType\r
ldr R1,ASM_PFX(CommonExceptionEntry)\r
bx R1\r
ASM_PFX(ExceptionHandlersEnd):\r
\r
//\r
-// This code runs from CpuDxe driver loaded address. It is patched into \r
+// This code runs from CpuDxe driver loaded address. It is patched into\r
// CommonExceptionEntry.\r
//\r
ASM_PFX(AsmCommonExceptionEntry):\r
mrc p15, 0, R1, c6, c0, 2 @ Read IFAR\r
- str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR \r
- \r
+ str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR\r
+\r
mrc p15, 0, R1, c5, c0, 1 @ Read IFSR\r
str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r
- \r
+\r
mrc p15, 0, R1, c6, c0, 0 @ Read DFAR\r
str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r
- \r
+\r
mrc p15, 0, R1, c5, c0, 0 @ Read DFSR\r
str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r
- \r
- ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack \r
+\r
+ ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack\r
str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r
\r
add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
and R3, R1, #0x1f @ Check CPSR to see if User or System Mode\r
cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))\r
- cmpne R3, #0x10 @ \r
+ cmpne R3, #0x10 @\r
stmeqed R2, {lr}^ @ save unbanked lr\r
- @ else \r
+ @ else\r
stmneed R2, {lr} @ save SVC lr\r
\r
\r
- ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd \r
+ ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd\r
@ Check to see if we have to adjust for Thumb entry\r
sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType == 2)) {\r
- cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb \r
+ cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb\r
bhi NoAdjustNeeded\r
- \r
- tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry \r
+\r
+ tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry\r
addne R5, R5, #2 @ PC += 2;\r
strne R5,[SP,#0x58] @ Update LR value pushed by srsfd\r
- \r
+\r
NoAdjustNeeded:\r
\r
str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r
- \r
+\r
add R1, SP, #0x60 @ We pushed 0x60 bytes on the stack\r
str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r
- \r
- @ R0 is ExceptionType \r
- mov R1,SP @ R1 is SystemContext \r
+\r
+ @ R0 is ExceptionType\r
+ mov R1,SP @ R1 is SystemContext\r
\r
#if (FixedPcdGet32(PcdVFPEnabled))\r
vpush {d0-d15} @ save vstm registers in case they are used in optimizations\r
tst R4, #4\r
subne SP, SP, #4 @ Adjust SP if not 8-byte aligned\r
\r
-/* \r
+/*\r
VOID\r
EFIAPI\r
CommonCExceptionHandler (\r
IN OUT EFI_SYSTEM_CONTEXT SystemContext R1\r
)\r
\r
-*/ \r
+*/\r
blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler\r
\r
mov SP, R4 @ Restore SP\r
\r
#if (FixedPcdGet32(PcdVFPEnabled))\r
- vpop {d0-d15} \r
+ vpop {d0-d15}\r
#endif\r
\r
ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR\r
\r
ldr R1, [SP, #0x44] @ Restore EFI_SYSTEM_CONTEXT_ARM.DFSR\r
mcr p15, 0, R1, c5, c0, 0 @ Write DFSR\r
- \r
+\r
ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC\r
- str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored \r
+ str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored\r
\r
ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR\r
- str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored \r
- \r
+ str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored\r
+\r
add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry\r
add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
and R1, R1, #0x1f @ Check to see if User or System Mode\r
cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))\r
- cmpne R1, #0x10 @ \r
+ cmpne R1, #0x10 @\r
ldmeqed R2, {lr}^ @ restore unbanked lr\r
@ else\r
ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}\r
- \r
+\r
ldmfd SP!,{R0-R12} @ Restore general purpose registers\r
@ Exception handler can not change SP\r
- \r
+\r
add SP,SP,#0x20 @ Clear out the remaining stack space\r
ldmfd SP!,{LR} @ restore the link register for this context\r
rfefd SP! @ return from exception via srsfd stack slot\r
- \r
+\r
-//------------------------------------------------------------------------------ \r
+//------------------------------------------------------------------------------\r
//\r
// Use ARMv6 instruction to operate on a single stack\r
//\r
This is the stack constructed by the exception handler (low address to high address)\r
# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM\r
Reg Offset\r
- === ====== \r
+ === ======\r
R0 0x00 # stmfd SP!,{R0-R12}\r
R1 0x04\r
R2 0x08\r
DFAR 0x48\r
IFSR 0x4c\r
IFAR 0x50\r
- \r
+\r
LR 0x54 # SVC Link register (we need to restore it)\r
- \r
- LR 0x58 # pushed by srsfd \r
- CPSR 0x5c \r
+\r
+ LR 0x58 # pushed by srsfd\r
+ CPSR 0x5c\r
\r
*/\r
- \r
- \r
+\r
+\r
EXPORT ExceptionHandlersStart\r
EXPORT ExceptionHandlersEnd\r
EXPORT CommonExceptionEntry\r
\r
PRESERVE8\r
AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5\r
- \r
+\r
//\r
// This code gets copied to the ARM vector table\r
// ExceptionHandlersStart - ExceptionHandlersEnd gets copied\r
stmfd SP!,{LR} ; Store the link register for the current mode\r
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
stmfd SP!,{R0-R12} ; Store the register state\r
- \r
+\r
mov R0,#0 ; ExceptionType\r
ldr R1,CommonExceptionEntry\r
bx R1\r
stmfd SP!,{R0-R12} ; Store the register state\r
\r
mov R0,#1 ; ExceptionType\r
- ldr R1,CommonExceptionEntry; \r
+ ldr R1,CommonExceptionEntry;\r
bx R1\r
\r
SoftwareInterruptEntry\r
ExceptionHandlersEnd\r
\r
//\r
-// This code runs from CpuDxe driver loaded address. It is patched into \r
+// This code runs from CpuDxe driver loaded address. It is patched into\r
// CommonExceptionEntry.\r
//\r
AsmCommonExceptionEntry\r
mrc p15, 0, R1, c6, c0, 2 ; Read IFAR\r
- str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR \r
- \r
+ str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR\r
+\r
mrc p15, 0, R1, c5, c0, 1 ; Read IFSR\r
str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r
- \r
+\r
mrc p15, 0, R1, c6, c0, 0 ; Read DFAR\r
str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r
- \r
+\r
mrc p15, 0, R1, c5, c0, 0 ; Read DFSR\r
str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r
- \r
- ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack \r
+\r
+ ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack\r
str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r
\r
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
and R3, R1, #0x1f ; Check CPSR to see if User or System Mode\r
cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))\r
- cmpne R3, #0x10 ; \r
+ cmpne R3, #0x10 ;\r
stmeqed R2, {lr}^ ; save unbanked lr\r
- ; else \r
+ ; else\r
stmneed R2, {lr} ; save SVC lr\r
\r
\r
- ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd \r
+ ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd\r
; Check to see if we have to adjust for Thumb entry\r
sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType == 2)) {\r
- cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb \r
+ cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb\r
bhi NoAdjustNeeded\r
- \r
- tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry \r
+\r
+ tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry\r
addne R5, R5, #2 ; PC += 2;\r
strne R5,[SP,#0x58] ; Update LR value pushed by srsfd\r
- \r
+\r
NoAdjustNeeded\r
\r
str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r
- \r
+\r
add R1, SP, #0x60 ; We pushed 0x60 bytes on the stack\r
str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r
- \r
- ; R0 is ExceptionType \r
- mov R1,SP ; R1 is SystemContext \r
+\r
+ ; R0 is ExceptionType\r
+ mov R1,SP ; R1 is SystemContext\r
\r
#if (FixedPcdGet32(PcdVFPEnabled))\r
vpush {d0-d15} ; save vstm registers in case they are used in optimizations\r
tst R4, #4\r
subne SP, SP, #4 ; Adjust SP if not 8-byte aligned\r
\r
-/* \r
+/*\r
VOID\r
EFIAPI\r
CommonCExceptionHandler (\r
#if (FixedPcdGet32(PcdVFPEnabled))\r
vpop {d0-d15}\r
#endif\r
- \r
+\r
ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR\r
mcr p15, 0, R1, c5, c0, 1 ; Write IFSR\r
\r
ldr R1, [SP, #0x44] ; Restore EFI_SYSTEM_CONTEXT_ARM.DFSR\r
mcr p15, 0, R1, c5, c0, 0 ; Write DFSR\r
- \r
+\r
ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC\r
- str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored \r
+ str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored\r
\r
ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR\r
- str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored \r
- \r
+ str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored\r
+\r
add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry\r
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
and R1, R1, #0x1f ; Check to see if User or System Mode\r
cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))\r
- cmpne R1, #0x10 ; \r
+ cmpne R1, #0x10 ;\r
ldmeqed R2, {lr}^ ; restore unbanked lr\r
; else\r
ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}\r
- \r
+\r
ldmfd SP!,{R0-R12} ; Restore general purpose registers\r
; Exception handler can not change SP\r
- \r
+\r
add SP,SP,#0x20 ; Clear out the remaining stack space\r
ldmfd SP!,{LR} ; restore the link register for this context\r
rfefd SP! ; return from exception via srsfd stack slot\r
- \r
+\r
END\r
\r
\r
// Second Level Descriptors\r
typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r
\r
-EFI_STATUS \r
+EFI_STATUS\r
SectionToGcdAttributes (\r
IN UINT32 SectionAttributes,\r
OUT UINT64 *GcdAttributes\r
\r
// Calculate number of 4KB page table entries to change\r
NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;\r
- \r
+\r
// Iterate for the number of 4KB pages to change\r
Offset = 0;\r
for(p = 0; p < NumPageEntries; p++) {\r
// Calculate index into first level translation table for page table value\r
- \r
+\r
FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
if (EFI_ERROR(Status)) {\r
// Exit for loop\r
- break; \r
- } \r
- \r
+ break;\r
+ }\r
+\r
// Re-read descriptor\r
Descriptor = FirstLevelTable[FirstLevelIdx];\r
}\r
// Make this virtual address point at a physical page\r
PageTableEntry &= ~VirtualMask;\r
}\r
- \r
+\r
if (CurrentPageTableEntry != PageTableEntry) {\r
Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r
if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {\r
WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);\r
}\r
\r
- // Only need to update if we are changing the entry \r
- PageTable[PageTableIndex] = PageTableEntry; \r
+ // Only need to update if we are changing the entry\r
+ PageTable[PageTableIndex] = PageTableEntry;\r
ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
}\r
\r
Status = EFI_SUCCESS;\r
Offset += TT_DESCRIPTOR_PAGE_SIZE;\r
- \r
+\r
} // End first level translation table loop\r
\r
return Status;\r
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
// EntryValue: values at bit positions specified by EntryMask\r
\r
- // Make sure we handle a section range that is unmapped \r
+ // Make sure we handle a section range that is unmapped\r
EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;\r
EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;\r
\r
\r
// calculate number of 1MB first level entries this applies to\r
NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;\r
- \r
+\r
// iterate through each descriptor\r
for(i=0; i<NumSections; i++) {\r
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r
Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);\r
} else {\r
// still a section entry\r
- \r
+\r
// mask off appropriate fields\r
Descriptor = CurrentDescriptor & ~EntryMask;\r
\r
WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r
}\r
\r
- // Only need to update if we are changing the descriptor \r
+ // Only need to update if we are changing the descriptor\r
FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r
}\r
return Status;\r
}\r
\r
-EFI_STATUS \r
+EFI_STATUS\r
ConvertSectionToPages (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress\r
)\r
)\r
{\r
EFI_STATUS Status;\r
- \r
+\r
if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
// Is the base and length a multiple of 1 MB?\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Copyright (c) 2011, ARM Limited. All rights reserved.\r
- \r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
\r
/**\r
- This function flushes the range of addresses from Start to Start+Length \r
- from the processor's data cache. If Start is not aligned to a cache line \r
- boundary, then the bytes before Start to the preceding cache line boundary \r
- are also flushed. If Start+Length is not aligned to a cache line boundary, \r
- then the bytes past Start+Length to the end of the next cache line boundary \r
- are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r
- supported. If the data cache is fully coherent with all DMA operations, then \r
- this function can just return EFI_SUCCESS. If the processor does not support \r
+ This function flushes the range of addresses from Start to Start+Length\r
+ from the processor's data cache. If Start is not aligned to a cache line\r
+ boundary, then the bytes before Start to the preceding cache line boundary\r
+ are also flushed. If Start+Length is not aligned to a cache line boundary,\r
+ then the bytes past Start+Length to the end of the next cache line boundary\r
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r
+ supported. If the data cache is fully coherent with all DMA operations, then\r
+ this function can just return EFI_SUCCESS. If the processor does not support\r
flushing a range of the data cache, then the entire data cache can be flushed.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
default:\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
- This function enables interrupt processing by the processor. \r
+ This function enables interrupt processing by the processor.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
\r
\r
/**\r
- This function retrieves the processor's current interrupt state a returns it in \r
- State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r
+ This function retrieves the processor's current interrupt state a returns it in\r
+ State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
are currently disabled, then FALSE is returned.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
/**\r
This function generates an INIT on the processor. If this function succeeds, then the\r
- processor will be reset, and control will not be returned to the caller. If InitType is \r
- not supported by this processor, or the processor cannot programmatically generate an \r
- INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r
+ processor will be reset, and control will not be returned to the caller. If InitType is\r
+ not supported by this processor, or the processor cannot programmatically generate an\r
+ INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r
occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
/**\r
Callback function for idle events.\r
- \r
+\r
@param Event Event whose notification function is being invoked.\r
@param Context The pointer to the notification function's context,\r
which is implementation-dependent.\r
EFI_STATUS Status;\r
EFI_EVENT IdleLoopEvent;\r
\r
- InitializeExceptions (&mCpu); \r
- \r
+ InitializeExceptions (&mCpu);\r
+\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
- &mCpuHandle, \r
- &gEfiCpuArchProtocolGuid, &mCpu, \r
+ &mCpuHandle,\r
+ &gEfiCpuArchProtocolGuid, &mCpu,\r
&gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,\r
NULL\r
);\r
- \r
+\r
//\r
// Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r
// and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r
// after the protocol is installed\r
//\r
SyncCacheConfig (&mCpu);\r
- \r
+\r
// If the platform is a MPCore system then install the Configuration Table describing the\r
// secondary core states\r
if (ArmIsMpCore()) {\r
\r
\r
/**\r
- This function registers and enables the handler specified by InterruptHandler for a processor \r
- interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
- handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
+ This function registers and enables the handler specified by InterruptHandler for a processor\r
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the\r
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.\r
The installed handler is called once for each processor interrupt or exception.\r
\r
@param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
\r
\r
/**\r
- This function registers and enables the handler specified by InterruptHandler for a processor \r
- interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
- handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
+ This function registers and enables the handler specified by InterruptHandler for a processor\r
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the\r
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.\r
The installed handler is called once for each processor interrupt or exception.\r
\r
@param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
);\r
\r
-EFI_STATUS \r
+EFI_STATUS\r
ConvertSectionToPages (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress\r
);\r
#/** @file\r
-# \r
+#\r
# DXE CPU driver\r
-# \r
+#\r
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
#\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
-# \r
+#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-# \r
+#\r
#**/\r
\r
[Defines]\r
[Pcd.common]\r
gArmTokenSpaceGuid.PcdVFPEnabled\r
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\r
- \r
+\r
[FeaturePcd.common]\r
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport\r
gArmTokenSpaceGuid.PcdRelocateVectorTable\r
Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>\r
Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>\r
\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
MemoryInit.c\r
- \r
+\r
Abstract:\r
\r
PEIM to provide fake memory init\r
\r
FileHandle - Handle of the file being invoked.\r
PeiServices - Describes the list of possible PEI Services.\r
- \r
+\r
Returns:\r
\r
Status - EFI_SUCCESS if the boot mode could be set\r
\r
[Ppis]\r
gArmMpCoreInfoPpiGuid\r
- \r
+\r
[Guids]\r
gArmMpCoreInfoGuid\r
\r
\r
[Depex]\r
gEfiPeiMemoryDiscoveredPpiGuid\r
- \r
+\r
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;\r
\r
/**\r
- This function registers the handler NotifyFunction so it is called every time \r
- the timer interrupt fires. It also passes the amount of time since the last \r
- handler call to the NotifyFunction. If NotifyFunction is NULL, then the \r
- handler is unregistered. If the handler is registered, then EFI_SUCCESS is \r
- returned. If the CPU does not support registering a timer interrupt handler, \r
- then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler \r
- when a handler is already registered, then EFI_ALREADY_STARTED is returned. \r
- If an attempt is made to unregister a handler when a handler is not registered, \r
- then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to \r
- register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR \r
+ This function registers the handler NotifyFunction so it is called every time\r
+ the timer interrupt fires. It also passes the amount of time since the last\r
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the\r
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is\r
+ returned. If the CPU does not support registering a timer interrupt handler,\r
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler\r
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.\r
+ If an attempt is made to unregister a handler when a handler is not registered,\r
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to\r
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR\r
is returned.\r
\r
@param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
\r
/**\r
\r
- This function adjusts the period of timer interrupts to the value specified \r
- by TimerPeriod. If the timer period is updated, then the selected timer \r
- period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If \r
- the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. \r
- If an error occurs while attempting to update the timer period, then the \r
- timer hardware will be put back in its state prior to this call, and \r
- EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt \r
- is disabled. This is not the same as disabling the CPU's interrupts. \r
- Instead, it must either turn off the timer hardware, or it must adjust the \r
- interrupt controller so that a CPU interrupt is not generated when the timer \r
- interrupt fires. \r
+ This function adjusts the period of timer interrupts to the value specified\r
+ by TimerPeriod. If the timer period is updated, then the selected timer\r
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If\r
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.\r
+ If an error occurs while attempting to update the timer period, then the\r
+ timer hardware will be put back in its state prior to this call, and\r
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt\r
+ is disabled. This is not the same as disabling the CPU's interrupts.\r
+ Instead, it must either turn off the timer hardware, or it must adjust the\r
+ interrupt controller so that a CPU interrupt is not generated when the timer\r
+ interrupt fires.\r
\r
@param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If\r
)\r
{\r
UINT64 TimerTicks;\r
- \r
+\r
// Always disable the timer\r
ArmArchTimerDisableTimer ();\r
\r
}\r
\r
/**\r
- This function retrieves the period of timer interrupts in 100 ns units, \r
- returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod \r
- is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is \r
+ This function retrieves the period of timer interrupts in 100 ns units,\r
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod\r
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is\r
returned, then the timer is currently disabled.\r
\r
@param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
}\r
\r
/**\r
- This function generates a soft timer interrupt. If the platform does not support soft \r
- timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. \r
- If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() \r
- service, then a soft timer interrupt will be generated. If the timer interrupt is \r
- enabled when this service is called, then the registered handler will be invoked. The \r
- registered handler should not be able to distinguish a hardware-generated timer \r
+ This function generates a soft timer interrupt. If the platform does not support soft\r
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.\r
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()\r
+ service, then a soft timer interrupt will be generated. If the timer interrupt is\r
+ enabled when this service is called, then the registered handler will be invoked. The\r
+ registered handler should not be able to distinguish a hardware-generated timer\r
interrupt from a software-generated timer interrupt.\r
\r
@param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
#/** @file\r
-# \r
+#\r
# Component description file for Timer DXE module\r
-# \r
+#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
-# \r
+#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-# \r
+#\r
#**/\r
\r
[Defines]\r
INF_VERSION = 0x00010005\r
BASE_NAME = ArmTimerDxe\r
- FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7 \r
+ FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
\r
BaseMemoryLib\r
DebugLib\r
UefiDriverEntryPoint\r
- IoLib \r
+ IoLib\r
\r
[Guids]\r
\r
[Protocols]\r
- gEfiTimerArchProtocolGuid \r
+ gEfiTimerArchProtocolGuid\r
gHardwareInterruptProtocolGuid\r
\r
[Pcd.common]\r
gEmbeddedTokenSpaceGuid.PcdTimerPeriod\r
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum \r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum\r
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum\r
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz \r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz\r
\r
[Depex]\r
gHardwareInterruptProtocolGuid\r
- \r
\ No newline at end of file
#include <Guid/FileSystemVolumeLabelInfo.h>\r
\r
#include <Library/BaseLib.h>\r
-#include <Library/BaseMemoryLib.h> \r
+#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/SemihostLib.h>\r
)\r
{\r
SEMIHOST_FCB *RootFcb = NULL;\r
- \r
+\r
if (Root == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
if (RootFcb == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
- \r
+\r
RootFcb->IsRoot = TRUE;\r
RootFcb->Info.Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;\r
\r
if (EFI_ERROR(Status)) {\r
return Status;\r
}\r
- \r
+\r
IsRoot = FALSE;\r
}\r
\r
FreeFCB (Fcb);\r
}\r
}\r
- \r
+\r
return Status;\r
}\r
\r
*BufferSize -= WriteSize;\r
Fcb->Position += *BufferSize;\r
}\r
- \r
+\r
return Status;\r
}\r
\r
)\r
{\r
SEMIHOST_FCB *Fcb = NULL;\r
- \r
+\r
if (Position == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
Info->FileName[0] = L'\0';\r
} else {\r
for (Index = 0; Index < NameSize; Index++) {\r
- Info->FileName[Index] = Fcb->FileName[Index]; \r
+ Info->FileName[Index] = Fcb->FileName[Index];\r
}\r
}\r
\r
- *BufferSize = ResultSize; \r
+ *BufferSize = ResultSize;\r
\r
return EFI_SUCCESS;\r
}\r
EFI_FILE_SYSTEM_INFO *Info = NULL;\r
EFI_STATUS Status;\r
UINTN ResultSize = SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (mSemihostFsLabel);\r
- \r
+\r
if (*BufferSize >= ResultSize) {\r
ZeroMem (Buffer, ResultSize);\r
Status = EFI_SUCCESS;\r
- \r
+\r
Info = Buffer;\r
\r
Info->Size = ResultSize;\r
Status = EFI_BUFFER_TOO_SMALL;\r
}\r
\r
- *BufferSize = ResultSize; \r
+ *BufferSize = ResultSize;\r
return Status;\r
}\r
\r
SEMIHOST_FCB *Fcb;\r
EFI_STATUS Status;\r
UINTN ResultSize;\r
- \r
+\r
Fcb = SEMIHOST_FCB_FROM_THIS(File);\r
- \r
+\r
if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid) != 0) {\r
Status = GetFilesystemInfo (Fcb, BufferSize, Buffer);\r
} else if (CompareGuid (InformationType, &gEfiFileInfoGuid) != 0) {\r
}\r
\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
- &gInstallHandle, \r
- &gEfiSimpleFileSystemProtocolGuid, &gSemihostFs, \r
+ &gInstallHandle,\r
+ &gEfiSimpleFileSystemProtocolGuid, &gSemihostFs,\r
&gEfiDevicePathProtocolGuid, &gDevicePath,\r
NULL\r
);\r
FreePool (mSemihostFsLabel);\r
}\r
}\r
- \r
+\r
return Status;\r
}\r
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>\r
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.\r
#\r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#**/\r
\r
\r
[Sources.ARM, Sources.AARCH64]\r
Arm/SemihostFs.c\r
- \r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
ArmPkg/ArmPkg.dec\r
[Protocols]\r
gEfiSimpleFileSystemProtocolGuid\r
gEfiDevicePathProtocolGuid\r
- \r
+\r
ldr r1, =Address ; \\r
ldr r0, =Data ; \\r
str r0, [r1]\r
- \r
+\r
#define MmioOr32(Address, OrData) \\r
ldr r1, =Address ; \\r
ldr r2, =OrData ; \\r
and r0, r0, r2 ; \\r
ldr r2, =OrData ; \\r
orr r0, r0, r2 ; \\r
- str r0, [r1] \r
+ str r0, [r1]\r
\r
#define MmioWriteFromReg32(Address, Reg) \\r
ldr r1, =Address ; \\r
#else\r
\r
//\r
-// Use ARM assembly macros, form armasam \r
+// Use ARM assembly macros, form armasam\r
//\r
// Less magic in the macros if ldr reg, =expr works\r
//\r
\r
// returns Data in R0 and Address in R1, and OrData in r2\r
#define MmioOr32(Address, OrData) MmioOr32Macro Address, OrData\r
- \r
+\r
\r
// returns _Data in R0 and _Address in R1, and _OrData in r2\r
\r
; Copyright (c) 2009, Apple Inc. All rights reserved.<BR>\r
; Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
;\r
-; This program and the accompanying materials \r
-; are licensed and made available under the terms and conditions of the BSD License \r
-; which accompanies this distribution. The full text of the license may be found at \r
-; http://opensource.org/licenses/bsd-license.php \r
-; \r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
;**/\r
\r
\r
- MACRO \r
- MmioWrite32Macro $Address, $Data \r
- ldr r1, = ($Address) \r
- ldr r0, = ($Data) \r
- str r0, [r1] \r
+ MACRO\r
+ MmioWrite32Macro $Address, $Data\r
+ ldr r1, = ($Address)\r
+ ldr r0, = ($Data)\r
+ str r0, [r1]\r
MEND\r
- \r
- MACRO \r
- MmioOr32Macro $Address, $OrData \r
- ldr r1, =($Address) \r
- ldr r2, =($OrData) \r
- ldr r0, [r1] \r
- orr r0, r0, r2 \r
- str r0, [r1] \r
+\r
+ MACRO\r
+ MmioOr32Macro $Address, $OrData\r
+ ldr r1, =($Address)\r
+ ldr r2, =($OrData)\r
+ ldr r0, [r1]\r
+ orr r0, r0, r2\r
+ str r0, [r1]\r
MEND\r
\r
- MACRO \r
- MmioAnd32Macro $Address, $AndData \r
- ldr r1, =($Address) \r
- ldr r2, =($AndData) \r
- ldr r0, [r1] \r
- and r0, r0, r2 \r
- str r0, [r1] \r
+ MACRO\r
+ MmioAnd32Macro $Address, $AndData\r
+ ldr r1, =($Address)\r
+ ldr r2, =($AndData)\r
+ ldr r0, [r1]\r
+ and r0, r0, r2\r
+ str r0, [r1]\r
MEND\r
\r
- MACRO \r
- MmioAndThenOr32Macro $Address, $AndData, $OrData \r
- ldr r1, =($Address) \r
- ldr r0, [r1] \r
- ldr r2, =($AndData) \r
- and r0, r0, r2 \r
- ldr r2, =($OrData) \r
- orr r0, r0, r2 \r
- str r0, [r1] \r
+ MACRO\r
+ MmioAndThenOr32Macro $Address, $AndData, $OrData\r
+ ldr r1, =($Address)\r
+ ldr r0, [r1]\r
+ ldr r2, =($AndData)\r
+ and r0, r0, r2\r
+ ldr r2, =($OrData)\r
+ orr r0, r0, r2\r
+ str r0, [r1]\r
MEND\r
\r
- MACRO \r
- MmioWriteFromReg32Macro $Address, $Reg \r
- ldr r1, =($Address) \r
- str $Reg, [r1] \r
+ MACRO\r
+ MmioWriteFromReg32Macro $Address, $Reg\r
+ ldr r1, =($Address)\r
+ str $Reg, [r1]\r
MEND\r
\r
- MACRO \r
- MmioRead32Macro $Address \r
- ldr r1, =($Address) \r
- ldr r0, [r1] \r
+ MACRO\r
+ MmioRead32Macro $Address\r
+ ldr r1, =($Address)\r
+ ldr r0, [r1]\r
+ MEND\r
+\r
+ MACRO\r
+ MmioReadToReg32Macro $Address, $Reg\r
+ ldr r1, =($Address)\r
+ ldr $Reg, [r1]\r
MEND\r
\r
- MACRO \r
- MmioReadToReg32Macro $Address, $Reg \r
- ldr r1, =($Address) \r
- ldr $Reg, [r1] \r
+ MACRO\r
+ LoadConstantMacro $Data\r
+ ldr r0, =($Data)\r
MEND\r
\r
- MACRO \r
- LoadConstantMacro $Data \r
- ldr r0, =($Data) \r
+ MACRO\r
+ LoadConstantToRegMacro $Data, $Reg\r
+ ldr $Reg, =($Data)\r
MEND\r
\r
- MACRO \r
- LoadConstantToRegMacro $Data, $Reg \r
- ldr $Reg, =($Data) \r
- MEND \r
- \r
; The reserved place must be 8-bytes aligned for pushing 64-bit variable on the stack\r
; Note: Global Size will be modified\r
MACRO\r
#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \\r
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK | \\r
- TT_DESCRIPTOR_TYPE_SECTION) \r
+ TT_DESCRIPTOR_TYPE_SECTION)\r
#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \\r
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH | \\r
/** @file\r
*\r
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
VOID\r
);\r
\r
-UINTN \r
+UINTN\r
EFIAPI\r
ArmReadCbar (\r
VOID\r
/** @file\r
*\r
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
/** @file\r
*\r
* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#define __ARM_DISASSEBLER_LIB_H__\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
- point to next instructin. \r
- \r
- We cheat and only decode instructions that access \r
+ Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instructin.\r
+\r
+ We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
- \r
- @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble. \r
+\r
+ @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.\r
@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream\r
@param Extended TRUE dump hex for instruction too.\r
@param ItBlock Size of IT Block\r
@param Buf Buffer to sprintf disassembly into.\r
- @param Size Size of Buf in bytes. \r
- \r
+ @param Size Size of Buf in bytes.\r
+\r
**/\r
VOID\r
DisassembleInstruction (\r
OUT CHAR8 *Buf,\r
OUT UINTN Size\r
);\r
- \r
-#endif \r
+\r
+#endif\r
ArmDataCachePresent (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmDataCacheSize (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmDataCacheAssociativity (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
VOID\r
);\r
- \r
+\r
BOOLEAN\r
EFIAPI\r
ArmInstructionCachePresent (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmInstructionCacheSize (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmInstructionCacheAssociativity (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
ArmDisableInstructionCache (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
ArmDisableFiq (\r
VOID\r
);\r
- \r
+\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
ArmInvalidateTlb (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
IN VOID *TranslationTableEntry,\r
IN VOID *Mva\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
OUT VOID **TranslationTableBase OPTIONAL,\r
OUT UINTN *TranslationTableSize OPTIONAL\r
);\r
- \r
+\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
ArmDataMemoryBarrier (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmDataSyncronizationBarrier (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
IN EFI_EXCEPTION_TYPE ExceptionType,\r
IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
);\r
- \r
-#endif \r
+\r
+#endif\r
* about the semihosting interface.\r
*\r
*/\r
- \r
+\r
#define SEMIHOST_FILE_MODE_READ (0 << 2)\r
#define SEMIHOST_FILE_MODE_WRITE (1 << 2)\r
#define SEMIHOST_FILE_MODE_APPEND (2 << 2)\r
SemihostWriteString (\r
IN CHAR8 *String\r
);\r
- \r
+\r
UINT32\r
SemihostSystem (\r
IN CHAR8 *CommandLine\r
);\r
- \r
+\r
#endif // __SEMIHOSTING_H__\r
If Buffer was not allocated with a page allocation function in the Memory Allocation Library,\r
then ASSERT().\r
If Pages is zero, then ASSERT().\r
- \r
+\r
@param Buffer Pointer to the buffer of pages to free.\r
@param Pages The number of 4 KB pages to free.\r
\r
If Buffer was not allocated with an aligned page allocation function in the Memory Allocation\r
Library, then ASSERT().\r
If Pages is zero, then ASSERT().\r
- \r
+\r
@param Buffer Pointer to the buffer of pages to free.\r
@param Pages The number of 4 KB pages to free.\r
\r
allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there\r
is not enough memory remaining to satisfy the request, then NULL is returned.\r
If Buffer is NULL, then ASSERT().\r
- If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). \r
+ If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().\r
\r
@param AllocationSize The number of bytes to allocate and zero.\r
@param Buffer The buffer to copy to the allocated buffer.\r
allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there\r
is not enough memory remaining to satisfy the request, then NULL is returned.\r
If Buffer is NULL, then ASSERT().\r
- If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). \r
+ If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().\r
\r
@param AllocationSize The number of bytes to allocate and zero.\r
@param Buffer The buffer to copy to the allocated buffer.\r
allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there\r
is not enough memory remaining to satisfy the request, then NULL is returned.\r
If Buffer is NULL, then ASSERT().\r
- If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). \r
+ If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().\r
\r
@param AllocationSize The number of bytes to allocate and zero.\r
@param Buffer The buffer to copy to the allocated buffer.\r
);\r
\r
/**\r
- Frees a buffer that was previously allocated with one of the aligned pool allocation functions \r
+ Frees a buffer that was previously allocated with one of the aligned pool allocation functions\r
in the Memory Allocation Library.\r
\r
Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the\r
IN EFI_PHYSICAL_ADDRESS VirtualMask,\r
OUT UINT64 *Attributes OPTIONAL\r
);\r
- \r
+\r
typedef\r
EFI_STATUS\r
(EFIAPI *FREE_CONVERTED_PAGES) (\r
\r
extern EFI_GUID gVirtualUncachedPagesProtocolGuid;\r
\r
-#endif \r
+#endif\r
#/** @file\r
-# \r
+#\r
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
-# \r
+#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-# \r
+#\r
#**/\r
\r
[Defines]\r
FILE_GUID = 82da1b44-d2d6-4a7d-bbf0-a0cb67964034\r
MODULE_TYPE = BASE\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = TimerLib \r
+ LIBRARY_CLASS = TimerLib\r
CONSTRUCTOR = TimerConstructor\r
\r
[Sources.common]\r
MdePkg/MdePkg.dec\r
EmbeddedPkg/EmbeddedPkg.dec\r
ArmPkg/ArmPkg.dec\r
- \r
+\r
\r
[LibraryClasses]\r
DebugLib\r
IoLib\r
ArmLib\r
- BaseLib \r
- \r
+ BaseLib\r
+\r
[Protocols]\r
- \r
+\r
[Guids]\r
- \r
+\r
[Pcd]\r
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz\r
\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
- \r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINTN ArmCacheLineLength = ArmDataCacheLineLength();\r
UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;\r
UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);\r
- \r
+\r
if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {\r
ArmDrainWriteBuffer ();\r
CacheOperation ();\r
Default exception handler\r
\r
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
- \r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINTN Index, Start, End;\r
CHAR8 *Str;\r
BOOLEAN First;\r
- \r
+\r
Str = mMregListStr;\r
*Str = '\0';\r
AsciiStrCat (Str, "{");\r
for (Index++; ((OpCode & (1 << Index)) != 0) && Index <= 15; Index++) {\r
End = Index;\r
}\r
- \r
+\r
if (!First) {\r
AsciiStrCat (Str, ",");\r
} else {\r
First = FALSE;\r
}\r
- \r
+\r
if (Start == End) {\r
AsciiStrCat (Str, gReg[Start]);\r
AsciiStrCat (Str, ", ");\r
AsciiStrCat (Str, "ERROR");\r
}\r
AsciiStrCat (Str, "}");\r
- \r
+\r
// BugBug: Make caller pass in buffer it is cleaner\r
return mMregListStr;\r
}\r
\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
- point to next instructin. \r
- \r
- We cheat and only decode instructions that access \r
+ Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instructin.\r
+\r
+ We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
- \r
- @param OpCodePtr Pointer to pointer of ARM instruction to disassemble. \r
+\r
+ @param OpCodePtr Pointer to pointer of ARM instruction to disassemble.\r
@param Buf Buffer to sprintf disassembly into.\r
- @param Size Size of Buf in bytes. \r
+ @param Size Size of Buf in bytes.\r
@param Extended TRUE dump hex for instruction too.\r
- \r
+\r
**/\r
VOID\r
DisassembleArmInstruction (\r
P = (OpCode & BIT24) == BIT24;\r
U = (OpCode & BIT23) == BIT23;\r
B = (OpCode & BIT22) == BIT22; // Also called S\r
- W = (OpCode & BIT21) == BIT21; \r
+ W = (OpCode & BIT21) == BIT21;\r
L = (OpCode & BIT20) == BIT20;\r
S = (OpCode & BIT6) == BIT6;\r
H = (OpCode & BIT5) == BIT5;\r
// LDREX, STREX\r
if ((OpCode & 0x0fe000f0) == 0x01800090) {\r
if (L) {\r
- // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>] \r
- AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]); \r
+ // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]\r
+ AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);\r
} else {\r
// A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]\r
- AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]); \r
- } \r
+ AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);\r
+ }\r
return;\r
}\r
- \r
+\r
// LDM/STM\r
if ((OpCode & 0x0e000000) == 0x08000000) {\r
if (L) {\r
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^\r
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^\r
- AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); \r
+ AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));\r
} else {\r
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^\r
- AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); \r
- } \r
+ AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));\r
+ }\r
return;\r
}\r
\r
if ((OpCode & 0xfd70f000 ) == 0xf550f000) {\r
Index = AsciiSPrint (Buf, Size, "PLD");\r
} else {\r
- Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]); \r
+ Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);\r
}\r
if (P) {\r
if (!I) {\r
} else {\r
Type = "ROR";\r
}\r
- \r
+\r
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));\r
}\r
} else { // !P\r
} else {\r
Type = "ROR";\r
}\r
- \r
+\r
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);\r
}\r
}\r
- return; \r
+ return;\r
}\r
- \r
+\r
if ((OpCode & 0x0e000000) == 0x00000000) {\r
// LDR/STR address mode 3\r
// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>\r
Root = "STR%aD %a ";\r
}\r
}\r
- \r
- Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]); \r
+\r
+ Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);\r
\r
S = (OpCode & BIT6) == BIT6;\r
H = (OpCode & BIT5) == BIT5;\r
AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);\r
return;\r
}\r
- \r
+\r
if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {\r
// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}\r
AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));\r
AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));\r
return;\r
}\r
- \r
+\r
if ((OpCode & 0xfff000f0) == 0xe1200070) {\r
// A4.1.7 BKPT <immed_16>\r
AsciiSPrint (Buf, Size, "BKPT %x", ((OpCode >> 8) | (OpCode & 0xf)) & 0xffff);\r
return;\r
- } \r
- \r
+ }\r
+\r
if ((OpCode & 0xfff10020) == 0xf1000000) {\r
// A4.1.16 CPS<effect> <iflags> {, #<mode>}\r
if (((OpCode >> 6) & 0x7) == 0) {\r
}\r
}\r
return;\r
- } \r
- \r
+ }\r
+\r
if ((OpCode & 0x0f000000) == 0x0f000000) {\r
// A4.1.107 SWI{<cond>} <immed_24>\r
AsciiSPrint (Buf, Size, "SWI%a %x", COND (OpCode), OpCode & 0x00ffffff);\r
return;\r
- } \r
+ }\r
\r
if ((OpCode & 0x0fb00000) == 0x01000000) {\r
// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR\r
AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");\r
return;\r
- } \r
+ }\r
\r
\r
if ((OpCode & 0x0db00000) == 0x03200000) {\r
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);\r
}\r
return;\r
- } \r
+ }\r
\r
if ((OpCode & 0xff000010) == 0xfe000000) {\r
// A4.1.13 CDP{<cond>} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>\r
AsciiSPrint (Buf, Size, "CDP%a 0x%x, 0x%x, CR%d, CR%d, CR%d, 0x%x", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, Rn, Rd, Rm, (OpCode >> 5) &0x7);\r
return;\r
}\r
- \r
+\r
if ((OpCode & 0x0e000000) == 0x0c000000) {\r
// A4.1.19 LDC and A4.1.96 SDC\r
if ((OpCode & 0xf0000000) == 0xf0000000) {\r
} else {\r
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);\r
}\r
- \r
+\r
if (!P) {\r
- if (!W) { \r
+ if (!W) {\r
// A5.5.5.5 [<Rn>], <option>\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff); \r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);\r
} else {\r
// A.5.5.4 [<Rn>], #+/-<offset_8>*4\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff); \r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);\r
}\r
} else {\r
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W)); \r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));\r
}\r
- \r
+\r
}\r
- \r
+\r
if ((OpCode & 0x0f000010) == 0x0e000010) {\r
- // A4.1.32 MRC2, MCR2 \r
+ // A4.1.32 MRC2, MCR2\r
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);\r
- return; \r
+ return;\r
}\r
\r
if ((OpCode & 0x0ff00000) == 0x0c400000) {\r
- // A4.1.33 MRRC2, MCRR2 \r
+ // A4.1.33 MRRC2, MCRR2\r
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);\r
- return; \r
+ return;\r
}\r
\r
AsciiSPrint (Buf, Size, "Faulting OpCode 0x%08x", OpCode);\r
- \r
+\r
*OpCodePtr += 1;\r
return;\r
}\r
/** @file\r
Thumb Dissassembler. Still a work in progress.\r
\r
- Wrong output is a bug, so please fix it. \r
+ Wrong output is a bug, so please fix it.\r
Hex output means there is not yet an entry or a decode bug.\r
- gOpThumb[] are Thumb 16-bit, and gOpThumb2[] work on the 32-bit \r
- 16-bit stream of Thumb2 instruction. Then there are big case \r
+ gOpThumb[] are Thumb 16-bit, and gOpThumb2[] work on the 32-bit\r
+ 16-bit stream of Thumb2 instruction. Then there are big case\r
statements to print everything out. If you are adding instructions\r
try to reuse existing case entries if possible.\r
\r
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
- \r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Thumb address modes\r
#define LOAD_STORE_FORMAT1 1\r
#define LOAD_STORE_FORMAT1_H 101\r
-#define LOAD_STORE_FORMAT1_B 111 \r
+#define LOAD_STORE_FORMAT1_B 111\r
#define LOAD_STORE_FORMAT2 2\r
#define LOAD_STORE_FORMAT3 3\r
#define LOAD_STORE_FORMAT4 4\r
-#define LOAD_STORE_MULTIPLE_FORMAT1 5 \r
-#define PUSH_FORMAT 6 \r
-#define POP_FORMAT 106 \r
+#define LOAD_STORE_MULTIPLE_FORMAT1 5\r
+#define PUSH_FORMAT 6\r
+#define POP_FORMAT 106\r
#define IMMED_8 7\r
#define CONDITIONAL_BRANCH 8\r
#define UNCONDITIONAL_BRANCH 9\r
#define THUMB2_4REGS 230\r
#define ADD_IMM12_1REG 231\r
#define THUMB2_IMM16 232\r
-#define MRC_THUMB2 233 \r
-#define MRRC_THUMB2 234 \r
+#define MRC_THUMB2 233\r
+#define MRRC_THUMB2 234\r
#define THUMB2_MRS 235\r
#define THUMB2_MSR 236\r
\r
{ "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },\r
{ "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9\r
{ "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },\r
- { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP }, \r
+ { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },\r
{ "ADD" , 0xb000, 0xff80, DATA_FORMAT7 },\r
\r
{ "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },\r
{ "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },\r
{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
{ "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },\r
- \r
+\r
{ "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL\r
{ "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },\r
{ "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },\r
\r
THUMB_INSTRUCTIONS gOpThumb2[] = {\r
//Instruct OpCode OpCode Mask Addressig Mode\r
- \r
- { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW \r
+\r
+ { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW\r
{ "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD\r
{ "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}\r
{ "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>\r
{ "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>\r
{ "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>\r
{ "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>\r
- \r
+\r
{ "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>\r
{ "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
{ "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>\r
{ "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
\r
{ "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2\r
- { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm> \r
+ { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>\r
{ "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2\r
- { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm> \r
+ { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>\r
{ "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2\r
- { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm> \r
+ { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>\r
\r
{ "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>\r
{ "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>\r
{ "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>\r
{ "LDM" , 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>\r
{ "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>\r
- \r
+\r
{ "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}\r
{ "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}\r
{ "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}\r
{ "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}\r
{ "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}\r
\r
- { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label> \r
- { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label> \r
- { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label> \r
- { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label> \r
- { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label> \r
- \r
+ { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>\r
+ { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>\r
+ { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>\r
+ { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>\r
+ { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>\r
+\r
{ "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}\r
{ "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}\r
{ "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}\r
- { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form? \r
- { "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form? \r
- { "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]} \r
- { "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]} \r
- { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]} \r
+ { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?\r
+ { "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?\r
+ { "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}\r
\r
{ "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
{ "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>\r
- \r
- { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]] \r
- { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>] \r
- { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>] \r
- \r
- { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>] \r
-\r
- { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]} \r
+\r
+ { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]\r
+ { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]\r
+ { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]\r
+\r
+ { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]\r
+\r
+ { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}\r
{ "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}\r
{ "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}\r
- \r
+\r
{ "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}\r
{ "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}\r
{ "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}\r
- { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]} \r
+ { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}\r
\r
{ "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
\r
- { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]] \r
- { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>] \r
- { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>] \r
- \r
- { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>] \r
+ { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]\r
+ { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]\r
+ { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]\r
+\r
+ { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]\r
\r
{ "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>\r
{ "SRS" , 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>\r
UINTN Index, Start, End;\r
CHAR8 *Str;\r
BOOLEAN First;\r
- \r
+\r
Str = mThumbMregListStr;\r
*Str = '\0';\r
AsciiStrCat (Str, "{");\r
- \r
+\r
for (Index = 0, First = TRUE; Index <= 15; Index++) {\r
if ((RegBitMask & (1 << Index)) != 0) {\r
Start = End = Index;\r
for (Index++; ((RegBitMask & (1 << Index)) != 0) && (Index <= 9); Index++) {\r
End = Index;\r
}\r
- \r
+\r
if (!First) {\r
AsciiStrCat (Str, ",");\r
} else {\r
First = FALSE;\r
}\r
- \r
+\r
if (Start == End) {\r
AsciiStrCat (Str, gReg[Start]);\r
} else {\r
AsciiStrCat (Str, "ERROR");\r
}\r
AsciiStrCat (Str, "}");\r
- \r
+\r
// BugBug: Make caller pass in buffer it is cleaner\r
return mThumbMregListStr;\r
}\r
if (((Data & TopBit) == 0) || (TopBit == BIT31)) {\r
return Data;\r
}\r
- \r
+\r
do {\r
TopBit <<= 1;\r
- Data |= TopBit; \r
+ Data |= TopBit;\r
} while ((TopBit & BIT31) != BIT31);\r
\r
return Data;\r
}\r
\r
//\r
-// Some instructions specify the PC is always considered aligned \r
+// Some instructions specify the PC is always considered aligned\r
// The PC is after the instruction that is excuting. So you pass\r
// in the instruction address and you get back the aligned answer\r
//\r
}\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
- point to next instructin. \r
- \r
- We cheat and only decode instructions that access \r
+ Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instructin.\r
+\r
+ We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
- \r
- @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble. \r
+\r
+ @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.\r
@param Buf Buffer to sprintf disassembly into.\r
- @param Size Size of Buf in bytes. \r
+ @param Size Size of Buf in bytes.\r
@param Extended TRUE dump hex for instruction too.\r
- \r
+\r
**/\r
VOID\r
DisassembleThumbInstruction (\r
UINT32 PC, Target, msbit, lsbit;\r
CHAR8 *Cond;\r
BOOLEAN S, J1, J2, P, U, W;\r
- UINT32 coproc, opc1, opc2, CRd, CRn, CRm; \r
+ UINT32 coproc, opc1, opc2, CRd, CRn, CRm;\r
UINT32 Mask;\r
\r
OpCodePtr = *OpCodePtrPtr;\r
OpCode = **OpCodePtrPtr;\r
- \r
+\r
// Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.\r
OpCode32 = (((UINT32)OpCode) << 16) | *(OpCodePtr + 1);\r
\r
\r
// Increment by the minimum instruction size, Thumb2 could be bigger\r
*OpCodePtrPtr += 1;\r
- \r
+\r
// Manage IT Block ItFlag TRUE means we are in an IT block\r
/*if (*ItBlock != 0) {\r
ItFlag = TRUE;\r
for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {\r
if (Extended) {\r
- Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode, gOpThumb[Index].Start); \r
+ Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode, gOpThumb[Index].Start);\r
} else {\r
- Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start); \r
+ Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);\r
}\r
switch (gOpThumb[Index].AddressMode) {\r
case LOAD_STORE_FORMAT1:\r
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);\r
return;\r
case LOAD_STORE_FORMAT1_H:\r
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);\r
return;\r
case LOAD_STORE_FORMAT1_B:\r
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);\r
return;\r
\r
case LOAD_STORE_FORMAT2:\r
// A6.5.1 <Rd>, [<Rn>, <Rm>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);\r
return;\r
case LOAD_STORE_FORMAT3:\r
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);\r
return;\r
case LOAD_STORE_FORMAT4:\r
// Rt, [SP, #imm8]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);\r
return;\r
- \r
+\r
case LOAD_STORE_MULTIPLE_FORMAT1:\r
// <Rn>!, {r0-r7}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff)); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));\r
return;\r
- \r
+\r
case POP_FORMAT:\r
// POP {r0-r7,pc}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0))); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));\r
return;\r
\r
case PUSH_FORMAT:\r
// PUSH {r0-r7,lr}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0))); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));\r
return;\r
\r
- \r
+\r
case IMMED_8:\r
// A6.7 <immed_8>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);\r
return;\r
\r
case CONDITIONAL_BRANCH:\r
Cond = gCondition[(OpCode >> 8) & 0xf];\r
Buf[Offset-5] = *Cond++;\r
Buf[Offset-4] = *Cond;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8)); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));\r
return;\r
case UNCONDITIONAL_BRANCH_SHORT:\r
// A6.3.2 B <target_address>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11)); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));\r
return;\r
- \r
+\r
case BRANCH_EXCHANGE:\r
// A6.3.3 BX|BLX <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);\r
return;\r
\r
case DATA_FORMAT1:\r
// A6.4.3 <Rd>, <Rn>, <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);\r
return;\r
case DATA_FORMAT2:\r
// A6.4.3 <Rd>, <Rn>, #3_bit_immed\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);\r
return;\r
case DATA_FORMAT3:\r
// A6.4.3 <Rd>|<Rn>, #imm8\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);\r
return;\r
case DATA_FORMAT4:\r
// A6.4.3 <Rd>|<Rm>, #immed_5\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);\r
return;\r
case DATA_FORMAT5:\r
// A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);\r
return;\r
case DATA_FORMAT6_SP:\r
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);\r
return;\r
case DATA_FORMAT6_PC:\r
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);\r
return;\r
case DATA_FORMAT7:\r
// A6.4.3 SP, SP, #<7_Bit_immed>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);\r
return;\r
case DATA_FORMAT8:\r
// A6.4.3 <Rd>|<Rn>, <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);\r
return;\r
- \r
+\r
case CPS_FORMAT:\r
// A7.1.24\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f"); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");\r
return;\r
\r
case ENDIAN_FORMAT:\r
// A7.1.24\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE"); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");\r
return;\r
\r
case DATA_CBZ:\r
// CB{N}Z <Rn>, <Lable>\r
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);\r
return;\r
\r
case ADR_FORMAT:\r
// ADR <Rd>, <Label>\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);\r
return;\r
\r
case IT_BLOCK:\r
// ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]\r
// ITSTATE[7:5] == cond[3:1]\r
- // ITSTATE[4] == 1st Instruction cond[0] \r
- // ITSTATE[3] == 2st Instruction cond[0] \r
- // ITSTATE[2] == 3st Instruction cond[0] \r
+ // ITSTATE[4] == 1st Instruction cond[0]\r
+ // ITSTATE[3] == 2st Instruction cond[0]\r
+ // ITSTATE[2] == 3st Instruction cond[0]\r
// ITSTATE[1] == 4st Instruction cond[0]\r
// ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions\r
// 1st one in ITSTATE low bits defines the number of instructions\r
} else if ((OpCode & 0xf) == 0x8) {\r
*ItBlock = 1;\r
}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);\r
return;\r
}\r
}\r
}\r
\r
- \r
+\r
// Thumb2 are 32-bit instructions\r
*OpCodePtrPtr += 1;\r
Rt = (OpCode32 >> 12) & 0xf;\r
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {\r
if (Extended) {\r
- Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode32, gOpThumb2[Index].Start); \r
+ Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode32, gOpThumb2[Index].Start);\r
} else {\r
- Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start); \r
+ Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start);\r
}\r
switch (gOpThumb2[Index].AddressMode) {\r
case B_T3:\r
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1\r
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S\r
Target = SignExtend32 (Target, BIT20);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);\r
return;\r
case B_T4:\r
// S:I1:I2:imm10:imm11:0\r
Target |= (!(J1 ^ S) ? BIT23 : 0); // I1\r
Target |= (S ? BIT24 : 0); // S\r
Target = SignExtend32 (Target, BIT24);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);\r
return;\r
\r
case BL_T2:\r
Target |= (!(J1 ^ S) ? BIT24 : 0); // I1\r
Target |= (S ? BIT25 : 0); // S\r
Target = SignExtend32 (Target, BIT25);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);\r
return;\r
\r
case POP_T2:\r
return;\r
\r
case POP_T3:\r
- // <register> \r
+ // <register>\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);\r
return;\r
\r
\r
case LDM_REG_IMM12_SIGNED:\r
// <rt>, <label>\r
- Target = OpCode32 & 0xfff; \r
+ Target = OpCode32 & 0xfff;\r
if ((OpCode32 & BIT23) == 0) {\r
// U == 0 means subtrack, U == 1 means add\r
Target = -Target;\r
AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);\r
}\r
return;\r
- \r
+\r
case LDM_REG_IMM12:\r
// <rt>, [<rn>, {, #<imm12>]}\r
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
case LDRD_REG_IMM8_SIGNED:\r
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
P = (OpCode32 & BIT24) == BIT24; // index = P\r
- U = (OpCode32 & BIT23) == BIT23; \r
+ U = (OpCode32 & BIT23) == BIT23;\r
W = (OpCode32 & BIT21) == BIT21;\r
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
if (P) {\r
}\r
return;\r
\r
- case LDRD_REG_IMM8: \r
- // LDRD <rt>, <rt2>, <label> \r
- Target = (OpCode32 & 0xff) << 2; \r
+ case LDRD_REG_IMM8:\r
+ // LDRD <rt>, <rt2>, <label>\r
+ Target = (OpCode32 & 0xff) << 2;\r
if ((OpCode32 & BIT23) == 0) {\r
// U == 0 means subtrack, U == 1 means add\r
Target = -Target;\r
// LDREXD <Rt>, <Rt2>, [<Rn>]\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
return;\r
- \r
+\r
case SRS_FORMAT:\r
// SP{!}, #<mode>\r
W = (OpCode32 & BIT21) == BIT21;\r
W = (OpCode32 & BIT21) == BIT21;\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");\r
return;\r
- \r
+\r
projects / mirror_edk2.git / commitdiff