+++ /dev/null
-/** @file\r
- This file declares EFI IDE Controller Init Protocol\r
- The EFI_IDE_CONTROLLER_INIT_PROTOCOL provides the chipset-specific information to\r
- the IDE bus driver. This protocol is mandatory for IDE controllers if the IDE devices behind the\r
- controller are to be enumerated by an IDE bus driver.\r
- There can only be one instance of EFI_IDE_CONTROLLER_INIT_PROTOCOL for each IDE\r
- controller in a system. It is installed on the handle that corresponds to the IDE controller. An IDE\r
- bus driver that wishes to manage an IDE bus and possibly IDE devices in a system will have to\r
- retrieve the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance that is associated with the\r
- controller to be managed.\r
-\r
- Copyright (c) 2007 - 2009, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- @par Revision Reference:\r
- This Protocol is defined in IDE Controller Initialization Protocol Specification\r
- Version 0.9.\r
-\r
-**/\r
-\r
-#ifndef _EFI_IDE_CONTROLLER_INIT_PROTOCOL_H_\r
-#define _EFI_IDE_CONTROLLER_INIT_PROTOCOL_H_\r
-\r
-\r
-///\r
-/// Global ID for the EFI Platform IDE Protocol GUID\r
-///\r
-#define EFI_IDE_CONTROLLER_INIT_PROTOCOL_GUID \\r
- { 0xa1e37052, 0x80d9, 0x4e65, {0xa3, 0x17, 0x3e, 0x9a, 0x55, 0xc4, 0x3e, 0xc9 } }\r
-\r
-///\r
-/// Forward reference for pure ANSI compatability\r
-///\r
-typedef struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL EFI_IDE_CONTROLLER_INIT_PROTOCOL;\r
-\r
-//\r
-//////////////////////////////////////////////////////////////////////////////////////////\r
-// EFI_IDE_BUS_ENUMERATION_PHASE\r
-// EFI_IDE_CONTROLLER_ENUM_PHASE\r
-//\r
-typedef enum{\r
- EfiIdeBeforeChannelEnumeration,\r
- EfiIdeAfterChannelEnumeration,\r
- EfiIdeBeforeChannelReset,\r
- EfiIdeAfterChannelReset,\r
- EfiIdeBusBeforeDevicePresenceDetection,\r
- EfiIdeBusAfterDevicePresenceDetection,\r
- EfiIdeResetMode,\r
- EfiIdeBusPhaseMaximum\r
-} EFI_IDE_CONTROLLER_ENUM_PHASE;\r
-\r
-//\r
-//******************************************************\r
-// EFI_ATA_EXT_TRANSFER_PROTOCOL\r
-//******************************************************\r
-//\r
-// This extended mode describes the SATA physical protocol.\r
-// SATA physical layers can operate at different speeds.\r
-// These speeds are defined below. Various PATA protocols\r
-// and associated modes are not applicable to SATA devices.\r
-//\r
-\r
-typedef enum {\r
- EfiAtaSataTransferProtocol\r
-} EFI_ATA_EXT_TRANSFER_PROTOCOL;\r
-\r
-#define EFI_SATA_AUTO_SPEED 0\r
-#define EFI_SATA_GEN1_SPEED 1\r
-#define EFI_SATA_GEN2_SPEED 2\r
-\r
-//\r
-//*******************************************************\r
-// EFI_IDE_CABLE_TYPE\r
-//*******************************************************\r
-//\r
-typedef enum {\r
- EfiIdeCableTypeUnknown,\r
- EfiIdeCableType40pin,\r
- EfiIdeCableType80Pin,\r
- EfiIdeCableTypeSerial,\r
- EfiIdeCableTypeMaximum\r
-} EFI_IDE_CABLE_TYPE;\r
-\r
-//\r
-//******************************************************\r
-// EFI_ATA_MODE\r
-//******************************************************\r
-//\r
-typedef struct {\r
- BOOLEAN Valid;\r
- UINT32 Mode;\r
-} EFI_ATA_MODE;\r
-\r
-//\r
-//******************************************************\r
-// EFI_ATA_EXTENDED_MODE\r
-//******************************************************\r
-//\r
-typedef struct {\r
- EFI_ATA_EXT_TRANSFER_PROTOCOL TransferProtocol;\r
- UINT32 Mode;\r
-} EFI_ATA_EXTENDED_MODE;\r
-\r
-//\r
-//******************************************************\r
-// EFI_ATA_COLLECTIVE_MODE\r
-//******************************************************\r
-//\r
-typedef struct {\r
- EFI_ATA_MODE PioMode;\r
- EFI_ATA_MODE SingleWordDmaMode;\r
- EFI_ATA_MODE MultiWordDmaMode;\r
- EFI_ATA_MODE UdmaMode;\r
- UINT32 ExtModeCount;\r
- EFI_ATA_EXTENDED_MODE ExtMode[1];\r
-} EFI_ATA_COLLECTIVE_MODE;\r
-\r
-//\r
-//*******************************************************\r
-// EFI_ATA_IDENTIFY_DATA\r
-//*******************************************************\r
-//\r
-\r
-#pragma pack(1)\r
-\r
-typedef struct {\r
- UINT16 config; ///< General Configuration\r
- UINT16 cylinders; ///< Number of Cylinders\r
- UINT16 reserved_2;\r
- UINT16 heads; ///< Number of logical heads\r
- UINT16 vendor_data1;\r
- UINT16 vendor_data2;\r
- UINT16 sectors_per_track;\r
- UINT16 vendor_specific_7_9[3];\r
- CHAR8 SerialNo[20]; ///< ASCII\r
- UINT16 vendor_specific_20_21[2];\r
- UINT16 ecc_bytes_available;\r
- CHAR8 FirmwareVer[8]; ///< ASCII\r
- CHAR8 ModelName[40]; ///< ASCII\r
- UINT16 multi_sector_cmd_max_sct_cnt;\r
- UINT16 reserved_48;\r
- UINT16 capabilities;\r
- UINT16 reserved_50;\r
- UINT16 pio_cycle_timing;\r
- UINT16 reserved_52;\r
- UINT16 field_validity;\r
- UINT16 current_cylinders;\r
- UINT16 current_heads;\r
- UINT16 current_sectors;\r
- UINT16 CurrentCapacityLsb;\r
- UINT16 CurrentCapacityMsb;\r
- UINT16 reserved_59;\r
- UINT16 user_addressable_sectors_lo;\r
- UINT16 user_addressable_sectors_hi;\r
- UINT16 reserved_62;\r
- UINT16 multi_word_dma_mode;\r
- UINT16 advanced_pio_modes;\r
- UINT16 min_multi_word_dma_cycle_time;\r
- UINT16 rec_multi_word_dma_cycle_time;\r
- UINT16 min_pio_cycle_time_without_flow_control;\r
- UINT16 min_pio_cycle_time_with_flow_control;\r
- UINT16 reserved_69_79[11];\r
- UINT16 major_version_no;\r
- UINT16 minor_version_no;\r
- UINT16 command_set_supported_82; ///< word 82\r
- UINT16 command_set_supported_83; ///< word 83\r
- UINT16 command_set_feature_extn; ///< word 84\r
- UINT16 command_set_feature_enb_85; ///< word 85\r
- UINT16 command_set_feature_enb_86; ///< word 86\r
- UINT16 command_set_feature_default; ///< word 87\r
- UINT16 ultra_dma_mode; ///< word 88\r
- UINT16 reserved_89_105[17];\r
- UINT16 phy_logic_sector_support; ///< word 106\r
- UINT16 reserved_107_116[10];\r
- UINT16 logic_sector_size_lo; ///< word 117\r
- UINT16 logic_sector_size_hi; ///< word 118\r
- UINT16 reserved_119_127[9];\r
- UINT16 security_status;\r
- UINT16 vendor_data_129_159[31];\r
- UINT16 reserved_160_208[49];\r
- UINT16 alignment_logic_in_phy_blocks; ///< word 209\r
- UINT16 reserved_210_255[46];\r
-} EFI_ATA_IDENTIFY_DATA;\r
-\r
-#pragma pack()\r
-//\r
-//*******************************************************\r
-// EFI_ATAPI_IDENTIFY_DATA\r
-//*******************************************************\r
-//\r
-#pragma pack(1)\r
-typedef struct {\r
- UINT16 config; ///< General Configuration\r
- UINT16 obsolete_1;\r
- UINT16 specific_config;\r
- UINT16 obsolete_3;\r
- UINT16 retired_4_5[2];\r
- UINT16 obsolete_6;\r
- UINT16 cfa_reserved_7_8[2];\r
- UINT16 retired_9;\r
- CHAR8 SerialNo[20]; ///< ASCII\r
- UINT16 retired_20_21[2];\r
- UINT16 obsolete_22;\r
- CHAR8 FirmwareVer[8]; ///< ASCII\r
- CHAR8 ModelName[40]; ///< ASCII\r
- UINT16 multi_sector_cmd_max_sct_cnt;\r
- UINT16 reserved_48;\r
- UINT16 capabilities_49;\r
- UINT16 capabilities_50;\r
- UINT16 obsolete_51_52[2];\r
- UINT16 field_validity;\r
- UINT16 obsolete_54_58[5];\r
- UINT16 mutil_sector_setting;\r
- UINT16 user_addressable_sectors_lo;\r
- UINT16 user_addressable_sectors_hi;\r
- UINT16 obsolete_62;\r
- UINT16 multi_word_dma_mode;\r
- UINT16 advanced_pio_modes;\r
- UINT16 min_multi_word_dma_cycle_time;\r
- UINT16 rec_multi_word_dma_cycle_time;\r
- UINT16 min_pio_cycle_time_without_flow_control;\r
- UINT16 min_pio_cycle_time_with_flow_control;\r
- UINT16 reserved_69_74[6];\r
- UINT16 queue_depth;\r
- UINT16 reserved_76_79[4];\r
- UINT16 major_version_no;\r
- UINT16 minor_version_no;\r
- UINT16 cmd_set_support_82;\r
- UINT16 cmd_set_support_83;\r
- UINT16 cmd_feature_support;\r
- UINT16 cmd_feature_enable_85;\r
- UINT16 cmd_feature_enable_86;\r
- UINT16 cmd_feature_default;\r
- UINT16 ultra_dma_select;\r
- UINT16 time_required_for_sec_erase;\r
- UINT16 time_required_for_enhanced_sec_erase;\r
- UINT16 current_advanced_power_mgmt_value;\r
- UINT16 master_pwd_revison_code;\r
- UINT16 hardware_reset_result;\r
- UINT16 current_auto_acoustic_mgmt_value;\r
- UINT16 reserved_95_99[5];\r
- UINT16 max_user_lba_for_48bit_addr[4];\r
- UINT16 reserved_104_126[23];\r
- UINT16 removable_media_status_notification_support;\r
- UINT16 security_status;\r
- UINT16 vendor_data_129_159[31];\r
- UINT16 cfa_power_mode;\r
- UINT16 cfa_reserved_161_175[15];\r
- UINT16 current_media_serial_no[30];\r
- UINT16 reserved_206_254[49];\r
- UINT16 integrity_word;\r
-} EFI_ATAPI_IDENTIFY_DATA;\r
-\r
-#pragma pack()\r
-//\r
-//*******************************************************\r
-// EFI_IDENTIFY_DATA\r
-//*******************************************************\r
-//\r
-typedef union {\r
- EFI_ATA_IDENTIFY_DATA AtaData;\r
- EFI_ATAPI_IDENTIFY_DATA AtapiData;\r
-} EFI_IDENTIFY_DATA;\r
-\r
-#define EFI_ATAPI_DEVICE_IDENTIFY_DATA 0x8000\r
-\r
-//\r
-/////////////////////////////////////////////////////////////////////////////////////////\r
-// Function prototype declaration, for ANSI compatability\r
-//\r
-/**\r
- Returns the information about the specified IDE channel.\r
-\r
- @param This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
- @param Channel Zero-based channel number.\r
- @param Enabled TRUE if this channel is enabled. Disabled channels are not scanned\r
- to see if any devices are present.\r
- @param MaxDevices The maximum number of IDE devices that the bus driver\r
- can expect on this channel.\r
-\r
- @retval EFI_SUCCESS Information was returned without any errors.\r
- @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_IDE_CONTROLLER_GET_CHANNEL_INFO)(\r
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
- IN UINT8 Channel,\r
- OUT BOOLEAN *Enabled,\r
- OUT UINT8 *MaxDevices\r
-);\r
-\r
-/**\r
- The notifications from the IDE bus driver that it is about to enter a certain\r
- phase of the IDE channel enumeration process.\r
-\r
- @param This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
- @param Phase The phase during enumeration.\r
- @param Channel Zero-based channel number.\r
-\r
- @retval EFI_SUCCESS The notification was accepted without any errors.\r
- @retval EFI_NOT_SUPPORTED Phase is not supported.\r
- @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
- @retval EFI_NOT_READY This phase cannot be entered at this time.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_IDE_CONTROLLER_NOTIFY_PHASE)(\r
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
- IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,\r
- IN UINT8 Channel\r
-);\r
-\r
-/**\r
- Submits the device information to the IDE controller driver.\r
-\r
- @param This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
- @param Channel Zero-based channel number.\r
- @param Device Zero-based device number on the Channel.\r
- @param IdentifyData The device's response to the ATA IDENTIFY_DEVICE command.\r
-\r
- @retval EFI_SUCCESS The information was accepted without any errors.\r
- @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
- Or Device is invalid.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_IDE_CONTROLLER_SUBMIT_DATA)(\r
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
- IN UINT8 Channel,\r
- IN UINT8 Device,\r
- IN EFI_IDENTIFY_DATA *IdentifyData\r
-);\r
-\r
-/**\r
- Disqualifies specific modes for an IDE device.\r
-\r
- @param This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
- @param Channel Zero-based channel number.\r
- @param Device Zero-based device number on the Channel.\r
- @param BadModes The modes that the device does not support and that\r
- should be disqualified.\r
-\r
- @retval EFI_SUCCESS The modes were accepted without any errors.\r
- @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
- Or Device is invalid.\r
- \r
- @note: Inconsistent with specification here: \r
- Framework Spec IdeCont defined another case to return EFI_INVALID_PARAMETER when\r
- IdentifyData is NULL. However in the function there is no parameter named IdentifyData.\r
- So that should be a typo error in spec.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_IDE_CONTROLLER_DISQUALIFY_MODE)(\r
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
- IN UINT8 Channel,\r
- IN UINT8 Device,\r
- IN EFI_ATA_COLLECTIVE_MODE *BadModes\r
-);\r
-\r
-/**\r
- Returns the information about the optimum modes for the specified IDE device.\r
-\r
- @param This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
- @param Channel Zero-based channel number.\r
- @param Device Zero-based device number on the Channel.\r
- @param SupportedModes The optimum modes for the device.\r
-\r
- @retval EFI_SUCCESS SupportedModes was returned.\r
- @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
- Or Device is invalid. Or SupportedModes is NULL.\r
- @retval EFI_NOT_READY Modes cannot be calculated due to a lack of data.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_IDE_CONTROLLER_CALCULATE_MODE)(\r
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
- IN UINT8 Channel,\r
- IN UINT8 Device,\r
- OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes\r
-);\r
-\r
-/**\r
- Commands the IDE controller driver to program the IDE controller hardware\r
- so that the specified device can operate at the specified mode.\r
-\r
- @param This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
- @param Channel Zero-based channel number.\r
- @param Device Zero-based device number on the Channel.\r
- @param Modes The modes to set.\r
-\r
- @retval EFI_SUCCESS The command was accepted without any errors.\r
- @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
- Or Device is invalid.\r
- @retval EFI_NOT_READY Modes cannot be set at this time due to lack of data.\r
- @retval EFI_DEVICE_ERROR Modes cannot be set due to hardware failure.\r
- The IDE bus driver should not use this device.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_IDE_CONTROLLER_SET_TIMING)(\r
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
- IN UINT8 Channel,\r
- IN UINT8 Device,\r
- IN EFI_ATA_COLLECTIVE_MODE *Modes\r
-);\r
-\r
-//\r
-////////////////////////////////////////////////////////////////////////////////////////////////////\r
-// Interface structure\r
-// EFI_IDE_CONTROLLER_INIT_PROTOCOL protocol provides the chipset specific information to the IDE bus driver.\r
-// An IDE Bus driver wants to manage an IDE bus and possible IDE devices will have to retrieve the\r
-// EFI_IDE_CONTROLLER_INIT_PROTOCOL instances.\r
-//\r
-/**\r
- Provides the basic interfaces to abstract an IDE controller.\r
-**/\r
-struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL {\r
- ///\r
- /// Returns the information about a specific channel.\r
- ///\r
- EFI_IDE_CONTROLLER_GET_CHANNEL_INFO GetChannelInfo;\r
- \r
- ///\r
- /// The notification that the IDE bus driver is about to enter the\r
- /// specified phase during the enumeration process. \r
- ///\r
- EFI_IDE_CONTROLLER_NOTIFY_PHASE NotifyPhase;\r
- \r
- ///\r
- /// Submits the Drive Identify data that was returned by the device.\r
- ///\r
- EFI_IDE_CONTROLLER_SUBMIT_DATA SubmitData;\r
- \r
- ///\r
- /// Submits information about modes that should be disqualified.\r
- ///\r
- EFI_IDE_CONTROLLER_DISQUALIFY_MODE DisqualifyMode;\r
- \r
- ///\r
- /// Calculates and returns the optimum mode for a particular IDE device.\r
- ///\r
- EFI_IDE_CONTROLLER_CALCULATE_MODE CalculateMode;\r
- \r
- ///\r
- /// Programs the IDE controller hardware to the default timing or per the modes\r
- /// that were returned by the last call to CalculateMode(). \r
- ///\r
- EFI_IDE_CONTROLLER_SET_TIMING SetTiming;\r
- \r
- ///\r
- /// Set to TRUE if the enumeration group includes all the channels that are\r
- /// produced by this controller. FALSE if an enumeration group consists of\r
- /// only one channel. \r
- ///\r
- BOOLEAN EnumAll;\r
- \r
- ///\r
- /// The number of channels that are produced by this controller.\r
- ///\r
- UINT8 ChannelCount;\r
-};\r
-\r
-extern EFI_GUID gEfiIdeControllerInitProtocolGuid;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- This file declares EFI Incompatible PCI Device Support Protocol\r
- This protocol allows the PCI bus driver to support resource allocation for some PCI devices that do not comply\r
- with the PCI Specification.\r
- The EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL is used by the PCI bus driver\r
- to support resource allocation for some PCI devices that do not comply with the PCI Specification.\r
- This protocol can find some incompatible PCI devices and report their special resource\r
- requirements to the PCI bus driver. The generic PCI bus driver does not have prior knowledge of\r
- any incompatible PCI devices. It interfaces with the\r
- EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL to find out if a device is\r
- incompatible and to obtain the special configuration requirements for a specific incompatible PCI\r
- device.\r
- This protocol is optional, and only one instance of this protocol can be present in the system. If a\r
- platform supports this protocol, this protocol is produced by a Driver Execution Environment\r
- (DXE) driver and must be made available before the Boot Device Selection (BDS) phase. The PCI\r
- bus driver will look for the presence of this protocol before it begins PCI enumeration.\r
-\r
- Copyright (c) 2007 - 2009, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- @par Revision Reference:\r
- This protocol is defined in Framework of EFI PCI Platform Support Specification.\r
- Version 0.9.\r
-\r
-**/\r
-\r
-#ifndef _INCOMPATIBLE_PCI_DEVICE_SUPPORT_H_\r
-#define _INCOMPATIBLE_PCI_DEVICE_SUPPORT_H_\r
-\r
-\r
-#define EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL_GUID \\r
- {0xeb23f55a, 0x7863, 0x4ac2, {0x8d, 0x3d, 0x95, 0x65, 0x35, 0xde, 0x03, 0x75} }\r
-\r
-typedef struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL;\r
-\r
-/**\r
- Returns a list of ACPI resource descriptors that detail the special\r
- resource configuration requirements for an incompatible PCI device.\r
-\r
- @param This Pointer to the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL instance.\r
- @param VendorId A unique ID to identify the manufacturer of the PCI device.\r
- @param DeviceId A unique ID to identify the particular PCI device.\r
- @param RevisionId A PCI device-specific revision identifier.\r
- @param SubsystemVendorId Specifies the subsystem vendor ID.\r
- @param SubsystemDeviceId Specifies the subsystem device ID.\r
- @param Configuration A list of ACPI resource descriptors that detail\r
- the configuration requirement.\r
-\r
- @retval EFI_SUCCESS The function always returns EFI_SUCCESS.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE)(\r
- IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This,\r
- IN UINTN VendorId,\r
- IN UINTN DeviceId,\r
- IN UINTN RevisionId,\r
- IN UINTN SubsystemVendorId,\r
- IN UINTN SubsystemDeviceId,\r
- OUT VOID **Configuration\r
-);\r
-\r
-\r
-///\r
-/// Interface structure for the Incompatible PCI Device Support Protocol\r
-///\r
-struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL {\r
- ///\r
- /// Returns a list of ACPI resource descriptors that detail any special\r
- /// resource configuration requirements if the specified device is a recognized\r
- /// incompatible PCI device.\r
- ///\r
- EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE CheckDevice;\r
-};\r
-\r
-extern EFI_GUID gEfiIncompatiblePciDeviceSupportProtocolGuid;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- This file declares Pci Host Bridge Resource Allocation Protocol which \r
- Provides the basic interfaces to abstract a PCI host bridge resource allocation. \r
- This protocol is mandatory if the system includes PCI devices.\r
- \r
- Copyright (c) 2007 - 2009, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- @par Revision Reference:\r
- This protocol is defined in Framework of EFI Pci Host Bridge Resource Allocation Protocol Spec\r
- Version 0.9\r
-\r
-**/\r
-\r
-#ifndef _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
-#define _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
-\r
-#include <Protocol/PciRootBridgeIo.h>\r
-\r
-#define EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GUID \\r
- { 0xCF8034BE, 0x6768, 0x4d8b, {0xB7,0x39,0x7C,0xCE,0x68,0x3A,0x9F,0xBE }}\r
-\r
-\r
-typedef struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL;\r
-\r
-\r
-//\r
-// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES\r
-//\r
-\r
-/// If this bit is set, then the PCI Root Bridge does not\r
-/// support separate windows for Non-prefetchable and Prefetchable\r
-/// memory. A PCI bus driver needs to include requests for Prefetchable\r
-/// memory in the Non-prefetchable memory pool.\r
-///\r
-#define EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM 1\r
-\r
-///\r
-/// If this bit is set, then the PCI Root Bridge supports\r
-/// 64 bit memory windows. If this bit is not set,\r
-/// the PCI bus driver needs to include requests for 64 bit\r
-/// memory address in the corresponding 32 bit memory pool.\r
-///\r
-#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE 2\r
-\r
-typedef UINT64 EFI_RESOURCE_ALLOCATION_STATUS;\r
-\r
-///\r
-/// The request of this resource type could be fulfilled.\r
-///\r
-#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
-\r
-///\r
-/// The request of this resource type could not be fulfilled for its\r
-/// absence in the host bridge resource pool.\r
-///\r
-#define EFI_RESOURCE_NOT_SATISFIED 0xFFFFFFFFFFFFFFFFULL\r
-\r
-//\r
-// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE\r
-//\r
-typedef enum {\r
- ///\r
- /// Reset the host bridge PCI apertures and internal data structures.\r
- /// PCI enumerator should issue this notification before starting fresh\r
- /// enumeration process. Enumeration cannot be restarted after sending\r
- /// any other notification such as EfiPciHostBridgeBeginBusAllocation.\r
- ///\r
- EfiPciHostBridgeBeginEnumeration,\r
-\r
- ///\r
- /// The bus allocation phase is about to begin. No specific action\r
- /// is required here. This notification can be used to perform any\r
- /// chipset specific programming. \r
- ///\r
- EfiPciHostBridgeBeginBusAllocation,\r
-\r
- ///\r
- /// The bus allocation and bus programming phase is complete. No specific\r
- /// action is required here. This notification can be used to perform any\r
- /// chipset specific programming. \r
- ///\r
- EfiPciHostBridgeEndBusAllocation,\r
- \r
- ///\r
- /// The resource allocation phase is about to begin.No specific action is\r
- /// required here. This notification can be used to perform any chipset specific programming. \r
- ///\r
- EfiPciHostBridgeBeginResourceAllocation,\r
- \r
- ///\r
- /// Allocate resources per previously submitted requests for all the PCI Root\r
- /// Bridges. These resource settings are returned on the next call to\r
- /// GetProposedResources(). \r
- ///\r
- EfiPciHostBridgeAllocateResources,\r
- \r
- ///\r
- /// Program the Host Bridge hardware to decode previously allocated resources\r
- /// (proposed resources) for all the PCI Root Bridges.\r
- ///\r
- EfiPciHostBridgeSetResources,\r
- \r
- ///\r
- /// De-allocate previously allocated resources previously for all the PCI\r
- /// Root Bridges and reset the I/O and memory apertures to initial state. \r
- ///\r
- EfiPciHostBridgeFreeResources,\r
- \r
- ///\r
- /// The resource allocation phase is completed. No specific action is required\r
- /// here. This notification can be used to perform any chipset specific programming. \r
- ///\r
- EfiPciHostBridgeEndResourceAllocation\r
-} EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE;\r
-\r
-///\r
-/// Definitions of 2 notification points.\r
-///\r
-typedef enum {\r
- ///\r
- /// This notification is only applicable to PCI-PCI bridges and\r
- /// indicates that the PCI enumerator is about to begin enumerating\r
- /// the bus behind the PCI-PCI Bridge. This notification is sent after\r
- /// the primary bus number, the secondary bus number and the subordinate\r
- /// bus number registers in the PCI-PCI Bridge are programmed to valid\r
- /// (not necessary final) values\r
- ///\r
- EfiPciBeforeChildBusEnumeration,\r
-\r
- ///\r
- /// This notification is sent before the PCI enumerator probes BAR registers\r
- /// for every valid PCI function. \r
- ///\r
- EfiPciBeforeResourceCollection\r
-} EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE;\r
-\r
-/**\r
- These are the notifications from the PCI bus driver that it is about to enter a certain phase of the PCI \r
- enumeration process.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
- instance.\r
- @param Phase The phase during enumeration\r
-\r
- @retval EFI_SUCCESS The notification was accepted without any errors.\r
- @retval EFI_INVALID_PARAMETER The Phase is invalid.\r
- @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error \r
- is valid for a Phase of EfiPciHostBridgeAllocateResources if \r
- SubmitResources() has not been called for one or more \r
- PCI root bridges before this call.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid for \r
- a Phase of EfiPciHostBridgeSetResources.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
- This error is valid for a Phase of EfiPciHostBridgeAllocateResources\r
- if the previously submitted resource requests cannot be fulfilled or were only \r
- partially fulfilled\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE)(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
- );\r
-\r
-\r
-/**\r
- Returns the device handle of the next PCI root bridge that is associated with this host bridge.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
- instance.\r
- @param RootBridgeHandle Returns the device handle of the next PCI root bridge. On input, it holds the \r
- RootBridgeHandle that was returned by the most recent call to \r
- GetNextRootBridge(). If RootBridgeHandle is NULL on input, the handle \r
- for the first PCI root bridge is returned.\r
-\r
- @retval EFI_SUCCESS The requested attribute information was returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was returned \r
- on a previous call to GetNextRootBridge().\r
- @retval EFI_NOT_FOUND There are no more PCI root bridge device handles.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE)(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN OUT EFI_HANDLE *RootBridgeHandle\r
- );\r
-\r
-\r
-/**\r
- Returns the allocation attributes of a PCI root bridge.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
- instance.\r
- @param RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested.\r
- @param Attribute The pointer to attributes of the PCI root bridge.\r
-\r
- @retval EFI_SUCCESS The requested attribute information was returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Attributes is NULL.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES)(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT UINT64 *Attributes\r
- );\r
-\r
-\r
-/**\r
- Sets up the specified PCI root bridge for the bus enumeration process.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
- instance.\r
- @param RootBridgeHandle The PCI root bridge to be set up.\r
- @param Configuration Pointer to the pointer to the PCI bus resource descriptor.\r
-\r
- @retval EFI_SUCCESS The PCI root bridge was set up and the bus range was returned in \r
- Configuration.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION)(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
- );\r
-\r
-\r
-/**\r
- Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- instance. \r
- @param RootBridgeHandle The PCI root bridge whose bus range is to be programmed.\r
- @param Configuration The pointer to the PCI bus resource descriptor..\r
-\r
- @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Configuration is NULL\r
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) \r
- resource descriptor.\r
- @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource\r
- descriptor.\r
- @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI (2.0 & 3.0) resource \r
- descriptors other than bus descriptors.\r
- @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource \r
- descriptors.\r
- @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS)(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
- );\r
-\r
-\r
-/**\r
- Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
- instance.\r
- @param RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being \r
- submitted.\r
- @param Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
-\r
- @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were \r
- accepted.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) \r
- resource descriptor.\r
- @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource \r
- types that are not supported by this PCI root bridge. This error will \r
- happen if the caller did not combine resources according to \r
- Attributes that were returned by GetAllocAttributes().\r
- @retval EFI_INVALID_PARAMETER "Address Range Maximum" is invalid.\r
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
- \r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES)(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
- );\r
-\r
-\r
-/**\r
- Returns the proposed resource settings for the specified PCI root bridge.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
- instance.\r
- @param RootBridgeHandle The PCI root bridge handle.\r
- @param Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
-\r
- @retval EFI_SUCCESS The requested parameters were returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES)(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
- );\r
-\r
-\r
-\r
-/**\r
- Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various \r
- stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual \r
- PCI controllers before enumeration.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param RootBridgeHandle The associated PCI root bridge handle.\r
- @param PciAddress The address of the PCI device on the PCI bus.\r
- @param Phase The phase of the PCI device enumeration.\r
-\r
- @retval EFI_SUCCESS The requested parameters were returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in \r
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator \r
- should not enumerate this device, including its child devices if it is \r
- a PCI-to-PCI bridge.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER)(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
- );\r
-\r
-///\r
-/// Provides the basic interfaces to abstract a PCI host bridge resource allocation.\r
-///\r
-struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL {\r
- ///\r
- /// The notification from the PCI bus enumerator that it is about to enter\r
- /// a certain phase during the enumeration process.\r
- ///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE NotifyPhase;\r
- \r
- ///\r
- /// Retrieves the device handle for the next PCI root bridge that is produced by the\r
- /// host bridge to which this instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached. \r
- ///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE GetNextRootBridge;\r
- \r
- ///\r
- /// Retrieves the allocation-related attributes of a PCI root bridge.\r
- ///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES GetAllocAttributes;\r
- \r
- ///\r
- /// Sets up a PCI root bridge for bus enumeration.\r
- ///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION StartBusEnumeration;\r
- \r
- ///\r
- /// Sets up the PCI root bridge so that it decodes a specific range of bus numbers.\r
- ///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS SetBusNumbers;\r
- \r
- ///\r
- /// Submits the resource requirements for the specified PCI root bridge.\r
- ///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES SubmitResources;\r
- \r
- ///\r
- /// Returns the proposed resource assignment for the specified PCI root bridges.\r
- ///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES GetProposedResources;\r
- \r
- ///\r
- /// Provides hooks from the PCI bus driver to every PCI controller\r
- /// (device/function) at various stages of the PCI enumeration process that\r
- /// allow the host bridge driver to preinitialize individual PCI controllers\r
- /// before enumeration. \r
- ///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER PreprocessController;\r
-};\r
-\r
-extern EFI_GUID gEfiPciHostBridgeResourceAllocationProtocolGuid;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- This file declares EFI PCI Hot Plug Init Protocol.\r
- This protocol provides the necessary functionality to initialize the Hot Plug Controllers (HPCs) and\r
- the buses that they control. This protocol also provides information regarding resource padding.\r
-\r
- Copyright (c) 2007 - 2009, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- @par Revision Reference:\r
- This protocol is defined in Framework of EFI Hot Plug Pci Initialization Protocol Spec\r
- Version 0.9\r
-\r
-**/\r
-\r
-#ifndef _EFI_PCI_HOT_PLUG_INIT_H_\r
-#define _EFI_PCI_HOT_PLUG_INIT_H_\r
-\r
-\r
-///\r
-/// Global ID for the PCI Hot Plug Protocol\r
-///\r
-#define EFI_PCI_HOT_PLUG_INIT_PROTOCOL_GUID \\r
- { \\r
- 0xaa0e8bc1, 0xdabc, 0x46b0, {0xa8, 0x44, 0x37, 0xb8, 0x16, 0x9b, 0x2b, 0xea } \\r
- }\r
-\r
-typedef struct _EFI_PCI_HOT_PLUG_INIT_PROTOCOL EFI_PCI_HOT_PLUG_INIT_PROTOCOL;\r
-\r
-///\r
-/// Current state of an HPC\r
-///\r
-typedef UINT16 EFI_HPC_STATE;\r
-\r
-///\r
-/// The HPC initialization function was called and the HPC completed \r
-/// initialization, but it was not enabled for some reason. The HPC may be \r
-/// disabled in hardware, or it may be disabled due to user preferences, \r
-/// hardware failure, or other reasons. No resource padding is required.\r
-///\r
-#define EFI_HPC_STATE_INITIALIZED 0x01\r
-\r
-///\r
-/// The HPC initialization function was called, the HPC completed \r
-/// initialization, and it was enabled. Resource padding is required.\r
-///\r
-#define EFI_HPC_STATE_ENABLED 0x02\r
-\r
-///\r
-/// Location definition for PCI Hot Plug Controller\r
-///\r
-typedef struct{\r
- ///\r
- /// The device path to the Root HPC\r
- ///\r
- EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath;\r
- ///\r
- /// The device path to the Hot Plug Bus (HPB) that is controlled by \r
- /// the root HPC.\r
- ///\r
- EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath;\r
-} EFI_HPC_LOCATION;\r
-\r
-\r
-///\r
-/// Describes how resource padding should be applied\r
-///\r
-typedef enum{\r
- EfiPaddingPciBus,\r
- EfiPaddingPciRootBridge\r
-} EFI_HPC_PADDING_ATTRIBUTES;\r
-\r
-/**\r
- Returns a list of root Hot Plug Controllers (HPCs) that require initialization\r
- during the boot process.\r
-\r
- This procedure returns a list of root HPCs. The PCI bus driver must initialize these controllers \r
- during the boot process. The PCI bus driver may or may not be able to detect these HPCs. If the \r
- platform includes a PCI-to-CardBus bridge, it can be included in this list if it requires initialization. \r
- The HpcList must be self consistent. An HPC cannot control any of its parent buses. Only one HPC \r
- can control a PCI bus. Because this list includes only root HPCs, no HPC in the list can be a child of \r
- another HPC. This policy must be enforced by the EFI_PCI_HOT_PLUG_INIT_PROTOCOL. \r
- The PCI bus driver may not check for such invalid conditions. \r
- The callee allocates the buffer HpcList\r
-\r
- @param This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.\r
- @param HpcCount The number of root HPCs that were returned.\r
- @param HpcList The list of root HPCs. HpcCount defines the number of\r
- elements in this list.\r
-\r
- @retval EFI_SUCCESS HpcList was returned.\r
- @retval EFI_OUT_OF_RESOURCES HpcList was not returned due to insufficient resources.\r
- @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_GET_ROOT_HPC_LIST)(\r
- IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r
- OUT UINTN *HpcCount,\r
- OUT EFI_HPC_LOCATION **HpcList\r
-);\r
-\r
-/**\r
- Initializes one root Hot Plug Controller (HPC). This process may causes\r
- initialization of its subordinate buses.\r
- \r
- This function initializes the specified HPC. At the end of initialization, the hot-plug slots or sockets \r
- (controlled by this HPC) are powered and are connected to the bus. All the necessary registers in the \r
- HPC are set up. For a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set up \r
- are defined in the PCI Standard Hot Plug Controller and Subsystem Specification.\r
-\r
- @param This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.\r
- @param HpcDevicePath The device path to the HPC that is being initialized.\r
- @param HpcPciAddress The address of the HPC function on the PCI bus.\r
- @param Event The event that should be signaled when the HPC initialization\r
- is complete.\r
- @param HpcState The state of the HPC hardware. The state is EFI_HPC_STATE_INITIALIZED\r
- or EFI_HPC_STATE_ENABLED.\r
-\r
- @retval EFI_SUCCESS If Event is NULL, the specific HPC was successfully\r
- initialized. If Event is not NULL, Event will be signaled at a later time\r
- when initialization is complete.\r
- @retval EFI_UNSUPPORTED This instance of EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r
- does not support the specified HPC.\r
- @retval EFI_OUT_OF_RESOURCES Initialization failed due to insufficient\r
- resources.\r
- @retval EFI_INVALID_PARAMETER HpcState is NULL.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_INITIALIZE_ROOT_HPC)(\r
- IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r
- IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,\r
- IN UINT64 HpcPciAddress,\r
- IN EFI_EVENT Event, OPTIONAL\r
- OUT EFI_HPC_STATE *HpcState\r
-);\r
-\r
-/**\r
- Returns the resource padding that is required by the PCI bus that is controlled\r
- by the specified Hot Plug Controller (HPC).\r
-\r
- This function returns the resource padding that is required by the PCI bus that is controlled by the \r
- specified HPC. This member function is called for all the root HPCs and nonroot HPCs that are \r
- detected by the PCI bus enumerator. This function will be called before PCI resource allocation is \r
- completed. This function must be called after all the root HPCs, with the possible exception of a \r
- PCI-to-CardBus bridge, have completed initialization.\r
-\r
- @param This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.\r
- @param HpcDevicePath The device path to the HPC.\r
- @param HpcPciAddress The address of the HPC function on the PCI bus.\r
- @param HpcState The state of the HPC hardware.\r
- @param Padding The amount of resource padding that is required by the\r
- PCI bus under the control of the specified HPC.\r
- @param Attributes Describes how padding is accounted for. The padding\r
- is returned in the form of ACPI 2.0 resource descriptors.\r
-\r
- @retval EFI_SUCCESS The resource padding was successfully returned.\r
- @retval EFI_UNSUPPORTED This instance of the EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r
- does not support the specified HPC.\r
- @retval EFI_NOT_READY This function was called before HPC initialization is complete.\r
- @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NULL.\r
- @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Padding\r
- cannot be allocated due to insufficient resources.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_GET_HOT_PLUG_PADDING)(\r
- IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r
- IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,\r
- IN UINT64 HpcPciAddress,\r
- OUT EFI_HPC_STATE *HpcState,\r
- OUT VOID **Padding,\r
- OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes\r
-);\r
-\r
-\r
-//\r
-// Prototypes for the PCI Hot Plug Init Protocol\r
-//\r
-\r
-///\r
-/// This protocol provides the necessary functionality to initialize the\r
-/// Hot Plug Controllers (HPCs) and the buses that they control. This protocol\r
-/// also provides information regarding resource padding.\r
-///\r
-struct _EFI_PCI_HOT_PLUG_INIT_PROTOCOL {\r
- ///\r
- /// Returns a list of root HPCs and the buses that they control.\r
- ///\r
- EFI_GET_ROOT_HPC_LIST GetRootHpcList;\r
- \r
- ///\r
- /// Initializes the specified root HPC.\r
- ///\r
- EFI_INITIALIZE_ROOT_HPC InitializeRootHpc;\r
- \r
- ///\r
- /// Returns the resource padding that is required by the HPC.\r
- ///\r
- EFI_GET_HOT_PLUG_PADDING GetResourcePadding;\r
-};\r
-\r
-extern EFI_GUID gEfiPciHotPlugInitProtocolGuid;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- This file declares PlatfromOpRom protocols which provides the interface between \r
- the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific \r
- driver to describe the unique features of a platform. This\r
- protocol is optional.\r
- \r
- Copyright (c) 2007 - 2009, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- @par Revision Reference:\r
- This protocol is defined in PCI Platform Support Specification\r
- Version 0.9\r
-\r
-**/\r
-\r
-#ifndef _PCI_PLATFORM_H_\r
-#define _PCI_PLATFORM_H_\r
-\r
-#include <Protocol/PciHostBridgeResourceAllocation.h>\r
-\r
-//\r
-// Protocol for GUID.\r
-//\r
-\r
-#define EFI_PCI_PLATFORM_PROTOCOL_GUID \\r
-{ 0x7d75280, 0x27d4, 0x4d69, {0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41} }\r
-\r
-typedef struct _EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_PLATFORM_PROTOCOL;\r
-\r
-typedef UINT32 EFI_PCI_PLATFORM_POLICY;\r
-\r
-//\r
-// There are 4 legal combinations of following bit values:\r
-// EFI_RESERVE_NONE_IO_ALIAS,\r
-// EFI_RESERVE_ISA_IO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS,\r
-// EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS,\r
-// EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS\r
-//\r
-#define EFI_RESERVE_NONE_IO_ALIAS 0x0000\r
-#define EFI_RESERVE_ISA_IO_ALIAS 0x0001\r
-#define EFI_RESERVE_ISA_IO_NO_ALIAS 0x0002\r
-#define EFI_RESERVE_VGA_IO_ALIAS 0x0004\r
-#define EFI_RESERVE_VGA_IO_NO_ALIAS 0x0008\r
-\r
-///\r
-/// EFI_PCI_CHIPSET_EXECUTION_PHASE is used to call a platform protocol and execute\r
-/// platform-specific code.\r
-///\r
-typedef enum {\r
- ///\r
- /// The phase that indicates the entry point to the PCI Bus Notify phase. This\r
- /// platform hook is called before the PCI bus driver calls the\r
- /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.\r
- ///\r
- ChipsetEntry,\r
- ///\r
- /// The phase that indicates the exit point to the Chipset Notify phase before\r
- /// returning to the PCI Bus Driver Notify phase. This platform hook is called after\r
- /// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- /// driver.\r
- ///\r
- ChipsetExit,\r
- MaximumChipsetPhase\r
-} EFI_PCI_CHIPSET_EXECUTION_PHASE;\r
-\r
-\r
-/**\r
- The notification from the PCI bus enumerator to the platform that it is\r
- about to enter a certain phase during the enumeration process.\r
-\r
- The PlatformNotify() function can be used to notify the platform driver so that\r
- it can perform platform-specific actions. No specific actions are required.\r
- Eight notification points are defined at this time. More synchronization points\r
- may be added as required in the future. The PCI bus driver calls the platform driver\r
- twice for every Phase-once before the PCI Host Bridge Resource Allocation Protocol\r
- driver is notified, and once after the PCI Host Bridge Resource Allocation Protocol\r
- driver has been notified.\r
- This member function may not perform any error checking on the input parameters. It\r
- also does not return any error codes. If this member function detects any error condition,\r
- it needs to handle those errors on its own because there is no way to surface any\r
- errors to the caller.\r
-\r
- @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
- @param HostBridge The handle of the host bridge controller.\r
- @param Phase The phase of the PCI bus enumeration.\r
- @param ChipsetPhase Defines the execution phase of the PCI chipset driver.\r
-\r
- @retval EFI_SUCCESS The function completed successfully.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_PLATFORM_PHASE_NOTIFY)(\r
- IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
- IN EFI_HANDLE HostBridge,\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,\r
- IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r
-);\r
-\r
-\r
-/**\r
- The notification from the PCI bus enumerator to the platform for each PCI\r
- controller at several predefined points during PCI controller initialization.\r
-\r
- The PlatformPrepController() function can be used to notify the platform driver so that\r
- it can perform platform-specific actions. No specific actions are required.\r
- Several notification points are defined at this time. More synchronization points may be\r
- added as required in the future. The PCI bus driver calls the platform driver twice for\r
- every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver\r
- is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has\r
- been notified.\r
- This member function may not perform any error checking on the input parameters. It also\r
- does not return any error codes. If this member function detects any error condition, it\r
- needs to handle those errors on its own because there is no way to surface any errors to\r
- the caller.\r
-\r
- @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
- @param HostBridge The associated PCI host bridge handle.\r
- @param RootBridge The associated PCI root bridge handle.\r
- @param PciAddress The address of the PCI device on the PCI bus.\r
- @param Phase The phase of the PCI controller enumeration.\r
- @param ChipsetPhase Defines the execution phase of the PCI chipset driver.\r
-\r
- @retval EFI_SUCCESS The function completed successfully.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER)(\r
- IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
- IN EFI_HANDLE HostBridge,\r
- IN EFI_HANDLE RootBridge,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,\r
- IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r
-);\r
-\r
-\r
-/**\r
- Retrieves the platform policy regarding enumeration.\r
-\r
- The GetPlatformPolicy() function retrieves the platform policy regarding PCI\r
- enumeration. The PCI bus driver and the PCI Host Bridge Resource Allocation Protocol\r
- driver can call this member function to retrieve the policy.\r
-\r
- @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
- @param PciPolicy The platform policy with respect to VGA and ISA aliasing.\r
-\r
- @retval EFI_SUCCESS The function completed successfully.\r
- @retval EFI_INVALID_PARAMETER PciPolicy is NULL.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_PLATFORM_GET_PLATFORM_POLICY)(\r
- IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
- OUT EFI_PCI_PLATFORM_POLICY *PciPolicy\r
-);\r
-\r
-\r
-/**\r
- Gets the PCI device's option ROM from a platform-specific location.\r
-\r
- The GetPciRom() function gets the PCI device's option ROM from a platform-specific location.\r
- The option ROM will be loaded into memory. This member function is used to return an image\r
- that is packaged as a PCI 2.2 option ROM. The image may contain both legacy and EFI option\r
- ROMs. See the UEFI 2.0 Specification for details. This member function can be used to return\r
- option ROM images for embedded controllers. Option ROMs for embedded controllers are typically\r
- stored in platform-specific storage, and this member function can retrieve it from that storage\r
- and return it to the PCI bus driver. The PCI bus driver will call this member function before\r
- scanning the ROM that is attached to any controller, which allows a platform to specify a ROM\r
- image that is different from the ROM image on a PCI card.\r
-\r
- @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
- @param PciHandle The handle of the PCI device.\r
- @param RomImage If the call succeeds, the pointer to the pointer to the option ROM image.\r
- Otherwise, this field is undefined. The memory for RomImage is allocated\r
- by EFI_PCI_PLATFORM_PROTOCOL.GetPciRom() using the EFI Boot Service AllocatePool().\r
- It is the caller's responsibility to free the memory using the EFI Boot Service\r
- FreePool(), when the caller is done with the option ROM.\r
- @param RomSize If the call succeeds, a pointer to the size of the option ROM size. Otherwise,\r
- this field is undefined.\r
-\r
- @retval EFI_SUCCESS The option ROM was available for this device and loaded into memory.\r
- @retval EFI_NOT_FOUND No option ROM was available for this device.\r
- @retval EFI_OUT_OF_RESOURCES No memory was available to load the option ROM.\r
- @retval EFI_DEVICE_ERROR An error occurred in getting the option ROM.\r
-\r
-**/\r
-typedef\r
-EFI_STATUS\r
-(EFIAPI *EFI_PCI_PLATFORM_GET_PCI_ROM)(\r
- IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
- IN EFI_HANDLE PciHandle,\r
- OUT VOID **RomImage,\r
- OUT UINTN *RomSize\r
-);\r
-\r
-///\r
-/// This protocol provides the interface between the PCI bus driver/PCI Host\r
-/// Bridge Resource Allocation driver and a platform-specific driver to describe\r
-/// the unique features of a platform.\r
-///\r
-struct _EFI_PCI_PLATFORM_PROTOCOL {\r
- ///\r
- /// The notification from the PCI bus enumerator to the platform that it is about to \r
- /// enter a certain phase during the enumeration process.\r
- ///\r
- EFI_PCI_PLATFORM_PHASE_NOTIFY PlatformNotify;\r
- ///\r
- /// The notification from the PCI bus enumerator to the platform for each PCI \r
- /// controller at several predefined points during PCI controller initialization.\r
- /// \r
- EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController;\r
- /// \r
- /// Retrieves the platform policy regarding enumeration.\r
- ///\r
- EFI_PCI_PLATFORM_GET_PLATFORM_POLICY GetPlatformPolicy;\r
- ///\r
- /// Gets the PCI device\92s option ROM from a platform-specific location.\r
- ///\r
- EFI_PCI_PLATFORM_GET_PCI_ROM GetPciRom;\r
-};\r
-\r
-extern EFI_GUID gEfiPciPlatformProtocolGuid;\r
-\r
-#endif\r
SmmLib|Include/Library/SmmLib.h\r
\r
[Guids]\r
- ## EdkCompatibilityPkg/Foundation/Framework/Guid/AcpiTableStorage/AcpiTableStorage.h\r
- gEfiAcpiTableStorageGuid = { 0x7e374e25, 0x8e01, 0x4fee, { 0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd }}\r
- \r
## Include/Guid/DataHubRecords.h\r
gEfiCacheSubClassGuid = { 0x7f0013a7, 0xdc79, 0x4b22, { 0x80, 0x99, 0x11, 0xf7, 0x5f, 0xdc, 0x82, 0x9d }}\r
\r
## Include/Guid/FirmwareFileSystem.h\r
gEfiFirmwareFileSystemGuid = { 0x7A9354D9, 0x0468, 0x444a, {0x81, 0xCE, 0x0B, 0xF6, 0x17, 0xD8, 0x90, 0xDF }}\r
\r
- ## Include/Guid/BlockIo.h\r
+ ## Include/Guid/BlockIo.h\r
gEfiPeiIdeBlockIoPpiGuid = { 0x0964e5b22, 0x6459, 0x11d2, { 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b }}\r
\r
- ## Include/Guid/BlockIo.h\r
+ ## Include/Guid/BlockIo.h\r
gEfiPei144FloppyBlockIoPpiGuid = { 0xda6855bd, 0x07b7, 0x4c05, { 0x9e, 0xd8, 0xe2, 0x59, 0xfd, 0x36, 0x0e, 0x22 }}\r
\r
[Protocols]\r
## Include/Protocol/Legacy8259.h\r
gEfiLegacy8259ProtocolGuid = { 0x38321dba, 0x4fe0, 0x4e17, { 0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1 }}\r
\r
- ## Include\Protocol\CpuIo.h\r
+ ## Include/Protocol/CpuIo.h\r
gEfiCpuIoProtocolGuid = { 0xB0732526, 0x38C8, 0x4b40, { 0x88, 0x77, 0x61, 0xc7, 0xb0, 0x6a, 0xac, 0x45 }}\r
\r
- ## Include/Protocol/CpuIo.h\r
+ ## Include/Protocol/DataHub.h\r
gEfiDataHubProtocolGuid = { 0xae80d021, 0x618e, 0x11d4, { 0xbc, 0xd7, 0x00, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}\r
\r
## Include/Protocol/FirmwareVolume.h\r
## Include/Protocol/SectionExtraction.h\r
gEfiSectionExtractionProtocolGuid = { 0x448F5DA4, 0x6DD7, 0x4FE1, { 0x93, 0x07, 0x69, 0x22, 0x41, 0x92, 0x21, 0x5D }}\r
\r
- ## Include/Protocol/PciHotPlugInit.h\r
- gEfiPciHotPlugInitProtocolGuid = { 0xaa0e8bc1, 0xdabc, 0x46b0, { 0xa8, 0x44, 0x37, 0xb8, 0x16, 0x9b, 0x2b, 0xea }}\r
- \r
## Include/Protocol/FrameworkHii.h\r
gEfiHiiProtocolGuid = { 0xd7ad636e, 0xb997, 0x459b, { 0xbf, 0x3f, 0x88, 0x46, 0x89, 0x79, 0x80, 0xe1 }}\r
\r
## Include/Protocol/FrameworkMpService.h \r
gFrameworkEfiMpServiceProtocolGuid = { 0xf33261e7, 0x23cb, 0x11d5, {0xbd, 0x5c, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81}}\r
\r
- ## Include/Protocol/IdeControllerInit.h\r
- gEfiIdeControllerInitProtocolGuid = { 0xa1e37052, 0x80d9, 0x4e65, { 0xa3, 0x17, 0x3e, 0x9a, 0x55, 0xc4, 0x3e, 0xc9 }}\r
- \r
- ## Include/Protocol/PciHostBridgeResourceAllocation.h\r
- gEfiPciHostBridgeResourceAllocationProtocolGuid = { 0xCF8034BE, 0x6768, 0x4d8b, { 0xb7, 0x39, 0x7c, 0xce, 0x68, 0x3a, 0x9f, 0xbe }}\r
- \r
- ## Include/Protocol/PciPlatform.h\r
- gEfiPciPlatformProtocolGuid = { 0x07d75280, 0x27d4, 0x4d69, { 0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41 }}\r
- \r
- ## Include/Protocol/IncompatiblePciDeviceSupport.h\r
- gEfiIncompatiblePciDeviceSupportProtocolGuid = { 0xeb23f55a, 0x7863, 0x4ac2, { 0x8d, 0x3d, 0x95, 0x65, 0x35, 0xde, 0x03, 0x75 }}\r
- \r
## Include/Protocol/SmmBase.h\r
gEfiSmmBaseProtocolGuid = { 0x1390954D, 0xda95, 0x4227, { 0x93, 0x28, 0x72, 0x82, 0xc2, 0x17, 0xda, 0xa8 }}\r
\r
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