UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr4" with PatchInstructionX86()

Unlike "gSmmCr3" in the previous patch, "gSmmCr4" is not only used for
machine code patching, but also as a means to communicate the initial CR4
value from SmmRelocateBases() to InitSmmS3ResumeState(). In other words,
the last four bytes of the "mov eax, Cr4Value" instruction's binary
representation are utilized as normal data too.

In order to get rid of the DB for "mov eax, Cr4Value", we have to split
both roles, patching and data flow. Introduce the "mSmmCr4" global (SMRAM)
variable for the data flow purpose. Rename the "gSmmCr4" variable to
"gPatchSmmCr4" so that its association with PatchInstructionX86() is clear
from the declaration, change its type to X86_ASSEMBLY_PATCH_LABEL, and
patch it with PatchInstructionX86(), to the value now contained in
"mSmmCr4".

This lets us remove the binary (DB) encoding of "mov eax, Cr4Value" in
"SmmInit.nasm".

Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 554629536a5db5da465f24397289b30dd1a346b6..b4ed0a56a8146d1f287b8e59cdbba8549d99971e 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -746,7 +746,7 @@ InitSmmS3ResumeState (
 \r
     SmmS3ResumeState->SmmS3Cr0 = gSmmCr0;\r
     SmmS3ResumeState->SmmS3Cr3 = Cr3;\r
-    SmmS3ResumeState->SmmS3Cr4 = gSmmCr4;\r
+    SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;\r
 \r
     if (sizeof (UINTN) == sizeof (UINT64)) {\r
       SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index f7bb9b9a82e52f216f8e1e21cdd5f991b449eba8..bd07a6e4f53696b6af96b3b818188e598e1540bc 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -23,7 +23,7 @@ extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)\r
 \r
 global ASM_PFX(gPatchSmmCr3)\r
-global ASM_PFX(gSmmCr4)\r
+global ASM_PFX(gPatchSmmCr4)\r
 global ASM_PFX(gSmmCr0)\r
 global ASM_PFX(gSmmJmpAddr)\r
 global ASM_PFX(gSmmInitStack)\r
@@ -53,8 +53,8 @@ ASM_PFX(SmmStartup):
 ASM_PFX(gPatchSmmCr3):\r
     mov     cr3, eax\r
 o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
-    DB      0x66, 0xb8                  ; mov eax, imm32\r
-ASM_PFX(gSmmCr4): DD 0\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr4):\r
     mov     cr4, eax\r
     mov     ecx, 0xc0000080             ; IA32_EFER MSR\r
     rdmsr\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index c5b67e3dc0ce4892471d8a5818928a97d6473b64..a3fd796dba4a8d6a487f13138c133f22bda86dc6 100755 (executable)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -125,6 +125,11 @@ UINTN                    mSmmCpuSmramRangeCount;
 \r
 UINT8                    mPhysicalAddressBits;\r
 \r
+//\r
+// Control register contents saved for SMM S3 resume state initialization.\r
+//\r
+UINT32                   mSmmCr4;\r
+\r
 /**\r
   Initialize IDT to setup exception handlers for SMM.\r
 \r
@@ -407,7 +412,8 @@ SmmRelocateBases (
   //\r
   gSmmCr0 = (UINT32)AsmReadCr0 ();\r
   PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
-  gSmmCr4 = (UINT32)AsmReadCr4 ();\r
+  mSmmCr4 = (UINT32)AsmReadCr4 ();\r
+  PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r
 \r
   //\r
   // Patch GDTR for SMM base relocation\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index a01d0d76d6ff2010638b83335158278155243dcf..8202ce6f86824350b60335daa1ba65e7e676e5d3 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -310,7 +310,8 @@ extern CONST UINT8                  gcSmmInitTemplate[];
 extern CONST UINT16                 gcSmmInitSize;\r
 extern UINT32                       gSmmCr0;\r
 X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr3;\r
-extern UINT32                       gSmmCr4;\r
+extern UINT32                       mSmmCr4;\r
+X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr4;\r
 extern UINTN                        gSmmInitStack;\r
 \r
 /**\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 2df22a1f6cd1591a8aef3100d0de46c93809b731..971bd118132fc7c29ef8a83e46a84f825ef9a577 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -23,7 +23,7 @@ extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)\r
 \r
 global ASM_PFX(gPatchSmmCr3)\r
-global ASM_PFX(gSmmCr4)\r
+global ASM_PFX(gPatchSmmCr4)\r
 global ASM_PFX(gSmmCr0)\r
 global ASM_PFX(gSmmJmpAddr)\r
 global ASM_PFX(gSmmInitStack)\r
@@ -51,8 +51,8 @@ ASM_PFX(SmmStartup):
 ASM_PFX(gPatchSmmCr3):\r
     mov     cr3, eax\r
 o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
-    DB      0x66, 0xb8                   ; mov eax, imm32\r
-ASM_PFX(gSmmCr4): DD 0\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr4):\r
     or      ah,  2                      ; enable XMM registers access\r
     mov     cr4, eax\r
     mov     ecx, 0xc0000080             ; IA32_EFER MSR\r