MdePkg/BaseLib: Add stack switch related definitions for IA32
authorJian J Wang <jian.j.wang@intel.com>
Thu, 7 Dec 2017 12:14:35 +0000 (20:14 +0800)
committerStar Zeng <star.zeng@intel.com>
Fri, 8 Dec 2017 06:38:48 +0000 (14:38 +0800)
The new definitions include two structures

  IA32_TASK_STATE_SEGMENT
  IA32_TSS_DESCRIPTOR

two macros

  IA32_GDT_TYPE_TSS
  IA32_GDT_ALIGNMENT

and one API

  VOID
  EFIAPI
  AsmWriteTr (
    IN UINT16 Selector
    );

They're needed to setup task gate and interrupt stack table for stack switch.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
Reviewed-by: Jiewen.yao@intel.com
MdePkg/Include/Library/BaseLib.h
MdePkg/Library/BaseLib/BaseLib.inf
MdePkg/Library/BaseLib/Ia32/WriteTr.nasm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteTr.nasm [new file with mode: 0644]

index d33c3b6b38ea24d7336fb8a7fdc5d6a710875323..2b98af4cd17e574e1d9e66c8e743790367617e41 100644 (file)
@@ -6647,6 +6647,8 @@ typedef struct {
 #define IA32_IDT_GATE_TYPE_INTERRUPT_32  0x8E\r
 #define IA32_IDT_GATE_TYPE_TRAP_32       0x8F\r
 \r
+#define IA32_GDT_TYPE_TSS               0x9\r
+#define IA32_GDT_ALIGNMENT              8\r
 \r
 #if defined (MDE_CPU_IA32)\r
 ///\r
@@ -6663,6 +6665,70 @@ typedef union {
   UINT64  Uint64;\r
 } IA32_IDT_GATE_DESCRIPTOR;\r
 \r
+#pragma pack (1)\r
+//\r
+// IA32 Task-State Segment Definition\r
+//\r
+typedef struct {\r
+  UINT16    PreviousTaskLink;\r
+  UINT16    Reserved_2;\r
+  UINT32    ESP0;\r
+  UINT16    SS0;\r
+  UINT16    Reserved_10;\r
+  UINT32    ESP1;\r
+  UINT16    SS1;\r
+  UINT16    Reserved_18;\r
+  UINT32    ESP2;\r
+  UINT16    SS2;\r
+  UINT16    Reserved_26;\r
+  UINT32    CR3;\r
+  UINT32    EIP;\r
+  UINT32    EFLAGS;\r
+  UINT32    EAX;\r
+  UINT32    ECX;\r
+  UINT32    EDX;\r
+  UINT32    EBX;\r
+  UINT32    ESP;\r
+  UINT32    EBP;\r
+  UINT32    ESI;\r
+  UINT32    EDI;\r
+  UINT16    ES;\r
+  UINT16    Reserved_74;\r
+  UINT16    CS;\r
+  UINT16    Reserved_78;\r
+  UINT16    SS;\r
+  UINT16    Reserved_82;\r
+  UINT16    DS;\r
+  UINT16    Reserved_86;\r
+  UINT16    FS;\r
+  UINT16    Reserved_90;\r
+  UINT16    GS;\r
+  UINT16    Reserved_94;\r
+  UINT16    LDTSegmentSelector;\r
+  UINT16    Reserved_98;\r
+  UINT16    T;\r
+  UINT16    IOMapBaseAddress;\r
+} IA32_TASK_STATE_SEGMENT;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32  LimitLow:16;    ///< Segment Limit 15..00\r
+    UINT32  BaseLow:16;     ///< Base Address  15..00\r
+    UINT32  BaseMid:8;      ///< Base Address  23..16\r
+    UINT32  Type:4;         ///< Type (1 0 B 1)\r
+    UINT32  Reserved_43:1;  ///< 0\r
+    UINT32  DPL:2;          ///< Descriptor Privilege Level\r
+    UINT32  P:1;            ///< Segment Present\r
+    UINT32  LimitHigh:4;    ///< Segment Limit 19..16\r
+    UINT32  AVL:1;          ///< Available for use by system software\r
+    UINT32  Reserved_52:2;  ///< 0 0\r
+    UINT32  G:1;            ///< Granularity\r
+    UINT32  BaseHigh:8;     ///< Base Address 31..24\r
+  } Bits;\r
+  UINT64  Uint64;\r
+} IA32_TSS_DESCRIPTOR;\r
+#pragma pack ()\r
+\r
 #endif\r
 \r
 #if defined (MDE_CPU_X64)\r
@@ -6685,6 +6751,46 @@ typedef union {
   } Uint128;   \r
 } IA32_IDT_GATE_DESCRIPTOR;\r
 \r
+#pragma pack (1)\r
+//\r
+// IA32 Task-State Segment Definition\r
+//\r
+typedef struct {\r
+  UINT32    Reserved_0;\r
+  UINT64    RSP0;\r
+  UINT64    RSP1;\r
+  UINT64    RSP2;\r
+  UINT64    Reserved_28;\r
+  UINT64    IST[7];\r
+  UINT64    Reserved_92;\r
+  UINT16    Reserved_100;\r
+  UINT16    IOMapBaseAddress;\r
+} IA32_TASK_STATE_SEGMENT;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32  LimitLow:16;    ///< Segment Limit 15..00\r
+    UINT32  BaseLow:16;     ///< Base Address  15..00\r
+    UINT32  BaseMidl:8;     ///< Base Address  23..16\r
+    UINT32  Type:4;         ///< Type (1 0 B 1)\r
+    UINT32  Reserved_43:1;  ///< 0\r
+    UINT32  DPL:2;          ///< Descriptor Privilege Level\r
+    UINT32  P:1;            ///< Segment Present\r
+    UINT32  LimitHigh:4;    ///< Segment Limit 19..16\r
+    UINT32  AVL:1;          ///< Available for use by system software\r
+    UINT32  Reserved_52:2;  ///< 0 0\r
+    UINT32  G:1;            ///< Granularity\r
+    UINT32  BaseMidh:8;     ///< Base Address  31..24\r
+    UINT32  BaseHigh:32;    ///< Base Address  63..32\r
+    UINT32  Reserved_96:32; ///< Reserved\r
+  } Bits;\r
+  struct {\r
+    UINT64  Uint64;\r
+    UINT64  Uint64_1;\r
+  } Uint128;\r
+} IA32_TSS_DESCRIPTOR;\r
+#pragma pack ()\r
+\r
 #endif\r
 \r
 ///\r
@@ -8950,6 +9056,17 @@ AsmRdRand64  (
   OUT     UINT64                    *Rand\r
   );\r
 \r
+/**\r
+  Load given selector into TR register\r
+\r
+  @param[in] Selector     Task segment selector\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteTr (\r
+  IN UINT16 Selector\r
+  );\r
+\r
 #endif\r
 #endif\r
 \r
index 320ac457ea3d2668c1e71487b1bea229d6149042..fbfb0063b75f6b7fc37b20fe256437778fc5c3d5 100644 (file)
@@ -67,6 +67,8 @@
   BaseLibInternals.h\r
 \r
 [Sources.Ia32]\r
+  Ia32/WriteTr.nasm\r
+\r
   Ia32/Wbinvd.c | MSFT \r
   Ia32/WriteMm7.c | MSFT \r
   Ia32/WriteMm6.c | MSFT \r
   X64/EnableCache.asm\r
   X64/DisableCache.nasm\r
   X64/DisableCache.asm\r
+  X64/WriteTr.nasm\r
 \r
   X64/CpuBreakpoint.c | MSFT \r
   X64/WriteMsr64.c | MSFT \r
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm b/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
new file mode 100644 (file)
index 0000000..cde5a3a
--- /dev/null
@@ -0,0 +1,36 @@
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   WriteTr.nasm\r
+;\r
+; Abstract:\r
+;\r
+;   Write TR register\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; AsmWriteTr (\r
+;   UINT16 Selector\r
+;   );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmWriteTr)\r
+ASM_PFX(AsmWriteTr):\r
+    mov     eax, [esp+4]\r
+    ltr     ax\r
+    ret\r
+\r
diff --git a/MdePkg/Library/BaseLib/X64/WriteTr.nasm b/MdePkg/Library/BaseLib/X64/WriteTr.nasm
new file mode 100644 (file)
index 0000000..3bf1500
--- /dev/null
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   WriteTr.nasm\r
+;\r
+; Abstract:\r
+;\r
+;   Write TR register\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    DEFAULT REL\r
+    SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; AsmWriteTr (\r
+;   UINT16 Selector\r
+;   );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmWriteTr)\r
+ASM_PFX(AsmWriteTr):\r
+    mov     eax, ecx\r
+    ltr     ax\r
+    ret\r
+\r